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mirror of https://github.com/TomHarte/CLK.git synced 2024-11-24 10:31:15 +00:00

Updated The Mockingboard (markdown)

Thomas Harte 2024-02-15 08:56:06 -05:00
parent fe5e6f331b
commit c8e09acc7b

@ -6,8 +6,14 @@ Each AY is connected to its 6522:
* port A is connected to the AY's data pins;
* bit 0 of port B is connected to the AY's BC1;
* bit 1 of port B is connected to the AY's BDIR;
* bit 2 of port B is connected to the AY's BC2; and
* the AY's reset is active if all of bits 0, 1 and 2 are reset.
* BC2 is connected to +5v; and
* bit 2 of port B is connected to the AY's reset.
So, logically:
* BC1 is active if bit 0 is set;
* BDIR is active if bit 1 is set;
* BC2 is always active;
* reset will occur if bit 2 is reset.
The three channels from each AY are mixed together with equal volume.