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+ discussion of alternative potential Nick clocking.
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@ -8,7 +8,11 @@ Nick is the Enterprise's video chip, offering text and pixel modes at up to 8 bi
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Nick provides 57 slots per line, each slot being 16 cycles wide, for a total of 912 cycles/line. In its highest resolution mode it can output one pixel per cycle.
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It is stated to be 'phaselocked' with the PAL colour subcarrier on PAL machines; taking that to mean that 912 cycles equates to a slightly-overlong line of exactly 284 colour cycles:
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It is stated to be 'phaselocked' with the PAL colour subcarrier on PAL machines. Two possible timings to achieve this are floated in the preproduction documentation.
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### Possibility 1
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Taking that to mean that 912 cycles equates to a slightly-overlong line of exactly 284 colour cycles:
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1. each line should last 284*64/283.7516 µs = 45440000/709379 µs ≈ 64.06µs;
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2. therefore there are 1000000 / (45440000/709379) = 709379000000/45440000 = 17734475/1136 ≈ 15611.33 lines/second;
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@ -16,6 +20,18 @@ It is stated to be 'phaselocked' with the PAL colour subcarrier on PAL machines;
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That gives (1010865075/71) / 4000000 = 1010865075/284000000 = 40434603/11360000 ≈ 3.56 Nick cycles for every Z80 cycle.
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### Possibility 2
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Nick is fed with a clock rate of exactly 1/5th the PAL colour subcarrier, which drives eight separate out-of-phase internal clocks, to produce a pixel clock at 16/5ths the PAL colour subcarrier.
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That would imply a pixel clock of 16/5 * 4.43361875Mhz = 14,187,580 Hz.
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A 912-cycle line would then take 912/14187580 = 228/3546895 ≈ 64.28 µs; relative to the subcarrier, each would be 912*5/16 = 285 colour cycles long.
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#### Which is correct?
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Per its documentation, EP128Emu [prefers the former](http://www.ep128.hu/Ep_Emulator_eng.htm), or close enough, providing a table of built-in clock rates that "assume 14237536 Hz as the NICK frequency".
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### Z80 Access
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Nick marshals 64kb of memory; if the Z80 wants to access that 64kb or to access one of Nick's registers then it must wait for an access window.
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