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Add bit plane fetch orders.
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commit
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@ -1,9 +1,9 @@
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Relative to the internal counters:
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* NTSC: 262 lines, or 262/263 in interlaced mode; lines are alternately 227 and 228 cycles long;
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* PAL: 312 lines, or 312/313 in interlaced mode; lines are 227 cycles long.
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* NTSC: 262 lines, or 262/263 in interlaced mode; lines are alternately 227 and 228 slots long;
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* PAL: 312 lines, or 312/313 in interlaced mode; lines are 227 slots long.
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Each cycle being two processor clock ticks, or one NTSC-rate colour cycle — i.e. one chip RAM access window.
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Each 'slot' being two processor clock ticks, or one NTSC-rate colour cycle — i.e. one chip RAM access window.
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Fixed slot per-line cycle access breakdown:
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@ -18,9 +18,33 @@ Bitmap data fetch start time is programmable but may not begin earlier than slot
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## DMA Priority
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1. Bitplane fetching
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1. Bitplane fetching (or disk/sprite/refresh, per line region)
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2. Copper
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3. Blitter
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4. CPU
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The Blitter will yield every fourth slot if BLTPRI in DMACON is clear.
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The Blitter will yield every fourth slot if BLTPRI in DMACON is clear.
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## Bitplane Fetches
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### Low-resolution
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An eight-slot fetch pattern is followed:
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1. [unused]
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2. bit plane 4
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3. bit plane 6
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4. bit plane 2
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5. [unused]
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6. bit plane 3
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7. bit plane 5
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8. bit plane 1
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### High-resolution
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Four-slot fetch pattern:
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1. bit plane 4
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2. bit plane 2
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3. bit plane 3
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4. bit plane 1
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