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Added MOD instruction. Some refactoring.
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Russell-S-Harper
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@ -514,25 +514,7 @@ _8 PLA ; reset the sign of register p
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_9 JMP _TRFDR ; pull X, transfer RD to r register, let it handle the return
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.)
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_CMPDC .( ; compare D to C, return result in status
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LDA _RD+3
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CMP _RC+3
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BCC _1 ; definitely less
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BNE _1 ; definitely greater
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LDA _RD+2
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CMP _RC+2
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BCC _1 ; definitely less
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BNE _1 ; definitely greater
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LDA _RD+1
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CMP _RC+1
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BCC _1 ; definitely less
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BNE _1 ; definitely greater
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LDA _RD
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CMP _RC
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_1 RTS
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.)
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_DIV .( ; DIV r pq dr pq Rr <- Rp / Rq - division
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_INTDM .( ; initialize for DIV and MOD, returns sign of result in A
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TXA
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PHA ; save r register for later
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JSR _GETPQ
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@ -578,42 +560,32 @@ _2 LDA _R0,X ; copy p to RD
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STA _R0+1,X
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STA _R0+2,X
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STA _R0+3,X
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LDA _RD+3 ; save sign of quotient
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LDA _RD+3 ; get sign of result
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EOR _RC+3
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AND #_MSK_O
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PHA
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LDY #_RD-_R0 ; absolute value of register p saved in D
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JSR _ABSRY
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LDY #_RC-_R0 ; absolute value of register q saved in C
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JSR _ABSRY
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_3 JSR _CMPDC ; is D < C?
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BCC _4 ; yes, continue
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BEQ _5 ; D = C
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ASL _RC ; RC *= 2
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ROL _RC+1
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ROL _RC+2
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ROL _RC+3
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ASL _RB ; RB *= 2
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ROL _RB+1
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ROL _RB+2
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ROL _RB+3
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BCC _3
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; carry is set, means a real overflow condition
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LDA #$FF ; set to the maximum
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STA _R0,X
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STA _R0+1,X
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STA _R0+2,X
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LDA #_MAX_V|_F_O
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STA _R0+3,X
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JMP _9
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_4 LDA _RB ; is RB > 0?
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ORA _RB+1
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ORA _RB+2
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ORA _RB+3
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BEQ _7 ; no, done
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JSR _CMPDC ; is D >= C?
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BCC _6 ; no, skip subtraction
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_5 SEC ; RD -= RC
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RTS
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.)
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_CMPDC .( ; compare D to C, return result in status
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LDA _RD+3
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CMP _RC+3
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BCC _1 ; definitely less
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BNE _1 ; definitely greater
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LDA _RD+2
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CMP _RC+2
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BCC _1 ; definitely less
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BNE _1 ; definitely greater
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LDA _RD+1
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CMP _RC+1
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BCC _1 ; definitely less
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BNE _1 ; definitely greater
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LDA _RD
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CMP _RC
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_1 RTS
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.)
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_UPDDM .( ; update DIV and MOD
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SEC ; RD -= RC
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LDA _RD
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SBC _RC
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STA _RD
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@ -639,12 +611,23 @@ _5 SEC ; RD -= RC
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LDA _R0+3,X
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ADC _RB+3
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STA _R0+3,X
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LDA _RD ; is RD > 0?
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ORA _RD+1
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ORA _RD+2
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ORA _RD+3
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BEQ _7 ; no, done
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_6 CLC ; RC /= 2
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RTS
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.)
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_SHUDM .( ; shift up for DIV and MOD
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ASL _RC ; RC *= 2
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ROL _RC+1
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ROL _RC+2
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ROL _RC+3
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ASL _RB ; RB *= 2
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ROL _RB+1
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ROL _RB+2
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ROL _RB+3
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RTS
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.)
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_SHDDM .( ; shift down for DIV and MOD
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CLC ; RC /= 2
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ROR _RC+3
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ROR _RC+2
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ROR _RC+1
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@ -654,6 +637,43 @@ _6 CLC ; RC /= 2
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ROR _RB+2
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ROR _RB+1
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ROR _RB
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RTS
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.)
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_DIV .( ; DIV r pq dr pq Rr <- Rp / Rq - division
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JSR _INTDM ; initialize
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PHA ; save sign of result
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LDY #_RD-_R0 ; absolute value of register p saved in D
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JSR _ABSRY
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LDY #_RC-_R0 ; absolute value of register q saved in C
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JSR _ABSRY
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_3 JSR _CMPDC ; is D < C?
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BCC _4 ; yes, continue
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BEQ _5 ; D = C
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JSR _UPDDM ; confirmed D > C, so RD -= RC, RX += RB
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JSR _SHUDM ; shift up
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BCC _3 ; if carry is set, means a really bad overflow condition
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LDA #$FF ; set to the maximum
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STA _R0,X
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STA _R0+1,X
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STA _R0+2,X
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LDA #_MAX_V|_F_O
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STA _R0+3,X
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BNE _9
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_4 LDA _RB ; is RB > 0?
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ORA _RB+1
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ORA _RB+2
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ORA _RB+3
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BEQ _7 ; no, done
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JSR _CMPDC ; is D >= C?
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BCC _6 ; no, skip subtraction
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_5 JSR _UPDDM ; RD -= RC, RX += RB
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LDA _RD ; is RD > 0?
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ORA _RD+1
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ORA _RD+2
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ORA _RD+3
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BEQ _7 ; no, done
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_6 JSR _SHDDM ; shift down
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JMP _4
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_7 LDA _R0,X ; check for underflow
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ORA _R0+1,X
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@ -686,7 +706,66 @@ _C RTS
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.)
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_MOD .( ; MOD r pq er pq Rr <- Rp % Rq - modulus
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RTS
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JSR _INTDM ; initialize
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PHA ; save sign of result
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LDY #_RD-_R0 ; absolute value of register p saved in D
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JSR _ABSRY
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LDY #_RC-_R0 ; absolute value of register q saved in C
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JSR _ABSRY
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_3 JSR _CMPDC ; is D < C?
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BCC _4 ; yes, continue
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BEQ _5 ; D = C
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JSR _UPDDM ; confirmed D > C, so RD -= RC, RX += RB
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JSR _SHUDM ; shift up
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BCC _3 ; if carry is set, means a really bad overflow condition
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LDA #1 ; set to "overflowed non-zero"
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STA _R0,X
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LDA #0
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STA _R0+1,X
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STA _R0+2,X
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ORA #_F_O
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STA _R0+3,X
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BNE _9
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_4 LDA _RB+1 ; is RB < 1?
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CMP #_PLS_1
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BCC _7 ; yes, done
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JSR _CMPDC ; is D >= C?
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BCC _6 ; no, skip subtraction
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_5 JSR _UPDDM ; RD -= RC, RX += RB
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LDA _RD ; is RD > 0?
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ORA _RD+1
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ORA _RD+2
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ORA _RD+3
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BEQ _7 ; no, done
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_6 JSR _SHDDM ; shift down
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JMP _4
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_7 LDA _RD ; transfer RD to RX
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STA _R0,X
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LDA _RD+1
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STA _R0+1,X
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LDA _RD+2
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STA _R0+2,X
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LDA _RD+3
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STA _R0+3,X
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_8 LDA _F ; clear underflow
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AND #_F_U^$FF
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STA _F
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_9 LDA _R0+3,X ; check for overflow
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AND #_MSK_O
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BEQ _A ; all zero, no overflow
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LDA _F ; set overflow
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ORA #_F_O
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STA _F
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BNE _B
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_A LDA _F ; clear overflow
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AND #_F_O^$FF
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STA _F
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_B PLA ; set the sign of modulus
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BEQ _C
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TXA
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TAY
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JSR _NEGRY
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_C RTS
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.)
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_ESC .( ; ESC 00 - escape back into regular assembler
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@ -5,10 +5,9 @@
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HDR(DEMO)
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CMN
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SET(R0, 1023.9995)
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SET(R1, %0.0000000001)
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DIV(R2, R0, R1)
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MUL(R3, R1, R2)
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SET(R0, 1024 * 1024 - 0.001)
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SET(R1, 1/4)
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MOD(R2, R0, R1)
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ESC
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BRK
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