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Adding MUL instruction.
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Russell-S-Harper
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commit
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@ -299,7 +299,17 @@ _2 INC _PCL ; advance PC
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_3 RTS
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.)
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_TRFDR .( ; transfers RD to X as r register, updates overflow flag
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_RETZD .( ; clears register D, falls through to _TRFDR
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LDA #0
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STA _RD
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STA _RD+1
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STA _RD+2
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STA _RD+3
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.)
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_TRFDR .( ; pulls X, transfers RD to X as r register, updates overflow flag
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PLA
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TAX
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LDA _RD ; transfer result to Rr
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STA _R0,X
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LDA _RD+1
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@ -339,9 +349,7 @@ _ADD .( ; ADD r pq ar pq Rr <- Rp + Rq - addition
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LDA _R0+3,X
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ADC _R0+3,Y
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STA _RD+3
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PLA ; get r register
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TAX
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JMP _TRFDR ; transfer RD to r register, let it handle the return
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JMP _TRFDR ; pull X, transfer RD to r register, let it handle the return
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.)
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_SUB .( ; SUB r pq br pq Rr <- Rp - Rq - subtraction
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@ -361,13 +369,146 @@ _SUB .( ; SUB r pq br pq Rr <- Rp - Rq - subtraction
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LDA _R0+3,X
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SBC _R0+3,Y
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STA _RD+3
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PLA ; get r register
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TAX
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JMP _TRFDR ; transfer RD to r register, let it handle the return
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JMP _TRFDR ; pull X, transfer RD to r register, let it handle the return
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.)
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_TRFQD .( ; transfers Y as q register to RD
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LDA _R0,Y
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STA _RD
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LDA _R0+1,Y
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STA _RD+1
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LDA _R0+2,Y
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STA _RD+2
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LDA _R0+3,Y
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STA _RD+3
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RTS
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.)
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_NEGRY .( ; negates register at Y
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SEC
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LDA #0
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SBC _R0,Y
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STA _R0,Y
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LDA #0
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SBC _R0+1,Y
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STA _R0+1,Y
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LDA #0
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SBC _R0+2,Y
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STA _R0+2,Y
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LDA #0
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SBC _R0+3,Y
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STA _R0+3,Y
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RTS
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.)
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_ABSRY .( ; sets register at Y to absolute value
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LDA _R0+3,Y
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BMI _NEGRY
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RTS
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.)
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_MUL .( ; MUL r pq cr pq Rr <- Rp * Rq - multiplication
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RTS
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TXA ; adapted from http://www.6502.org/source/integers/32muldiv.htm
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PHA ; save r register for later
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JSR _GETPQ
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LDA _R0,X ; check for zero argument
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ORA _R0+1,X
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ORA _R0+2,X
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ORA _R0+3,X
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BNE _1 ; p is non-zero
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JMP _RETZD ; p is zero, return zero
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_1 LDA _R0,Y ; check for zero argument
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ORA _R0+1,Y
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ORA _R0+2,Y
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ORA _R0+3,Y
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BNE _2 ; q is non-zero
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JMP_RETZD ; q is zero, return zero
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_2 LDA _R0+3,X ; save sign of register p
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AND #%11000000
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PHA
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EOR _R0+3,Y
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AND #%11000000 ; save sign of product
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PHA
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JSR _TRFQD
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TXA
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TAY ; absolute value of register p
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JSR _ABSRY
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LDY #_RD-_R0 ; absolute value of register q saved in D
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JSR _ABSRY
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LDA #0
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STA _RB+4 ; clear upper half of product
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STA _RB+5
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STA _RB+6
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STA _RB+7
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LDY #34 ; thirty bit multiply and four bit shift
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_3 LSR _RD+3 ; shift operand
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ROR _RD+2
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ROR _RD+1
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ROR _RD
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BCC _4 ; skip adding in product if bit is zero
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CLC
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LDA _RB+4 ; add in p register
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ADC _R0,X
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STA _RB+4
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LDA _RB+5
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ADC _R0+1,X
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STA _RB+5
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LDA _RB+6
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ADC _R0+2,X
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STA _RB+6
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LDA _RB+7
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ADC _R0+3,X
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_4 ROR ; shift the product
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STA _RB+7
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ROR _RB+6
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ROR _RB+5
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ROR _RB+4
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ROR _RB+3
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ROR _RB+2
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ROR _RB+1
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ROR _RB
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DEY
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BNE _3 ; repeat until bits are done
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LDA _RB+1 ; copy result to RD
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STA _RD
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LDA _RB+2
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STA _RD+1
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LDA _RB+3
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STA _RD+2
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LDA _RB+4
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STA _RD+3
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AND #_MSK_O ; consider the overflow bits
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ORA _RB+5 ; check all the other bytes
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ORA _RB+6
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ORA _RB+7
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BEQ _5 ; all zeroes means no overflow
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LDA _RD+3 ; overflow situation, set accordingly
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AND #_MSK_O^$FF ; set overflow
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ORA #_F_O
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STA _RD+3
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BNE _6
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_5 LDA _RD ; check for underflow
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ORA _RD+1
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ORA _RD+2
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ORA _RD+3
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BNE _6 ; non-zero result means no underflow
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LDA _F ; we checked earlier for zero operands, so a zero result means underflow, set underflow
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ORA #_F_U
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STA _F
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BNE _7
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_6 LDA _F ; clear underflow
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AND #_F_U^$FF
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STA _F
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_7 PLA ; set the sign of the product
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BEQ _8
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LDY #_RD-_R0 ; negate register D
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JSR _NEGRY
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_8 PLA ; reset the sign of register p
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BEQ _9
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TXA
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TAY
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JSR _NEGRY
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_9 JMP _TRFDR ; pull X, transfer RD to r register, let it handle the return
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.)
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_DIV .( ; DIV r pq dr pq Rr <- Rp / Rq - division
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@ -58,9 +58,9 @@ _R7 = _R6 + 4
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_R8 = _R7 + 4
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_R9 = _R8 + 4
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_RA = _R9 + 4
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_RB = _RA + 4
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_RC = _RB + 4 ; workspace for arithmetic operations
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_RD = _RC + 4 ; as above and for EXC
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_RB = _RA + 4 ; workspace for MUL, DIV, and MOD
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_RC = _RB + 4 ; as above
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_RD = _RC + 4 ; as above and for ADD, SUB, and EXC
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_RE = _RD + 4 ; register E maintains common status
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_RF = _RE + 4 ; register F saves/restores processor status
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@ -5,10 +5,9 @@
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HDR(DEMO)
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CMN
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SET(R0, 1/1024)
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SET(R1, -1/1024)
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ADD(R2, R0, R1)
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SUB(R3, R0, R1)
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SET(R0, -1023.9995)
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SET(R1, -1023.9995)
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MUL(R2, R0, R1)
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ESC
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BRK
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