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Looks like the stray tick in the 6502 step method wasn't stray after all!

This commit is contained in:
Adrian Conlon 2024-01-07 11:37:28 +00:00
parent 70c316fd4f
commit 22f337569d
2 changed files with 19 additions and 2 deletions
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2
M6502/HarteTest_6502/checker_t.h
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@ -84,7 +84,7 @@ public:
[[nodiscard]] constexpr auto cycles() const noexcept { return m_cycles; }
[[nodiscard]] constexpr auto valid() const noexcept { return m_valid; }
[[nodiscard]] constexpr auto invalid() const noexcept { return !valid(); }
[[nodiscard]] constexpr auto unimplemented() const noexcept { return invalid() && m_cycle_count_mismatch && (cycles() == 0); }
[[nodiscard]] constexpr auto unimplemented() const noexcept { return invalid() && m_cycle_count_mismatch && (cycles() == 1); }
[[nodiscard]] constexpr auto implemented() const noexcept { return !unimplemented(); }
[[nodiscard]] constexpr const auto& messages() const noexcept { return m_messages; }

19
M6502/src/mos6502.cpp
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@ -21,25 +21,42 @@ DEFINE_PIN_LEVEL_CHANGERS(RDY, MOS6502)
DEFINE_PIN_LEVEL_CHANGERS(RW, MOS6502)
int EightBit::MOS6502::step() noexcept {
resetCycles();
ExecutingInstruction.fire(*this);
if (LIKELY(powered())) {
tick(); // A cycle is used, whether or RDY is high or not
if (UNLIKELY(lowered(SO())))
handleSO();
if (LIKELY(raised(RDY()))) {
lowerSYNC(); // Instruction fetch beginning
// Read the opcode within the existing cycle
assert(cycles() == 1 && "An extra cycle has occurred");
// Can't use fetchByte, since that would add an extra tick.
raiseRW();
opcode() = BUS().read(PC()++); // can't use fetchByte
opcode() = BUS().read(PC()++);
assert(cycles() == 1 && "BUS read has introduced stray cycles");
// Priority: RESET > NMI > INT
if (UNLIKELY(lowered(RESET())))
handleRESET();
else if (UNLIKELY(lowered(NMI())))
handleNMI();
else if (UNLIKELY(lowered(INT()) && !interruptMasked()))
handleINT();
// Whatever opcode is available, execute it.
execute();
}
}
ExecutedInstruction.fire(*this);
return cycles();
}