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More M6532 documentation added/adjusted

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Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
This commit is contained in:
Adrian Conlon 2018-12-03 23:39:22 +00:00
parent fe1aaf56c7
commit 2a223a5acd
2 changed files with 99 additions and 78 deletions
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143
M6532/inc/M6532.h
View File

@ -14,7 +14,7 @@
| |_| |
VSS -| 1 40|- A6
| |
A5 -| 2 39|- 02
A5 -| 2 39|- theta 2
| |
A4 -| 3 38|- CS1
| | ___
@ -58,7 +58,7 @@
PA0-PA7 = port A
PB0-PB7 = port B
Vcc = ground
02 = clock input
theta 2 = clock input
CS1 = chip select 1
CS2 = chip select 2 (low)
RS = RAM select (low)
@ -118,6 +118,61 @@
-- | REGISTER |
| B |
|_____________|
Basic Elements of Interval Timer
--------------------------------
R/W PA7 A3 D7 D6 D5 D4 D3 D2 D1 D0 R/W A1 A0
| | | | | | | | | | | | | |
V V V V V V V V V V V | V V
+---------------+ +-----------------------------------+ | +---------------+
___ | | | |<---+----->| |<---- theta 2
IRQ <---| Interrupt |<------| Programmable | | Divide |
| Control | | Register | | Down |
| | | |<----------| |
+---------------+ +-----------------------------------+ +---------------+
| | | | | | | | | |
+-----------------------+ | | | | | | |
| | | | | | | | |
| +-------------------+ | | | | | |
| | | | | | | |
V V V V V V V V
D7 D6 D5 D4 D3 D2 D1 D0
RAM—128 Bytes (1024 Bits)
The 128 x 8 Read/Write memory acts as a conventional static RAM. Data can be written into the RAM from
the microprocessor by selecting the chip (CS1 = 1, CS2 = 0) and by setting RS to a logic 0 (0.4v). Address
lines AO through A6 are then used to select the desired byte of storage.
Addressing Decode
-----------------
__
RS R/W A4 A3 A2 A1 A0
Write RAM 0 0 - - - - -
Read RAM 0 1 - - - - -
Write DDRA 1 0 - - 0 0 1
Read DDRA 1 1 - - 0 0 1
Write DDRB 1 0 - - 0 1 1
Read DDRB 1 1 - - 0 1 1
Write Output Reg A 1 0 - - 0 0 0
Read Output Reg A 1 1 - - 0 0 0
Write Output Reg B 1 0 - - 0 1 0
Read Output Reg B 1 1 - - 0 1 0
Write Timer
+ 1T 1 0 1 (a) 1 0 0
+ 8T 1 0 1 (a) 1 0 1
+ 64T 1 0 1 (a) 1 1 0
+ 1024T 1 0 1 (a) 1 1 1
Read Timer 1 1 - (a) 1 — 0
Read Interrupt Flag(s) 1 1 — — 1 — 1
Write Edge Detect Control 1 0 0 — 1 (b) (c)
(a) A3 = 0 to disable interrupt trom timer to IRQ
A3 = 1 to enable interrupt from timer to IRQ
(b) A1 = 0 to disable interrupt from PA7 to IRQ
A1 = 1 to enable interrupt from PA7 to IRQ
(c) A0 = 0 for negative edge-detect
AO = 1 for positive edge-detect
*/
@ -127,48 +182,6 @@ namespace EightBit {
M6532() noexcept;
virtual ~M6532() = default;
/*
Address Lines (A0-A6)
There are 7 address pins. In addition to these 7, there is 9 RAM SELECT pin. These pins, A0-A6 and RAM
SELECT, are always used as addressing pins. There are two additional pins which are used as CHIP
SELECTS. They are pins CS1 and CS2.
*/
uint8_t& address() { return m_address; }
// RAM SELECT, active low
PinLevel& RS() { return m_rs; }
// CHIP SELECT 1, active high
PinLevel& CS1() { return m_cs1; }
// CHIP SELECT 2, active low
PinLevel& CS2() { return m_cs2; }
/*
Data Bus (D0-D7)
The 6532 has eight bi-directional data pins (D0-D7). These pins connect to the system's data lines and
allow transfer of data to and from the microprocessor array. The output buffers remain in the off state except
when a Read operation occurs and are capable of driving one standard TTL load and 130 pf.
*/
uint8_t& data() { return m_data; }
/*
Peripheral Data Ports
The 6532 has 16 pins available for peripheral I/O operations. Each pin is individually software programmable
to act as either an input or an output. The 16 pins are divided into 2 8-bit ports, PA0-PA7 and PB0-PB7.
PA7 also has other uses which are discussed in later sections. The pins are set up as an input by writing a
"0" into the corresponding bit of the data direction register. A "1" into the data direction register will cause
its corresponding bit to be an output. When in the input mode, the peripheral output buffers are in the "1"
state and pull-up device acts as less than one TTL load to the peripheral data lines. On a Read operation, the
microprocessor unit reads the peripheral pin. When the peripheral device gets information from the 6532 it
receives data stored in the data register. The microprocessor will read correct information if the peripheral
lines are greater than 2.0 volts for a "1" and less than 0.8 volts for a "0" as the peripheral pins are all TTL
compatible. Pins PB0-PB7 are also capable of sourcing 3 ma at 1.5v, thus making them capable of Darlington
drive.
*/
uint8_t& PA() { return m_pa; }
uint8_t& PB() { return m_pb; }
/* ___
Reset (RES)
During system initialization a logic "0" on the RES input will cause a zeroing of all four I/O registers. This
@ -196,6 +209,48 @@ namespace EightBit {
*/
PinLevel& IRQ() { return m_irq; }
/*
Data Bus (D0-D7)
The 6532 has eight bi-directional data pins (D0-D7). These pins connect to the system's data lines and
allow transfer of data to and from the microprocessor array. The output buffers remain in the off state except
when a Read operation occurs and are capable of driving one standard TTL load and 130 pf.
*/
uint8_t& data() { return m_data; }
/*
Peripheral Data Ports
The 6532 has 16 pins available for peripheral I/O operations. Each pin is individually software programmable
to act as either an input or an output. The 16 pins are divided into 2 8-bit ports, PA0-PA7 and PB0-PB7.
PA7 also has other uses which are discussed in later sections. The pins are set up as an input by writing a
"0" into the corresponding bit of the data direction register. A "1" into the data direction register will cause
its corresponding bit to be an output. When in the input mode, the peripheral output buffers are in the "1"
state and pull-up device acts as less than one TTL load to the peripheral data lines. On a Read operation, the
microprocessor unit reads the peripheral pin. When the peripheral device gets information from the 6532 it
receives data stored in the data register. The microprocessor will read correct information if the peripheral
lines are greater than 2.0 volts for a "1" and less than 0.8 volts for a "0" as the peripheral pins are all TTL
compatible. Pins PB0-PB7 are also capable of sourcing 3 ma at 1.5v, thus making them capable of Darlington
drive.
*/
uint8_t& PA() { return m_pa; }
uint8_t& PB() { return m_pb; }
/*
Address Lines (A0-A6)
There are 7 address pins. In addition to these 7, there is 9 RAM SELECT pin. These pins, A0-A6 and RAM
SELECT, are always used as addressing pins. There are two additional pins which are used as CHIP
SELECTS. They are pins CS1 and CS2.
*/
uint8_t& address() { return m_address; }
// RAM SELECT, active low
PinLevel& RS() { return m_rs; }
// CHIP SELECT 1, active high
PinLevel& CS1() { return m_cs1; }
// CHIP SELECT 2, active low
PinLevel& CS2() { return m_cs2; }
void tick();
virtual void initialise() final;

34
M6532/src/M6532.cpp
View File

@ -6,40 +6,6 @@
EightBit::M6532::M6532() noexcept {
}
/*
RAM—128 Bytes (1024 Bits)
The 128 x 8 Read/Write memory acts as a conventional static RAM. Data can be written into the RAM from
the microprocessor by selecting the chip (CS1 = 1, CS2 = 0) and by setting RS to a logic 0 (0.4v). Address
lines AO through A6 are then used to select the desired byte of storage.
*/
/*
__
RS R/W A4 A3 A2 A1 A0
Write RAM 0 0 - - - - -
Read RAM 0 1 - - - - -
Write DDRA 1 0 - - 0 0 1
Read DDRA 1 1 - - 0 0 1
Write DDRB 1 0 - - 0 1 1
Read DDRB 1 1 - - 0 1 1
Write Output Reg A 1 0 - - 0 0 0
Read Output Reg A 1 1 - - 0 0 0
Write Output Reg B 1 0 - - 0 1 0
Read Output Reg B
Write Timer
1 1 0 1 0
+ 1T 1 0 1 (a) 1 0 0
+ 8T 1 0 1 (a) 1 0 1
+ 64T t 0 1 (a) 1 1 0
+ 1024T 1 0 1 (a) 1 1 1
Read Timer 1 1 _ (a) 1 — 0
Read Interrupt Flag(s) 1 1 — — 1 — 1
Write Edge Detect Control 1 0 0 — 1 (b) (0)
*/
void EightBit::M6532::tick() {
if (selected()) {