From 4c6f44c3943b513a7e060d4e81674259729aede0 Mon Sep 17 00:00:00 2001 From: "Adrian.Conlon" Date: Mon, 5 Jun 2017 17:31:21 +0100 Subject: [PATCH] Add 8080 test runner Signed-off-by: Adrian.Conlon --- EightBit.sln | 10 + Intel8080/test/Board.cpp | 85 ++ Intel8080/test/Board.h | 36 + Intel8080/test/Configuration.cpp | 8 + Intel8080/test/Configuration.h | 42 + Intel8080/test/Game.cpp | 21 + Intel8080/test/Game.h | 22 + Intel8080/test/roms/8080EX1.COM | Bin 0 -> 4608 bytes Intel8080/test/roms/8080EX1.MAC | 1286 +++++++++++++++++ Intel8080/test/roms/8080EXER.COM | Bin 0 -> 4608 bytes Intel8080/test/roms/8080PRE.COM | Bin 0 -> 1024 bytes Intel8080/test/roms/8080PRE.MAC | 291 ++++ Intel8080/test/roms/8085EXER.MAC | 1284 ++++++++++++++++ Intel8080/test/roms/CPUTEST.COM | Bin 0 -> 19200 bytes Intel8080/test/roms/TEST.ASM | 805 +++++++++++ Intel8080/test/roms/TEST.COM | Bin 0 -> 1793 bytes Intel8080/test/stdafx.cpp | 1 + Intel8080/test/stdafx.h | 24 + Intel8080/test/test.cpp | 19 + Intel8080/test/test_Intel8080.vcxproj | 177 +++ Intel8080/test/test_Intel8080.vcxproj.filters | 44 + 21 files changed, 4155 insertions(+) create mode 100644 Intel8080/test/Board.cpp create mode 100644 Intel8080/test/Board.h create mode 100644 Intel8080/test/Configuration.cpp create mode 100644 Intel8080/test/Configuration.h create mode 100644 Intel8080/test/Game.cpp create mode 100644 Intel8080/test/Game.h create mode 100644 Intel8080/test/roms/8080EX1.COM create mode 100644 Intel8080/test/roms/8080EX1.MAC create mode 100644 Intel8080/test/roms/8080EXER.COM create mode 100644 Intel8080/test/roms/8080PRE.COM create mode 100644 Intel8080/test/roms/8080PRE.MAC create mode 100644 Intel8080/test/roms/8085EXER.MAC create mode 100644 Intel8080/test/roms/CPUTEST.COM create mode 100644 Intel8080/test/roms/TEST.ASM create mode 100644 Intel8080/test/roms/TEST.COM create mode 100644 Intel8080/test/stdafx.cpp create mode 100644 Intel8080/test/stdafx.h create mode 100644 Intel8080/test/test.cpp create mode 100644 Intel8080/test/test_Intel8080.vcxproj create mode 100644 Intel8080/test/test_Intel8080.vcxproj.filters diff --git a/EightBit.sln b/EightBit.sln index f9de29c..0cc0d71 100644 --- a/EightBit.sln +++ b/EightBit.sln @@ -7,6 +7,8 @@ Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "EightBit", "src\EightBit.vc EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Intel8080", "Intel8080\src\Intel8080.vcxproj", "{93BDC8D8-9F0D-44ED-94FB-1BE6AC4B6BD6}" EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "test_Intel8080", "Intel8080\test\test_Intel8080.vcxproj", "{391D3B95-D9DA-47E5-9F61-70483F6BB396}" +EndProject Global GlobalSection(SolutionConfigurationPlatforms) = preSolution Debug|x64 = Debug|x64 @@ -31,6 +33,14 @@ Global {93BDC8D8-9F0D-44ED-94FB-1BE6AC4B6BD6}.Release|x64.Build.0 = Release|x64 {93BDC8D8-9F0D-44ED-94FB-1BE6AC4B6BD6}.Release|x86.ActiveCfg = Release|Win32 {93BDC8D8-9F0D-44ED-94FB-1BE6AC4B6BD6}.Release|x86.Build.0 = Release|Win32 + {391D3B95-D9DA-47E5-9F61-70483F6BB396}.Debug|x64.ActiveCfg = Debug|x64 + {391D3B95-D9DA-47E5-9F61-70483F6BB396}.Debug|x64.Build.0 = Debug|x64 + {391D3B95-D9DA-47E5-9F61-70483F6BB396}.Debug|x86.ActiveCfg = Debug|Win32 + {391D3B95-D9DA-47E5-9F61-70483F6BB396}.Debug|x86.Build.0 = Debug|Win32 + {391D3B95-D9DA-47E5-9F61-70483F6BB396}.Release|x64.ActiveCfg = Release|x64 + {391D3B95-D9DA-47E5-9F61-70483F6BB396}.Release|x64.Build.0 = Release|x64 + {391D3B95-D9DA-47E5-9F61-70483F6BB396}.Release|x86.ActiveCfg = Release|Win32 + {391D3B95-D9DA-47E5-9F61-70483F6BB396}.Release|x86.Build.0 = Release|Win32 EndGlobalSection GlobalSection(SolutionProperties) = preSolution HideSolutionNode = FALSE diff --git a/Intel8080/test/Board.cpp b/Intel8080/test/Board.cpp new file mode 100644 index 0000000..e0fd1a3 --- /dev/null +++ b/Intel8080/test/Board.cpp @@ -0,0 +1,85 @@ +#include "stdafx.h" +#include "Board.h" +#include "Disassembler.h" +#include "Configuration.h" + +#include + +Board::Board(const Configuration& configuration) +: m_configuration(configuration), + m_memory(0xffff), + m_cpu(EightBit::Intel8080(m_memory, m_ports)) { +} + +void Board::initialise() { + + m_memory.clear(); + auto romDirectory = m_configuration.getRomDirectory(); + + //m_memory.loadRam(romDirectory + "/TEST.COM", 0x100); // Microcosm + //m_memory.loadRam(romDirectory + "/8080PRE.COM", 0x100); // Bartholomew preliminary + m_memory.loadRam(romDirectory + "/8080EX1.COM", 0x100); // Cringle/Bartholomew + //m_memory.loadRam(romDirectory + "/CPUTEST.COM", 0x100); // SuperSoft diagnostics + + m_memory.set(5, 0xc9); // ret + m_cpu.ExecutingInstruction.connect(std::bind(&Board::Cpu_ExecutingInstruction_Cpm, this, std::placeholders::_1)); + + if (m_configuration.isProfileMode()) { + m_cpu.ExecutingInstruction.connect(std::bind(&Board::Cpu_ExecutingInstruction_Profile, this, std::placeholders::_1)); + } + + if (m_configuration.isDebugMode()) { + m_cpu.ExecutingInstruction.connect(std::bind(&Board::Cpu_ExecutingInstruction_Debug, this, std::placeholders::_1)); + } + + m_cpu.initialise(); + m_cpu.setProgramCounter(m_configuration.getStartAddress()); +} + +void Board::Cpu_ExecutingInstruction_Cpm(const EightBit::Intel8080&) { + auto pc = m_cpu.getProgramCounter(); + switch (pc.word) { + case 0x0: // CP/M warm start + m_cpu.halt(); + m_profiler.dump(); + break; + case 0x5: // BDOS + bdos(); + break; + default: + break; + } +} + +void Board::bdos() { + auto c = m_cpu.C(); + switch (c) { + case 0x2: { + auto character = m_cpu.E(); + std::cout << character; + break; + } + case 0x9: + for (uint16_t i = m_cpu.DE().word; m_memory.get(i) != '$'; ++i) { + std::cout << m_memory.get(i); + } + break; + } +} + +void Board::Cpu_ExecutingInstruction_Profile(const EightBit::Intel8080& cpu) { + + const auto pc = cpu.getProgramCounter(); + + m_profiler.addAddress(pc.word); + m_profiler.addInstruction(m_memory.peek(pc.word)); +} + +void Board::Cpu_ExecutingInstruction_Debug(const EightBit::Intel8080&) { + + std::cerr + << EightBit::Disassembler::state(m_cpu) + << "\t" + << EightBit::Disassembler::disassemble(m_cpu) + << '\n'; +} diff --git a/Intel8080/test/Board.h b/Intel8080/test/Board.h new file mode 100644 index 0000000..fa96247 --- /dev/null +++ b/Intel8080/test/Board.h @@ -0,0 +1,36 @@ +#pragma once + +//#include + +#include "Memory.h" +#include "InputOutput.h" +#include "Intel8080.h" +#include "Profiler.h" +#include "EventArgs.h" + +class Configuration; + +class Board { +public: + Board(const Configuration& configuration); + + EightBit::Memory& getMemory() { return m_memory; } + const EightBit::Intel8080& getCPU() const { return m_cpu; } + EightBit::Intel8080& getCPUMutable() { return m_cpu; } + + void initialise(); + +private: + const Configuration& m_configuration; + EightBit::Memory m_memory; + EightBit::InputOutput m_ports; + EightBit::Intel8080 m_cpu; + EightBit::Profiler m_profiler; + + void Cpu_ExecutingInstruction_Cpm(const EightBit::Intel8080& cpu); + + void Cpu_ExecutingInstruction_Debug(const EightBit::Intel8080& cpuEvent); + void Cpu_ExecutingInstruction_Profile(const EightBit::Intel8080& cpuEvent); + + void bdos(); +}; diff --git a/Intel8080/test/Configuration.cpp b/Intel8080/test/Configuration.cpp new file mode 100644 index 0000000..77ae143 --- /dev/null +++ b/Intel8080/test/Configuration.cpp @@ -0,0 +1,8 @@ +#include "stdafx.h" +#include "Configuration.h" + +Configuration::Configuration() +: m_debugMode(false), + m_profileMode(false), + m_romDirectory("roms") { +} diff --git a/Intel8080/test/Configuration.h b/Intel8080/test/Configuration.h new file mode 100644 index 0000000..0e6cee8 --- /dev/null +++ b/Intel8080/test/Configuration.h @@ -0,0 +1,42 @@ +#pragma once + +#include + +#include "Memory.h" + +class Configuration { +public: + Configuration(); + + bool isDebugMode() const { + return m_debugMode; + } + + void setDebugMode(bool value) { + m_debugMode = value; + } + + bool isProfileMode() const { + return m_profileMode; + } + + void setProfileMode(bool value) { + m_profileMode = value; + } + + std::string getRomDirectory() const { + return m_romDirectory; + } + + EightBit::register16_t getStartAddress() const { + EightBit::register16_t returned; + returned.word = 0x100; + return returned; + } + +private: + bool m_debugMode; + bool m_profileMode; + + std::string m_romDirectory; +}; diff --git a/Intel8080/test/Game.cpp b/Intel8080/test/Game.cpp new file mode 100644 index 0000000..ed823c9 --- /dev/null +++ b/Intel8080/test/Game.cpp @@ -0,0 +1,21 @@ +#include "stdafx.h" +#include "Game.h" + +#include + +Game::Game(const Configuration& configuration) +: m_configuration(configuration), + m_board(configuration) { +} + +void Game::initialise() { + m_board.initialise(); +} + +void Game::runLoop() { + auto& cpu = m_board.getCPUMutable(); + auto cycles = 0; + while (!cpu.isHalted()) { + cycles = cpu.step(); + } +} diff --git a/Intel8080/test/Game.h b/Intel8080/test/Game.h new file mode 100644 index 0000000..9e5f682 --- /dev/null +++ b/Intel8080/test/Game.h @@ -0,0 +1,22 @@ +#pragma once + +//#include +//#include +//#include +//#include + +#include "Board.h" + +class Configuration; + +class Game { +public: + Game(const Configuration& configuration); + + void runLoop(); + void initialise(); + +private: + const Configuration& m_configuration; + mutable Board m_board; +}; diff --git a/Intel8080/test/roms/8080EX1.COM b/Intel8080/test/roms/8080EX1.COM new file mode 100644 index 0000000000000000000000000000000000000000..13c1432c8d81d4a4c1095b1a717911ea1ee60ec7 GIT binary patch literal 4608 zcmb`Kc~}$I8pdbHM#xMcMy-g{Kq4vx#0?QJN>ON)#T`XdLJ~HU009B17pWGPwxVLG zSS#X!LRAzZ`=SKYf=2dL0YPI$RH_9l){=WB0fHFs{io-7hB@cVH^1-w-Z_~wl+j^m zOfx4!1GG0Nl`MaTn%KcH%$&+uu!a1dUYRLOV^LM}We_BW@4;3&@j5Sc+;JH=Dqf7g zhqofc6J8SBi5WyHNldy&veJ#$eW~kC&LC6u#Ci~>tG(ic z^+OCVKU&nm-87S8 z;FlF=JHi_3D8U&!Mzto;PfnPX%oT1A4q=GJW57d0mNFK^acYEOSl--_q_Ftz>IEaGrC!$6 zA1wead`$o49A~OSpjg7@^CTPwSBpg~B_6~v8!er<(Xrp`^@{s^?}ow?WB6L=5QOpf zyr3`B@O`!NaUkxP{NmDzgO48FrJZ}K^Oc*qE|}9aZEHx)|0`ji9Pp!n{wNMZJ0Ag{ z15NYEn+S2Irhl(nn@I2>eyCroe3gF18;OxdKToUv@qqs_89=$)p|nYMAX{!hqP>8~=E{-n__(5jyW_{0f4uiKtln4PChF8Yi(X~ro2 zr|>HNxU59Bh997n&jkFwvQ(1D2=5{5GT-g_u(M3#&!^l``*X^Ic|+rmc0L>MXU8&9 z*E^A~mG+(KsBt*M(dhrAe3gEsXWe>@exX+V^8kN+-cE$0z`-&5HndLgUN9Bof0_&~ zf`!QY=u#k@v zu$1Otweym!qaqoDneX!RF5-z3d@!Q6rW{jLdRfCAVStbiUeBL+L9>*mfRC$|M6TH- zS^SJ2+i76gJzpDJGpEV&bgze5*#F^UUQh9Mw#<)@^2rRRN}X%&T5I+%4HaxxqXz2k z`#$kFVN~F#{fj-O5|$F|kx-h{+&F&Mr7v(W4!)Hc-)ry@Nj)(-1GXnv>^9yiK2OR}sVX3yzty3uP*3;~_&@J0f>OIu*1T zpie|W--L+Tz+l1+h4E0#I3}GEl_`6#N5jFe!N?e)(Abb+kLp8Deu`@6h7Lwl+EJc# z47SM@Q0&~nu-pojA4JMCk1O=bE%ag3e8Uag(%NPY3tNo6DbuNZB~yu znam0W2cGksGRFWhX-7<7P=G2^8bZXYgvnDVL<1lQoXeOLc{+tjkfl&6ZZ;^~v6^BA zp~^}MQCGj813l=ar0aXUBFOT=#PCJM@I^YJzSv0Vtl2S+URnWsy{RyNL2)*DPKog# zMGnF;T?CAoKtj~%&eGpF@K6j5aW*kPhGN)=ISpX~fx|KVK#L8ub~Bwa>>vl}tSNm} z(a;0WfaLR#9^!Z^JQ3RR_326;GJXfi17zBafI7U9=qGRW_4R|zpy($g2NzB(i6Dzb zY78;)kywqu5YX>2?3srZdI@ovoKl&F*g&NMDmA)@M-nB2-1EJD_RM3F#_ zIuOXDM_vJ9u;60sYvx~VSml43K+r-&An0*1oZdEAE)6s#y!6smO95qQrW1c7@!LtT^DRnYk9!Vw04xlP0wW*Gg z-$sFl7txCTn+hU+Xjp)D0_XdIsrvG2^c9xoiTph~gW<6P%rY3uRhIzbjd1qwg~zzrG>GRy!=Vdl&plU%A{Pbc_IPEK=%6R=}e(0CqmN>RgZms{1sO@o2Uw!tfJ#}%n z>B6M-{B3DB{_!1%{!UQwd_3&!!6OP=-svym9n?kp?Zu4WTmucZH263^KI0!Malk#U zS%I&2sYT=dN!82VHa|P<-4|I&!uy34jhBiBmdt4uK3dk{z5PKWT6M8z(MGct>r1QJ zA-mt2R>fYg=1w%Z)|b6rTF$I0NIafboT@)VCog#`VZZJzq$Mkp(#@I`ymQ}%09RTm z*Z5+NpXH*62abo~`=P|7T1HWCgMoQyX50Z{PWIGO*B_@o&8wdqMXETX4-L%wiJTVS zNlluxD+n#r6)mzn!WSNU!t;i=ZClkhMacDy6IeID_J!Pq#KadyaO&5)b^A*D^~*g4 zS6gn4%k5tIeM#Q4_xbyG`nDN&OlYW8|WfBs$XDsaora#3Al-``Gw-9hujE$=V;?{{wX$*W$9w+x$$Ggkbn=eo5G-C41c5b7{p z$MM$^ih)4|!r1E>kUfnN94F29t0&*%K0dXjeSkW%r6TESb&~1rrnGAtrHekZx`uv} zTkLIrqd<81Mcy99&)20nxSTE|JhS%aXALe3Pu50W!QVHV5cXi=o<}^&xF7lU-=d-* zPIQo0+GA=J*Tb+f>}B&(P*!{VA(g10mXFKbd>$gZxM z&2CBlep7pf@d>`{>T}*}v+Y4=f6);g)%%4^Oz)xEES8Y`;|P!^J@NYT-CcRnk_$N*XxN=KPbeHXkST#Dc*+!$;!9B8G+nw%DRcds%0s9T~SSF?Mrw3p0x{cQrQK6 zGj6rd#J|1@baCT|BkyO_1TAlA^m?$QgW|WK+5V68qKq}|g~>NvvZ{7jXDhpli(gNv zERcP-Mtanmb?xl=f@&Lryoq>pZM)}8W{dxIsb92JId^&9<^Urd^I(e~uTe@Clp*n_ Qy$BsfmO8x$|F!)81>F^*-v9sr literal 0 HcmV?d00001 diff --git a/Intel8080/test/roms/8080EX1.MAC b/Intel8080/test/roms/8080EX1.MAC new file mode 100644 index 0000000..16cf070 --- /dev/null +++ b/Intel8080/test/roms/8080EX1.MAC @@ -0,0 +1,1286 @@ + title 'Z80 instruction set exerciser' + +; zexlax.z80 - Z80 instruction set exerciser +; Copyright (C) 1994 Frank D. Cringle +; +; This program is free software; you can redistribute it and/or +; modify it under the terms of the GNU General Public License +; as published by the Free Software Foundation; either version 2 +; of the License, or (at your option) any later version. +; +; This program is distributed in the hope that it will be useful, +; but WITHOUT ANY WARRANTY; without even the implied warranty of +; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +; GNU General Public License for more details. +; +; You should have received a copy of the GNU General Public License +; along with this program; if not, write to the Free Software +; Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +; +;****************************************************************************** +; +; Modified to exercise an 8080 by Ian Bartholomew, February 2009 +; +; CRC values for a KR580VM80A CPU +; +; I have made the following changes - +; +; Converted all mnemonics to 8080 and rewritten any Z80 code used +; in the original exerciser. Changes are tagged with a #idb in the +; source code listing. +; +; Removed any test descriptors that are not used. +; +; Changed the macro definitions to work in M80 +; +; The machine state snapshot has been changed to remove the IX/IY registers. +; They have been replaced by two more copies of HL to obviate the need +; for major changes in the exerciser code. +; +; Changed flag mask in all tests to 0ffh to reflect that the 8080, unlike the 8085 +; and Z80, does define the unused bits in the flag register - [S Z 0 AC 0 P 1 C] +; +;****************************************************************************** + + .8080 + aseg + org 100h + +begin: jmp start + +; machine state before test (needs to be at predictably constant address) +msbt: ds 14 +spbt: ds 2 + +; For the purposes of this test program, the machine state consists of: +; a 2 byte memory operand, followed by +; the registers iy,ix,hl,de,bc,af,sp +; for a total of 16 bytes. + +; The program tests instructions (or groups of similar instructions) +; by cycling through a sequence of machine states, executing the test +; instruction for each one and running a 32-bit crc over the resulting +; machine states. At the end of the sequence the crc is compared to +; an expected value that was found empirically on a real Z80. + +; A test case is defined by a descriptor which consists of: +; a flag mask byte, +; the base case, +; the incement vector, +; the shift vector, +; the expected crc, +; a short descriptive message. +; +; The flag mask byte is used to prevent undefined flag bits from +; influencing the results. Documented flags are as per Mostek Z80 +; Technical Manual. +; +; The next three parts of the descriptor are 20 byte vectors +; corresponding to a 4 byte instruction and a 16 byte machine state. +; The first part is the base case, which is the first test case of +; the sequence. This base is then modified according to the next 2 +; vectors. Each 1 bit in the increment vector specifies a bit to be +; cycled in the form of a binary counter. For instance, if the byte +; corresponding to the accumulator is set to 0ffh in the increment +; vector, the test will be repeated for all 256 values of the +; accumulator. Note that 1 bits don't have to be contiguous. The +; number of test cases 'caused' by the increment vector is equal to +; 2^(number of 1 bits). The shift vector is similar, but specifies a +; set of bits in the test case that are to be successively inverted. +; Thus the shift vector 'causes' a number of test cases equal to the +; number of 1 bits in it. + +; The total number of test cases is the product of those caused by the +; counter and shift vectors and can easily become unweildy. Each +; individual test case can take a few milliseconds to execute, due to +; the overhead of test setup and crc calculation, so test design is a +; compromise between coverage and execution time. + +; This program is designed to detect differences between +; implementations and is not ideal for diagnosing the causes of any +; discrepancies. However, provided a reference implementation (or +; real system) is available, a failing test case can be isolated by +; hand using a binary search of the test space. + + +start: lhld 6 + sphl + lxi d,msg1 + mvi c,9 + call bdos + + lxi h,tests ; first test case +loop: mov a,m ; end of list ? + inx h + ora m + jz done + dcx h + call stt + jmp loop + +done: lxi d,msg2 + mvi c,9 + call bdos + jmp 0 ; warm boot + +tests: + dw add16 + dw alu8i + dw alu8r + dw daa + dw inca + dw incb + dw incbc + dw incc + dw incd + dw incde + dw ince + dw inch + dw inchl + dw incl + dw incm + dw incsp + dw ld162 + dw ld166 + dw ld16im + dw ld8bd + dw ld8im + dw ld8rr + dw lda + dw rot8080 + dw stabd + dw 0 + +tstr macro insn,memop,hliy,hlix,hl,de,bc,flags,acc,sp + local lab +lab: db insn + ds lab+4-$,0 + dw memop,hliy,hlix,hl,de,bc + db flags + db acc + dw sp + if $-lab ne 20 + error 'missing parameter' + endif + endm + +tmsg macro m + local lab +lab: db m + if $ ge lab+30 + error 'message too long' + else + ds lab+30-$,'.' + endif + db '$' + endm + +; add hl, (19,456 cycles) +add16: db 0ffh ; flag mask + tstr 9,0c4a5h,0c4c7h,0d226h,0a050h,058eah,08566h,0c6h,0deh,09bc9h + tstr 030h,0,0,0,0f821h,0,0,0,0,0 ; (512 cycles) + tstr 0,0,0,0,-1,-1,-1,0d7h,0,-1 ; (38 cycles) + db 014h, 047h, 04bh, 0a6h ; expected crc + tmsg 'dad ' + +; aluop a,nn (28,672 cycles) +alu8i: db 0ffh ; flag mask + tstr 0c6h,09140h,07e3ch,07a67h,0df6dh,05b61h,00b29h,010h,066h,085b2h + tstr 038h,0,0,0,0,0,0,0,-1,0 ; (2048 cycles) + tstr <0,-1>,0,0,0,0,0,0,0d7h,0,0 ; (14 cycles) + db 09eh, 092h, 02fh, 09eh ; expected crc + tmsg 'aluop nn' + +; aluop a, (753,664 cycles) +alu8r: db 0ffh ; flag mask + tstr 080h,0c53eh,0573ah,04c4dh,msbt,0e309h,0a666h,0d0h,03bh,0adbbh + tstr 03fh,0,0,0,0,0,0,0,-1,0 ; (16,384 cycles) + tstr 0,0ffh,0,0,0,-1,-1,0d7h,0,0 ; (46 cycles) + db 0cfh, 076h, 02ch, 086h ; expected crc + tmsg 'aluop ' + +; +daa: db 0ffh ; flag mask + tstr 027h,02141h,009fah,01d60h,0a559h,08d5bh,09079h,004h,08eh,0299dh + tstr 018h,0,0,0,0,0,0,0d7h,-1,0 ; (65,536 cycles) + tstr 0,0,0,0,0,0,0,0,0,0 ; (1 cycle) + db 0bbh,03fh,003h,00ch ; expected crc + tmsg '' + +; a (3072 cycles) +inca: db 0ffh ; flag mask + tstr 03ch,04adfh,0d5d8h,0e598h,08a2bh,0a7b0h,0431bh,044h,05ah,0d030h + tstr 001h,0,0,0,0,0,0,0,-1,0 ; (512 cycles) + tstr 0,0,0,0,0,0,0,0d7h,0,0 ; (6 cycles) + db 0adh,0b6h,046h,00eh ; expected crc + tmsg ' a' + +; b (3072 cycles) +incb: db 0ffh ; flag mask + tstr 004h,0d623h,0432dh,07a61h,08180h,05a86h,01e85h,086h,058h,09bbbh + tstr 001h,0,0,0,0,0,0ff00h,0,0,0 ; (512 cycles) + tstr 0,0,0,0,0,0,0,0d7h,0,0 ; (6 cycles) + db 083h,0edh,013h,045h ; expected crc + tmsg ' b' + +; bc (1536 cycles) +incbc: db 0ffh ; flag mask + tstr 003h,0cd97h,044abh,08dc9h,0e3e3h,011cch,0e8a4h,002h,049h,02a4dh + tstr 008h,0,0,0,0,0,0f821h,0,0,0 ; (256 cycles) + tstr 0,0,0,0,0,0,0,0d7h,0,0 ; (6 cycles) + db 0f7h,092h,087h,0cdh ; expected crc + tmsg ' b' + +; c (3072 cycles) +incc: db 0ffh ; flag mask + tstr 00ch,0d789h,00935h,0055bh,09f85h,08b27h,0d208h,095h,005h,00660h + tstr 001h,0,0,0,0,0,0ffh,0,0,0 ; (512 cycles) + tstr 0,0,0,0,0,0,0,0d7h,0,0 ; (6 cycles) + db 0e5h,0f6h,072h,01bh ; expected crc + tmsg ' c' + +; d (3072 cycles) +incd: db 0ffh ; flag mask + tstr 014h,0a0eah,05fbah,065fbh,0981ch,038cch,0debch,043h,05ch,003bdh + tstr 001h,0,0,0,0,0ff00h,0,0,0,0 ; (512 cycles) + tstr 0,0,0,0,0,0,0,0d7h,0,0 ; (6 cycles) + db 015h,0b5h,057h,09ah ; expected crc + tmsg ' d' + +; de (1536 cycles) +incde: db 0ffh ; flag mask + tstr 013h,0342eh,0131dh,028c9h,00acah,09967h,03a2eh,092h,0f6h,09d54h + tstr 008h,0,0,0,0,0f821h,0,0,0,0 ; (256 cycles) + tstr 0,0,0,0,0,0,0,0d7h,0,0 ; (6 cycles) + db 07fh,04eh,025h,001h ; expected crc + tmsg ' d' + +; e (3072 cycles) +ince: db 0ffh ; flag mask + tstr 01ch,0602fh,04c0dh,02402h,0e2f5h,0a0f4h,0a10ah,013h,032h,05925h + tstr 001h,0,0,0,0,0ffh,0,0,0,0 ; (512 cycles) + tstr 0,0,0,0,0,0,0,0d7h,0,0 ; (6 cycles) + db 0cfh,02ah,0b3h,096h ; expected crc + tmsg ' e' + +; h (3072 cycles) +inch: db 0ffh ; flag mask + tstr 024h,01506h,0f2ebh,0e8ddh,0262bh,011a6h,0bc1ah,017h,006h,02818h + tstr 001h,0,0,0,0ff00h,0,0,0,0,0 ; (512 cycles) + tstr 0,0,0,0,0,0,0,0d7h,0,0 ; (6 cycles) + db 012h,0b2h,095h,02ch ; expected crc + tmsg ' h' + +; hl (1536 cycles) +inchl: db 0ffh ; flag mask + tstr 023h,0c3f4h,007a5h,01b6dh,04f04h,0e2c2h,0822ah,057h,0e0h,0c3e1h + tstr 008h,0,0,0,0f821h,0,0,0,0,0 ; (256 cycles) + tstr 0,0,0,0,0,0,0,0d7h,0,0 ; (6 cycles) + db 09fh,02bh,023h,0c0h ; expected crc + tmsg ' h' + +; l (3072 cycles) +incl: db 0ffh ; flag mask + tstr 02ch,08031h,0a520h,04356h,0b409h,0f4c1h,0dfa2h,0d1h,03ch,03ea2h + tstr 001h,0,0,0,0ffh,0,0,0,0,0 ; (512 cycles) + tstr 0,0,0,0,0,0,0,0d7h,0,0 ; (6 cycles) + db 0ffh,057h,0d3h,056h ; expected crc + tmsg ' l' + +; (hl) (3072 cycles) +incm: db 0ffh ; flag mask + tstr 034h,0b856h,00c7ch,0e53eh,msbt,0877eh,0da58h,015h,05ch,01f37h + tstr 001h,0ffh,0,0,0,0,0,0,0,0 ; (512 cycles) + tstr 0,0,0,0,0,0,0,0d7h,0,0 ; (6 cycles) + db 092h,0e9h,063h,0bdh ; expected crc + tmsg ' m' + +; sp (1536 cycles) +incsp: db 0ffh ; flag mask + tstr 033h,0346fh,0d482h,0d169h,0deb6h,0a494h,0f476h,053h,002h,0855bh + tstr 008h,0,0,0,0,0,0,0,0,0f821h ; (256 cycles) + tstr 0,0,0,0,0,0,0,0d7h,0,0 ; (6 cycles) + db 0d5h,070h,02fh,0abh ; expected crc + tmsg ' sp' + +; ld hl,(nnnn) (16 cycles) +ld162: db 0ffh ; flag mask + tstr <02ah,low msbt,high msbt>,09863h,07830h,02077h,0b1feh,0b9fah,0abb8h,004h,006h,06015h + tstr 0,0,0,0,0,0,0,0,0,0 ; (1 cycle) + tstr 0,-1,0,0,0,0,0,0,0,0 ; (16 cycles) + db 0a9h,0c3h,0d5h,0cbh ; expected crc + tmsg 'lhld nnnn' + +; ld (nnnn),hl (16 cycles) +ld166: db 0ffh ; flag mask + tstr <022h,low msbt,high msbt>,0d003h,07772h,07f53h,03f72h,064eah,0e180h,010h,02dh,035e9h + tstr 0,0,0,0,0,0,0,0,0,0 ; (1 cycle) + tstr 0,0,0,0,-1,0,0,0,0,0 ; (16 cycles) + db 0e8h,086h,04fh,026h ; expected crc + tmsg 'shld nnnn' + +; ld ,nnnn (64 cycles) +ld16im: db 0ffh ; flag mask + tstr 1,05c1ch,02d46h,08eb9h,06078h,074b1h,0b30eh,046h,0d1h,030cch + tstr 030h,0,0,0,0,0,0,0,0,0 ; (4 cycles) + tstr <0,0ffh,0ffh>,0,0,0,0,0,0,0,0,0 ; (16 cycles) + db 0fch,0f4h,06eh,012h ; expected crc + tmsg 'lxi ,nnnn' + +; ld a,<(bc),(de)> (44 cycles) +ld8bd: db 0ffh ; flag mask + tstr 00ah,0b3a8h,01d2ah,07f8eh,042ach,msbt,msbt,0c6h,0b1h,0ef8eh + tstr 010h,0,0,0,0,0,0,0,0,0 ; (2 cycles) + tstr 0,0ffh,0,0,0,0,0,0d7h,-1,0 ; (22 cycles) + db 02bh,082h,01dh,05fh ; expected crc + tmsg 'ldax ' + +; ld ,nn (64 cycles) +ld8im: db 0ffh ; flag mask + tstr 6,0c407h,0f49dh,0d13dh,00339h,0de89h,07455h,053h,0c0h,05509h + tstr 038h,0,0,0,0,0,0,0,0,0 ; (8 cycles) + tstr 0,0,0,0,0,0,0,0,-1,0 ; (8 cycles) + db 0eah,0a7h,020h,044h ; expected crc + tmsg 'mvi ,nn' + +; ld , (3456 cycles) +ld8rr: db 0ffh ; flag mask + tstr 040h,072a4h,0a024h,061ach,msbt,082c7h,0718fh,097h,08fh,0ef8eh + tstr 03fh,0,0,0,0,0,0,0,0,0 ; (64 cycles) + tstr 0,0ffh,0,0,0,-1,-1,0d7h,-1,0 ; (54 cycles) + db 010h,0b5h,08ch,0eeh ; expected crc + tmsg 'mov ,' + +; ld a,(nnnn) / ld (nnnn),a (44 cycles) +lda: db 0ffh ; flag mask + tstr <032h,low msbt,high msbt>,0fd68h,0f4ech,044a0h,0b543h,00653h,0cdbah,0d2h,04fh,01fd8h + tstr 008h,0,0,0,0,0,0,0,0,0 ; (2 cycle) + tstr 0,0ffh,0,0,0,0,0,0d7h,-1,0 ; (22 cycles) + db 0edh,057h,0afh,072h ; expected crc + tmsg 'sta nnnn / lda nnnn' + +; (6144 cycles) +rot8080: db 0ffh ; flag mask + tstr 7,0cb92h,06d43h,00a90h,0c284h,00c53h,0f50eh,091h,0ebh,040fch + tstr 018h,0,0,0,0,0,0,0,-1,0 ; (1024 cycles) + tstr 0,0,0,0,0,0,0,0d7h,0,0 ; (6 cycles) + db 0e0h,0d8h,092h,035h ; expected crc + tmsg '' + +; ld (),a (96 cycles) +stabd: db 0ffh ; flag mask + tstr 2,00c3bh,0b592h,06cffh,0959eh,msbt,msbt+1,0c1h,021h,0bde7h + tstr 018h,0,0,0,0,0,0,0,0,0 ; (4 cycles) + tstr 0,-1,0,0,0,0,0,0,-1,0 ; (24 cycles) + db 02bh,004h,071h,0e9h ; expected crc + tmsg 'stax ' + +; start test pointed to by (hl) +stt: push h + mov a,m ; get pointer to test + inx h + mov h,m + mov l,a + mov a,m ; flag mask + sta flgmsk+1 + inx h + push h + lxi d,20 + dad d ; point to incmask + lxi d,counter + call initmask + pop h + push h + lxi d,20+20 + dad d ; point to scanmask + lxi d,shifter + call initmask + lxi h,shifter + mvi m,1 ; first bit + pop h + push h + lxi d,iut ; copy initial instruction under test + lxi b,4 + +;#idb ldir replaced with following code +ldir1: mov a,m + stax d + inx h + inx d + dcx b + mov a,b + ora c + jnz ldir1 +;#idb + + lxi d,msbt ; copy initial machine state + lxi b,16 + +;#idb ldir replaced with following code +ldir2: mov a,m + stax d + inx h + inx d + dcx b + mov a,b + ora c + jnz ldir2 +;#idb + + lxi d,20+20+4 ; skip incmask, scanmask and expcrc + dad d + xchg + mvi c,9 + call bdos ; show test name + call initcrc ; initialise crc +; test loop +tlp: lda iut + cpi 076h ; pragmatically avoid halt intructions + jz tlp2 + ani 0dfh + cpi 0ddh + jnz tlp1 + lda iut+1 + cpi 076h +tlp1: cnz test ; execute the test instruction +tlp2: call count ; increment the counter + cnz shift ; shift the scan bit + pop h ; pointer to test case + jz tlp3 ; done if shift returned NZ + lxi d,20+20+20 + dad d ; point to expected crc + call cmpcrc + lxi d,okmsg + jz tlpok + lxi d,ermsg1 + mvi c,9 + call bdos + call phex8 + lxi d,ermsg2 + mvi c,9 + call bdos + lxi h,crcval + call phex8 + lxi d,crlf +tlpok: mvi c,9 + call bdos + pop h + inx h + inx h + ret + +tlp3: push h + mvi a,1 ; initialise count and shift scanners + sta cntbit + sta shfbit + lxi h,counter + shld cntbyt + lxi h,shifter + shld shfbyt + + mvi b,4 ; bytes in iut field + pop h ; pointer to test case + push h + lxi d,iut + call setup ; setup iut + mvi b,16 ; bytes in machine state + lxi d,msbt + call setup ; setup machine state + jmp tlp + +; setup a field of the test case +; b = number of bytes +; hl = pointer to base case +; de = destination +setup: call subyte + inx h + dcr b + jnz setup + ret + +subyte: push b + push d + push h + mov c,m ; get base byte + lxi d,20 + dad d ; point to incmask + mov a,m + cpi 0 + jz subshf + mvi b,8 ; 8 bits +subclp: rrc + push psw + mvi a,0 + cc nxtcbit ; get next counter bit if mask bit was set + xra c ; flip bit if counter bit was set + rrc + mov c,a + pop psw + dcr b + jnz subclp + mvi b,8 +subshf: lxi d,20 + dad d ; point to shift mask + mov a,m + cpi 0 + jz substr + mvi b,8 ; 8 bits +sbshf1: rrc + push psw + mvi a,0 + cc nxtsbit ; get next shifter bit if mask bit was set + xra c ; flip bit if shifter bit was set + rrc + mov c,a + pop psw + dcr b + jnz sbshf1 +substr: pop h + pop d + mov a,c + stax d ; mangled byte to destination + inx d + pop b + ret + +; get next counter bit in low bit of a +cntbit: ds 1 +cntbyt: ds 2 + +nxtcbit: push b + push h + lhld cntbyt + mov b,m + lxi h,cntbit + mov a,m + mov c,a + rlc + mov m,a + cpi 1 + jnz ncb1 + lhld cntbyt + inx h + shld cntbyt +ncb1: mov a,b + ana c + pop h + pop b + rz + mvi a,1 + ret + +; get next shifter bit in low bit of a +shfbit: ds 1 +shfbyt: ds 2 + +nxtsbit: push b + push h + lhld shfbyt + mov b,m + lxi h,shfbit + mov a,m + mov c,a + rlc + mov m,a + cpi 1 + jnz nsb1 + lhld shfbyt + inx h + shld shfbyt +nsb1: mov a,b + ana c + pop h + pop b + rz + mvi a,1 + ret + + +; clear memory at hl, bc bytes +clrmem: push psw + push b + push d + push h + mvi m,0 + mov d,h + mov e,l + inx d + dcx b + +;#idb ldir replaced with following code +ldir3: mov a,m + stax d + inx h + inx d + dcx b + mov a,b + ora c + jnz ldir3 +;#idb + + pop h + pop d + pop b + pop psw + ret + +; initialise counter or shifter +; de = pointer to work area for counter or shifter +; hl = pointer to mask +initmask: + push d + xchg + lxi b,20+20 + call clrmem ; clear work area + xchg + mvi b,20 ; byte counter + mvi c,1 ; first bit + mvi d,0 ; bit counter +imlp: mov e,m +imlp1: mov a,e + ana c + jz imlp2 + inr d +imlp2: mov a,c + rlc + mov c,a + cpi 1 + jnz imlp1 + inx h + dcr b + jnz imlp +; got number of 1-bits in mask in reg d + mov a,d + ani 0f8h + rrc + rrc + rrc ; divide by 8 (get byte offset) + mov l,a + mvi h,0 + mov a,d + ani 7 ; bit offset + inr a + mov b,a + mvi a,080h +imlp3: rlc + dcr b + jnz imlp3 + pop d + dad d + lxi d,20 + dad d + mov m,a + ret + +; multi-byte counter +count: push b + push d + push h + lxi h,counter ; 20 byte counter starts here + lxi d,20 ; somewhere in here is the stop bit + xchg + dad d + xchg +cntlp: inr m + mov a,m + cpi 0 + jz cntlp1 ; overflow to next byte + mov b,a + ldax d + ana b ; test for terminal value + jz cntend + mvi m,0 ; reset to zero +cntend: pop b + pop d + pop h + ret + +cntlp1: inx h + inx d + jmp cntlp + + +; multi-byte shifter +shift: push b + push d + push h + lxi h,shifter ; 20 byte shift register starts here + lxi d,20 ; somewhere in here is the stop bit + xchg + dad d + xchg +shflp: mov a,m + ora a + jz shflp1 + mov b,a + ldax d + ana b + jnz shlpe + mov a,b + rlc + cpi 1 + jnz shflp2 + mvi m,0 + inx h + inx d +shflp2: mov m,a + xra a ; set Z +shlpe: pop h + pop d + pop b + ret +shflp1: inx h + inx d + jmp shflp + +counter: ds 2*20 +shifter: ds 2*20 + +; test harness +test: push psw + push b + push d + push h + if 0 + lxi d,crlf + mvi c,9 + call bdos + lxi h,iut + mvi b,4 + call hexstr + mvi e,' ' + mvi c,2 + call bdos + mvi b,16 + lxi h,msbt + call hexstr + endif + di ; disable interrupts + +;#idb ld (spsav),sp replaced by following code +;#idb All registers and flages are immediately overwritten so +;#idb no need to preserve any state. + lxi h,0 ; save stack pointer + dad sp + shld spsav +;#idb + + lxi sp,msbt+2 ; point to test-case machine state + +;#idb pop iy +;#idb pop ix both replaced by following code +;#idb Just dummy out ix/iy with copies of hl + pop h ; and load all regs + pop h +;#idb + + pop h + pop d + pop b + pop psw + +;#idb ld sp,(spbt) replaced with the following code +;#idb HL is copied/restored before/after load so no state changed + shld temp + lhld spbt + sphl + lhld temp +;#idb + +iut: ds 4 ; max 4 byte instruction under test + +;#idb ld (spat),sp replaced with the following code +;#idb Must be very careful to preserve registers and flag +;#idb state resulting from the test. The temptation is to use the +;#idb stack - but that doesn't work because of the way the app +;#idb uses SP as a quick way of pointing to memory. +;#idb Bit of a code smell, but I can't think of an easier way. + shld temp + lxi h,0 + jc temp1 ;jump on the state of the C flag set in the test + + dad sp ;this code will clear the C flag (0 + nnnn = nc) + jmp temp2 ;C flag is same state as before + +temp1: dad sp ;this code will clear the C flag (0 + nnnn = nc) + stc ;C flage needs re-setting to preserve state + +temp2: shld spat + lhld temp +;#idb + + lxi sp,spat + push psw ; save other registers + push b + push d + push h + +;#idb push ix +;#idb push iy both replaced by following code +;#idb Must match change made to pops made before test + push h + push h +;#idb + +;#idb ld sp,(spsav) replaced with following code +;#idb No need to preserve state + lhld spsav ; restore stack pointer + sphl +;#idb + + ei ; enable interrupts + lhld msbt ; copy memory operand + shld msat + lxi h,flgsat ; flags after test + mov a,m +flgmsk: ani 0ffh ; mask-out irrelevant bits (self-modified code!) + mov m,a + mvi b,16 ; total of 16 bytes of state + lxi d,msat + lxi h,crcval +tcrc: ldax d + inx d + call updcrc ; accumulate crc of this test case + dcr b + jnz tcrc + if 0 + mvi e,' ' + mvi c,2 + call bdos + lxi h,crcval + call phex8 + lxi d,crlf + mvi c,9 + call bdos + lxi h,msat + mvi b,16 + call hexstr + lxi d,crlf + mvi c,9 + call bdos + endif + pop h + pop d + pop b + pop psw + ret + +;#idb Added to store HL state +temp: ds 2 +;#idb + +; machine state after test +msat: ds 14 ; memop,iy,ix,hl,de,bc,af +spat: ds 2 ; stack pointer after test +flgsat equ spat-2 ; flags + +spsav: ds 2 ; saved stack pointer + +; display hex string (pointer in hl, byte count in b) +hexstr: mov a,m + call phex2 + inx h + dcr b + jnz hexstr + ret + +; display hex +; display the big-endian 32-bit value pointed to by hl +phex8: push psw + push b + push h + mvi b,4 +ph8lp: mov a,m + call phex2 + inx h + dcr b + jnz ph8lp + pop h + pop b + pop psw + ret + +; display byte in a +phex2: push psw + rrc + rrc + rrc + rrc + call phex1 + pop psw +; fall through + +; display low nibble in a +phex1: push psw + push b + push d + push h + ani 0fh + cpi 10 + jc ph11 + adi 'a'-'9'-1 +ph11: adi '0' + mov e,a + mvi c,2 + call bdos + pop h + pop d + pop b + pop psw + ret + +bdos: push psw + push b + push d + push h + call 5 + pop h + pop d + pop b + pop psw + ret + +msg1: db '8080 instruction exerciser (KR580VM80A CPU)',10,13,'$' +msg2: db 'Tests complete$' +okmsg: db ' OK',10,13,'$' +ermsg1: db ' ERROR **** crc expected:$' +ermsg2: db ' found:$' +crlf: db 10,13,'$' + +; compare crc +; hl points to value to compare to crcval +cmpcrc: push b + push d + push h + lxi d,crcval + mvi b,4 +cclp: ldax d + cmp m + jnz cce + inx h + inx d + dcr b + jnz cclp +cce: pop h + pop d + pop b + ret + +; 32-bit crc routine +; entry: a contains next byte, hl points to crc +; exit: crc updated +updcrc: push psw + push b + push d + push h + push h + lxi d,3 + dad d ; point to low byte of old crc + xra m ; xor with new byte + mov l,a + mvi h,0 + dad h ; use result as index into table of 4 byte entries + dad h + xchg + lxi h,crctab + dad d ; point to selected entry in crctab + xchg + pop h + lxi b,4 ; c = byte count, b = accumulator +crclp: ldax d + xra b + mov b,m + mov m,a + inx d + inx h + dcr c + jnz crclp + if 0 + lxi h,crcval + call phex8 + lxi d,crlf + mvi c,9 + call bdos + endif + pop h + pop d + pop b + pop psw + ret + +initcrc:push psw + push b + push h + lxi h,crcval + mvi a,0ffh + mvi b,4 +icrclp: mov m,a + inx h + dcr b + jnz icrclp + pop h + pop b + pop psw + ret + +crcval: ds 4 + +crctab: db 000h,000h,000h,000h + db 077h,007h,030h,096h + db 0eeh,00eh,061h,02ch + db 099h,009h,051h,0bah + db 007h,06dh,0c4h,019h + db 070h,06ah,0f4h,08fh + db 0e9h,063h,0a5h,035h + db 09eh,064h,095h,0a3h + db 00eh,0dbh,088h,032h + db 079h,0dch,0b8h,0a4h + db 0e0h,0d5h,0e9h,01eh + db 097h,0d2h,0d9h,088h + db 009h,0b6h,04ch,02bh + db 07eh,0b1h,07ch,0bdh + db 0e7h,0b8h,02dh,007h + db 090h,0bfh,01dh,091h + db 01dh,0b7h,010h,064h + db 06ah,0b0h,020h,0f2h + db 0f3h,0b9h,071h,048h + db 084h,0beh,041h,0deh + db 01ah,0dah,0d4h,07dh + db 06dh,0ddh,0e4h,0ebh + db 0f4h,0d4h,0b5h,051h + db 083h,0d3h,085h,0c7h + db 013h,06ch,098h,056h + db 064h,06bh,0a8h,0c0h + db 0fdh,062h,0f9h,07ah + db 08ah,065h,0c9h,0ech + db 014h,001h,05ch,04fh + db 063h,006h,06ch,0d9h + db 0fah,00fh,03dh,063h + db 08dh,008h,00dh,0f5h + db 03bh,06eh,020h,0c8h + db 04ch,069h,010h,05eh + db 0d5h,060h,041h,0e4h + db 0a2h,067h,071h,072h + db 03ch,003h,0e4h,0d1h + db 04bh,004h,0d4h,047h + db 0d2h,00dh,085h,0fdh + db 0a5h,00ah,0b5h,06bh + db 035h,0b5h,0a8h,0fah + db 042h,0b2h,098h,06ch + db 0dbh,0bbh,0c9h,0d6h + db 0ach,0bch,0f9h,040h + db 032h,0d8h,06ch,0e3h + db 045h,0dfh,05ch,075h + db 0dch,0d6h,00dh,0cfh + db 0abh,0d1h,03dh,059h + db 026h,0d9h,030h,0ach + db 051h,0deh,000h,03ah + db 0c8h,0d7h,051h,080h + db 0bfh,0d0h,061h,016h + db 021h,0b4h,0f4h,0b5h + db 056h,0b3h,0c4h,023h + db 0cfh,0bah,095h,099h + db 0b8h,0bdh,0a5h,00fh + db 028h,002h,0b8h,09eh + db 05fh,005h,088h,008h + db 0c6h,00ch,0d9h,0b2h + db 0b1h,00bh,0e9h,024h + db 02fh,06fh,07ch,087h + db 058h,068h,04ch,011h + db 0c1h,061h,01dh,0abh + db 0b6h,066h,02dh,03dh + db 076h,0dch,041h,090h + db 001h,0dbh,071h,006h + db 098h,0d2h,020h,0bch + db 0efh,0d5h,010h,02ah + db 071h,0b1h,085h,089h + db 006h,0b6h,0b5h,01fh + db 09fh,0bfh,0e4h,0a5h + db 0e8h,0b8h,0d4h,033h + db 078h,007h,0c9h,0a2h + db 00fh,000h,0f9h,034h + db 096h,009h,0a8h,08eh + db 0e1h,00eh,098h,018h + db 07fh,06ah,00dh,0bbh + db 008h,06dh,03dh,02dh + db 091h,064h,06ch,097h + db 0e6h,063h,05ch,001h + db 06bh,06bh,051h,0f4h + db 01ch,06ch,061h,062h + db 085h,065h,030h,0d8h + db 0f2h,062h,000h,04eh + db 06ch,006h,095h,0edh + db 01bh,001h,0a5h,07bh + db 082h,008h,0f4h,0c1h + db 0f5h,00fh,0c4h,057h + db 065h,0b0h,0d9h,0c6h + db 012h,0b7h,0e9h,050h + db 08bh,0beh,0b8h,0eah + db 0fch,0b9h,088h,07ch + db 062h,0ddh,01dh,0dfh + db 015h,0dah,02dh,049h + db 08ch,0d3h,07ch,0f3h + db 0fbh,0d4h,04ch,065h + db 04dh,0b2h,061h,058h + db 03ah,0b5h,051h,0ceh + db 0a3h,0bch,000h,074h + db 0d4h,0bbh,030h,0e2h + db 04ah,0dfh,0a5h,041h + db 03dh,0d8h,095h,0d7h + db 0a4h,0d1h,0c4h,06dh + db 0d3h,0d6h,0f4h,0fbh + db 043h,069h,0e9h,06ah + db 034h,06eh,0d9h,0fch + db 0adh,067h,088h,046h + db 0dah,060h,0b8h,0d0h + db 044h,004h,02dh,073h + db 033h,003h,01dh,0e5h + db 0aah,00ah,04ch,05fh + db 0ddh,00dh,07ch,0c9h + db 050h,005h,071h,03ch + db 027h,002h,041h,0aah + db 0beh,00bh,010h,010h + db 0c9h,00ch,020h,086h + db 057h,068h,0b5h,025h + db 020h,06fh,085h,0b3h + db 0b9h,066h,0d4h,009h + db 0ceh,061h,0e4h,09fh + db 05eh,0deh,0f9h,00eh + db 029h,0d9h,0c9h,098h + db 0b0h,0d0h,098h,022h + db 0c7h,0d7h,0a8h,0b4h + db 059h,0b3h,03dh,017h + db 02eh,0b4h,00dh,081h + db 0b7h,0bdh,05ch,03bh + db 0c0h,0bah,06ch,0adh + db 0edh,0b8h,083h,020h + db 09ah,0bfh,0b3h,0b6h + db 003h,0b6h,0e2h,00ch + db 074h,0b1h,0d2h,09ah + db 0eah,0d5h,047h,039h + db 09dh,0d2h,077h,0afh + db 004h,0dbh,026h,015h + db 073h,0dch,016h,083h + db 0e3h,063h,00bh,012h + db 094h,064h,03bh,084h + db 00dh,06dh,06ah,03eh + db 07ah,06ah,05ah,0a8h + db 0e4h,00eh,0cfh,00bh + db 093h,009h,0ffh,09dh + db 00ah,000h,0aeh,027h + db 07dh,007h,09eh,0b1h + db 0f0h,00fh,093h,044h + db 087h,008h,0a3h,0d2h + db 01eh,001h,0f2h,068h + db 069h,006h,0c2h,0feh + db 0f7h,062h,057h,05dh + db 080h,065h,067h,0cbh + db 019h,06ch,036h,071h + db 06eh,06bh,006h,0e7h + db 0feh,0d4h,01bh,076h + db 089h,0d3h,02bh,0e0h + db 010h,0dah,07ah,05ah + db 067h,0ddh,04ah,0cch + db 0f9h,0b9h,0dfh,06fh + db 08eh,0beh,0efh,0f9h + db 017h,0b7h,0beh,043h + db 060h,0b0h,08eh,0d5h + db 0d6h,0d6h,0a3h,0e8h + db 0a1h,0d1h,093h,07eh + db 038h,0d8h,0c2h,0c4h + db 04fh,0dfh,0f2h,052h + db 0d1h,0bbh,067h,0f1h + db 0a6h,0bch,057h,067h + db 03fh,0b5h,006h,0ddh + db 048h,0b2h,036h,04bh + db 0d8h,00dh,02bh,0dah + db 0afh,00ah,01bh,04ch + db 036h,003h,04ah,0f6h + db 041h,004h,07ah,060h + db 0dfh,060h,0efh,0c3h + db 0a8h,067h,0dfh,055h + db 031h,06eh,08eh,0efh + db 046h,069h,0beh,079h + db 0cbh,061h,0b3h,08ch + db 0bch,066h,083h,01ah + db 025h,06fh,0d2h,0a0h + db 052h,068h,0e2h,036h + db 0cch,00ch,077h,095h + db 0bbh,00bh,047h,003h + db 022h,002h,016h,0b9h + db 055h,005h,026h,02fh + db 0c5h,0bah,03bh,0beh + db 0b2h,0bdh,00bh,028h + db 02bh,0b4h,05ah,092h + db 05ch,0b3h,06ah,004h + db 0c2h,0d7h,0ffh,0a7h + db 0b5h,0d0h,0cfh,031h + db 02ch,0d9h,09eh,08bh + db 05bh,0deh,0aeh,01dh + db 09bh,064h,0c2h,0b0h + db 0ech,063h,0f2h,026h + db 075h,06ah,0a3h,09ch + db 002h,06dh,093h,00ah + db 09ch,009h,006h,0a9h + db 0ebh,00eh,036h,03fh + db 072h,007h,067h,085h + db 005h,000h,057h,013h + db 095h,0bfh,04ah,082h + db 0e2h,0b8h,07ah,014h + db 07bh,0b1h,02bh,0aeh + db 00ch,0b6h,01bh,038h + db 092h,0d2h,08eh,09bh + db 0e5h,0d5h,0beh,00dh + db 07ch,0dch,0efh,0b7h + db 00bh,0dbh,0dfh,021h + db 086h,0d3h,0d2h,0d4h + db 0f1h,0d4h,0e2h,042h + db 068h,0ddh,0b3h,0f8h + db 01fh,0dah,083h,06eh + db 081h,0beh,016h,0cdh + db 0f6h,0b9h,026h,05bh + db 06fh,0b0h,077h,0e1h + db 018h,0b7h,047h,077h + db 088h,008h,05ah,0e6h + db 0ffh,00fh,06ah,070h + db 066h,006h,03bh,0cah + db 011h,001h,00bh,05ch + db 08fh,065h,09eh,0ffh + db 0f8h,062h,0aeh,069h + db 061h,06bh,0ffh,0d3h + db 016h,06ch,0cfh,045h + db 0a0h,00ah,0e2h,078h + db 0d7h,00dh,0d2h,0eeh + db 04eh,004h,083h,054h + db 039h,003h,0b3h,0c2h + db 0a7h,067h,026h,061h + db 0d0h,060h,016h,0f7h + db 049h,069h,047h,04dh + db 03eh,06eh,077h,0dbh + db 0aeh,0d1h,06ah,04ah + db 0d9h,0d6h,05ah,0dch + db 040h,0dfh,00bh,066h + db 037h,0d8h,03bh,0f0h + db 0a9h,0bch,0aeh,053h + db 0deh,0bbh,09eh,0c5h + db 047h,0b2h,0cfh,07fh + db 030h,0b5h,0ffh,0e9h + db 0bdh,0bdh,0f2h,01ch + db 0cah,0bah,0c2h,08ah + db 053h,0b3h,093h,030h + db 024h,0b4h,0a3h,0a6h + db 0bah,0d0h,036h,005h + db 0cdh,0d7h,006h,093h + db 054h,0deh,057h,029h + db 023h,0d9h,067h,0bfh + db 0b3h,066h,07ah,02eh + db 0c4h,061h,04ah,0b8h + db 05dh,068h,01bh,002h + db 02ah,06fh,02bh,094h + db 0b4h,00bh,0beh,037h + db 0c3h,00ch,08eh,0a1h + db 05ah,005h,0dfh,01bh + db 02dh,002h,0efh,08dh + + end + \ No newline at end of file diff --git a/Intel8080/test/roms/8080EXER.COM b/Intel8080/test/roms/8080EXER.COM new file mode 100644 index 0000000000000000000000000000000000000000..a6cb22defe9444878f48ba3737b49d8c46067804 GIT binary patch literal 4608 zcmcJSdt4L87RPrNzs zVS%*t`x z!Iu&jjj)CdEoqQ8I?*(2@(xIQ z@E@cWZF(u3k$inoNxN%6DPas>KVA=CpqI}8d|P`nhGKRVHRPDBuAK#-s^w&_|hmN33IHcI4w;cII>Bf!n3 zP!=1Q6-CQ-tGRABdVame9*Z5B5XFYQc7AcjWy02gGZMh&D8)m3C984TN zsDJF~1=1J_z}74S-lwJP)C)WUd~Mf(tw#^YdY0!zH{u~OZ<7<1m`b0+Y2DcA$E)$e${7zzP$iVmT zZ?58l)X(L<7_IM6_p4>&&)*T@LtzHLNA|x|#OFw*;KLJvk96!Zur&t2+X*|Is}ZFn z5nv)*ZvIE<1pY90%oZ9>2I&7!>#L4u1xLis--)x-^vRG3y&Y3}VJbC!Hn0&K*yafC z0D}Q99412XlUNKiHcS4BN+-au@kk#-=^V(Ud+Y6l zzAj1Bv6Fe^I70s?hDeL#x?v}ywb)m4y-scOofC>pxq*^ts6>qaKi z;Hl8YPfk|xvB}%XJ|NNt4CE1j#oc>uWMmX!3B}zbJG*le$Rv3JR%4DeC+UgwM{}LPm7RPY&bUgl^CI+lEu+wPM8OmT9NxlystfW5G@ycsBsNs2B(RW3S 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Cringle +; +; This program is free software; you can redistribute it and/or +; modify it under the terms of the GNU General Public License +; as published by the Free Software Foundation; either version 2 +; of the License, or (at your option) any later version. +; +; This program is distributed in the hope that it will be useful, +; but WITHOUT ANY WARRANTY; without even the implied warranty of +; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +; GNU General Public License for more details. +; +; You should have received a copy of the GNU General Public License +; along with this program; if not, write to the Free Software +; Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + + +; These tests have two goals. To start with, we assume the worst and +; successively test the instructions needed to continue testing. +; Then we try to test all instructions which cannot be handled by +; zexlax - the crc-based instruction exerciser. + +; Initially errors are 'reported' by jumping to 0. This should reboot +; cp/m, so if the program terminates without any output one of the +; early tests failed. Later errors are reported by outputting an +; address via the bdos conout routine. The address can be located in +; a listing of this program. + +; If the program runs to completion it displays a suitable message. + +;****************************************************************************** +; +; Modified by Ian Bartholomew to run a preliminary test on an 8080 CPU +; +; Assemble using M80 +; +;****************************************************************************** + + .8080 + aseg + org 100h + +start: mvi a,1 ; test simple compares and z/nz jumps + cpi 2 + jz 0 + cpi 1 + jnz 0 + jmp lab0 + hlt ; emergency exit + db 0ffh + +lab0: call lab2 ; does a simple call work? +lab1: jmp 0 ; fail + +lab2: pop h ; check return address + mov a,h + cpi high lab1 + jz lab3 + jmp 0 +lab3: mov a,l + cpi low lab1 + jz lab4 + jmp 0 + +; test presence and uniqueness of all machine registers +; (except ir) +lab4: lxi sp,regs1 + pop psw + pop b + pop d + pop h + lxi sp,regs2+8 + push h + push d + push b + push psw + +v defl 0 + rept 8 + lda regs2+v/2 +v defl v+2 + cpi v + jnz 0 + endm + +; test access to memory via (hl) + lxi h,hlval + mov a,m + cpi 0a5h + jnz 0 + lxi h,hlval+1 + mov a,m + cpi 03ch + jnz 0 + +; test unconditional return + lxi sp,stack + lxi h,reta + push h + ret + jmp 0 + +; test instructions needed for hex output +reta: mvi a,0ffh + ani 0fh + cpi 0fh + jnz 0 + mvi a,05ah + ani 0fh + cpi 0ah + jnz 0 + rrc + cpi 05h + jnz 0 + rrc + cpi 82h + jnz 0 + rrc + cpi 41h + jnz 0 + rrc + cpi 0a0h + jnz 0 + lxi h,01234h + push h + pop b + mov a,b + cpi 12h + jnz 0 + mov a,c + cpi 34h + jnz 0 + +; from now on we can report errors by displaying an address + +; test conditional call, ret, jp, jr +tcond macro flag,pcond,ncond,rel + lxi h,&flag + push h + pop psw + c&pcond lab1&pcond + jmp error +lab1&pcond: pop h + lxi h,0d7h xor &flag + push h + pop psw + c&ncond lab2&pcond + jmp error +lab2&pcond: pop h + lxi h,lab3&pcond + push h + lxi h,&flag + push h + pop psw + r&pcond + call error +lab3&pcond: lxi h,lab4&pcond + push h + lxi h,0d7h xor &flag + push h + pop psw + r&ncond + call error +lab4&pcond: lxi h,&flag + push h + pop psw + j&pcond lab5&pcond + call error +lab5&pcond: lxi h,0d7h xor &flag + push h + pop psw + j&ncond lab6&pcond + call error +lab6&pcond: + endm + + tcond 1,c,nc,1 + tcond 4,pe,po,0 + tcond 040h,z,nz,1 + tcond 080h,m,p,0 + +; test indirect jumps + lxi h,lab7 + pchl + call error + +; djnz (and (partially) inc a, inc hl) +lab7: mvi a,0a5h + mvi b,4 +lab8: rrc + dcr b + jnz lab8 + cpi 05ah + cnz error + mvi b,16 +lab9: inr a + dcr b + jnz lab9 + cpi 06ah + cnz error + mvi b,0 + lxi h,0 +lab10: inx h + dcr b + jnz lab10 + mov a,h + cpi 1 + cnz error + mov a,l + cpi 0 + cnz error + +allok: lxi d,okmsg + mvi c,9 + call 5 + jmp 0 + +okmsg: db '8080 Preliminary tests complete$' + +; display address at top of stack and exit +error: pop b + mvi h,high hextab + mov a,b + rrc + rrc + rrc + rrc + ani 15 + mov l,a + mov a,m + call conout + mov a,b + ani 15 + mov l,a + mov a,m + call conout + mov a,c + rrc + rrc + rrc + rrc + ani 15 + mov l,a + mov a,m + call conout + mov a,c + ani 15 + mov l,a + mov a,m + call conout + mvi a,13 + call conout + mvi a,10 + call conout + jmp 0 + +conout: push psw + push b + push d + push h + mvi c,2 + mov e,a + call 5 + pop h + pop d + pop b + pop psw + ret + +v defl 0 +regs1: rept 8 +v defl v+2 + db v + endm + +regs2: ds 8,0 + +hlval: db 0a5h,03ch + +; skip to next page boundary + org (($+255)/256)*256 +hextab: db '0123456789abcdef' + ds 240 + +stack equ $ + + end start + diff --git a/Intel8080/test/roms/8085EXER.MAC b/Intel8080/test/roms/8085EXER.MAC new file mode 100644 index 0000000..d142076 --- /dev/null +++ b/Intel8080/test/roms/8085EXER.MAC @@ -0,0 +1,1284 @@ + title 'Z80 instruction set exerciser' + +; zexlax.z80 - Z80 instruction set exerciser +; Copyright (C) 1994 Frank D. Cringle +; +; This program is free software; you can redistribute it and/or +; modify it under the terms of the GNU General Public License +; as published by the Free Software Foundation; either version 2 +; of the License, or (at your option) any later version. +; +; This program is distributed in the hope that it will be useful, +; but WITHOUT ANY WARRANTY; without even the implied warranty of +; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +; GNU General Public License for more details. +; +; You should have received a copy of the GNU General Public License +; along with this program; if not, write to the Free Software +; Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +; +;****************************************************************************** +; +; Modified to exercise an 8085 by Ian Bartholomew, October 2009 +; +; I have made the following changes - +; +; Converted all mnemonics to 8080 and rewritten any Z80 code used +; in the original exerciser. Changes are tagged with a #idb in the +; source code listing. +; +; Removed any test descriptors that are not used. +; +; Changed the macro definitions to work in M80 +; +; The machine state snapshot has been changed to remove the IX/IY registers. +; They have been replaced by two more copies of HL to obviate the need +; for major changes in the exerciser code. +; +; Changed flag mask in all tests to 0d5h to reflect that in the 8085 the unused bits +; in the flag register are undefined- [S Z X AC X P X C] +; +;****************************************************************************** + + .8080 + aseg + org 100h + +begin: jmp start + +; machine state before test (needs to be at predictably constant address) +msbt: ds 14 +spbt: ds 2 + +; For the purposes of this test program, the machine state consists of: +; a 2 byte memory operand, followed by +; the registers iy,ix,hl,de,bc,af,sp +; for a total of 16 bytes. + +; The program tests instructions (or groups of similar instructions) +; by cycling through a sequence of machine states, executing the test +; instruction for each one and running a 32-bit crc over the resulting +; machine states. At the end of the sequence the crc is compared to +; an expected value that was found empirically on a real Z80. + +; A test case is defined by a descriptor which consists of: +; a flag mask byte, +; the base case, +; the incement vector, +; the shift vector, +; the expected crc, +; a short descriptive message. +; +; The flag mask byte is used to prevent undefined flag bits from +; influencing the results. Documented flags are as per Mostek Z80 +; Technical Manual. +; +; The next three parts of the descriptor are 20 byte vectors +; corresponding to a 4 byte instruction and a 16 byte machine state. +; The first part is the base case, which is the first test case of +; the sequence. This base is then modified according to the next 2 +; vectors. Each 1 bit in the increment vector specifies a bit to be +; cycled in the form of a binary counter. For instance, if the byte +; corresponding to the accumulator is set to 0ffh in the increment +; vector, the test will be repeated for all 256 values of the +; accumulator. Note that 1 bits don't have to be contiguous. The +; number of test cases 'caused' by the increment vector is equal to +; 2^(number of 1 bits). The shift vector is similar, but specifies a +; set of bits in the test case that are to be successively inverted. +; Thus the shift vector 'causes' a number of test cases equal to the +; number of 1 bits in it. + +; The total number of test cases is the product of those caused by the +; counter and shift vectors and can easily become unweildy. Each +; individual test case can take a few milliseconds to execute, due to +; the overhead of test setup and crc calculation, so test design is a +; compromise between coverage and execution time. + +; This program is designed to detect differences between +; implementations and is not ideal for diagnosing the causes of any +; discrepancies. However, provided a reference implementation (or +; real system) is available, a failing test case can be isolated by +; hand using a binary search of the test space. + + +start: lhld 6 + sphl + lxi d,msg1 + mvi c,9 + call bdos + + lxi h,tests ; first test case +loop: mov a,m ; end of list ? + inx h + ora m + jz done + dcx h + call stt + jmp loop + +done: lxi d,msg2 + mvi c,9 + call bdos + jmp 0 ; warm boot + +tests: + dw add16 + dw alu8i + dw alu8r + dw daa + dw inca + dw incb + dw incbc + dw incc + dw incd + dw incde + dw ince + dw inch + dw inchl + dw incl + dw incm + dw incsp + dw ld162 + dw ld166 + dw ld16im + dw ld8bd + dw ld8im + dw ld8rr + dw lda + dw rot8080 + dw stabd + dw 0 + +tstr macro insn,memop,hliy,hlix,hl,de,bc,flags,acc,sp + local lab +lab: db insn + ds lab+4-$,0 + dw memop,hliy,hlix,hl,de,bc + db flags + db acc + dw sp + if $-lab ne 20 + error 'missing parameter' + endif + endm + +tmsg macro m + local lab +lab: db m + if $ ge lab+30 + error 'message too long' + else + ds lab+30-$,'.' + endif + db '$' + endm + +; add hl, (19,456 cycles) +add16: db 0d5h ; flag mask + tstr 9,0c4a5h,0c4c7h,0d226h,0a050h,058eah,08566h,0c6h,0deh,09bc9h + tstr 030h,0,0,0,0f821h,0,0,0,0,0 ; (512 cycles) + tstr 0,0,0,0,-1,-1,-1,0d7h,0,-1 ; (38 cycles) + db 0,0,0,0 ; expected crc + tmsg 'dad ' + +; aluop a,nn (28,672 cycles) +alu8i: db 0d5h ; flag mask + tstr 0c6h,09140h,07e3ch,07a67h,0df6dh,05b61h,00b29h,010h,066h,085b2h + tstr 038h,0,0,0,0,0,0,0,-1,0 ; (2048 cycles) + tstr <0,-1>,0,0,0,0,0,0,0d7h,0,0 ; (14 cycles) + db 0,0,0,0 ; expected crc + tmsg 'aluop nn' + +; aluop a, (753,664 cycles) +alu8r: db 0d5h ; flag mask + tstr 080h,0c53eh,0573ah,04c4dh,msbt,0e309h,0a666h,0d0h,03bh,0adbbh + tstr 03fh,0,0,0,0,0,0,0,-1,0 ; (16,384 cycles) + tstr 0,0ffh,0,0,0,-1,-1,0d7h,0,0 ; (46 cycles) + db 0,0,0,0 ; expected crc + tmsg 'aluop ' + +; +daa: db 0d5h ; flag mask + tstr 027h,02141h,009fah,01d60h,0a559h,08d5bh,09079h,004h,08eh,0299dh + tstr 018h,0,0,0,0,0,0,0d7h,-1,0 ; (65,536 cycles) + tstr 0,0,0,0,0,0,0,0,0,0 ; (1 cycle) + db 0,0,0,0 ; expected crc + tmsg '' + +; a (3072 cycles) +inca: db 0d5h ; flag mask + tstr 03ch,04adfh,0d5d8h,0e598h,08a2bh,0a7b0h,0431bh,044h,05ah,0d030h + tstr 001h,0,0,0,0,0,0,0,-1,0 ; (512 cycles) + tstr 0,0,0,0,0,0,0,0d7h,0,0 ; (6 cycles) + db 0,0,0,0 ; expected crc + tmsg ' a' + +; b (3072 cycles) +incb: db 0d5h ; flag mask + tstr 004h,0d623h,0432dh,07a61h,08180h,05a86h,01e85h,086h,058h,09bbbh + tstr 001h,0,0,0,0,0,0ff00h,0,0,0 ; (512 cycles) + tstr 0,0,0,0,0,0,0,0d7h,0,0 ; (6 cycles) + db 0,0,0,0 ; expected crc + tmsg ' b' + +; bc (1536 cycles) +incbc: db 0d5h ; flag mask + tstr 003h,0cd97h,044abh,08dc9h,0e3e3h,011cch,0e8a4h,002h,049h,02a4dh + tstr 008h,0,0,0,0,0,0f821h,0,0,0 ; (256 cycles) + tstr 0,0,0,0,0,0,0,0d7h,0,0 ; (6 cycles) + db 0,0,0,0 ; expected crc + tmsg ' b' + +; c (3072 cycles) +incc: db 0d5h ; flag mask + tstr 00ch,0d789h,00935h,0055bh,09f85h,08b27h,0d208h,095h,005h,00660h + tstr 001h,0,0,0,0,0,0ffh,0,0,0 ; (512 cycles) + tstr 0,0,0,0,0,0,0,0d7h,0,0 ; (6 cycles) + db 0,0,0,0 ; expected crc + tmsg ' c' + +; d (3072 cycles) +incd: db 0d5h ; flag mask + tstr 014h,0a0eah,05fbah,065fbh,0981ch,038cch,0debch,043h,05ch,003bdh + tstr 001h,0,0,0,0,0ff00h,0,0,0,0 ; (512 cycles) + tstr 0,0,0,0,0,0,0,0d7h,0,0 ; (6 cycles) + db 0,0,0,0 ; expected crc + tmsg ' d' + +; de (1536 cycles) +incde: db 0d5h ; flag mask + tstr 013h,0342eh,0131dh,028c9h,00acah,09967h,03a2eh,092h,0f6h,09d54h + tstr 008h,0,0,0,0,0f821h,0,0,0,0 ; (256 cycles) + tstr 0,0,0,0,0,0,0,0d7h,0,0 ; (6 cycles) + db 0,0,0,0 ; expected crc + tmsg ' d' + +; e (3072 cycles) +ince: db 0d5h ; flag mask + tstr 01ch,0602fh,04c0dh,02402h,0e2f5h,0a0f4h,0a10ah,013h,032h,05925h + tstr 001h,0,0,0,0,0ffh,0,0,0,0 ; (512 cycles) + tstr 0,0,0,0,0,0,0,0d7h,0,0 ; (6 cycles) + db 0,0,0,0 ; expected crc + tmsg ' e' + +; h (3072 cycles) +inch: db 0d5h ; flag mask + tstr 024h,01506h,0f2ebh,0e8ddh,0262bh,011a6h,0bc1ah,017h,006h,02818h + tstr 001h,0,0,0,0ff00h,0,0,0,0,0 ; (512 cycles) + tstr 0,0,0,0,0,0,0,0d7h,0,0 ; (6 cycles) + db 0,0,0,0 ; expected crc + tmsg ' h' + +; hl (1536 cycles) +inchl: db 0d5h ; flag mask + tstr 023h,0c3f4h,007a5h,01b6dh,04f04h,0e2c2h,0822ah,057h,0e0h,0c3e1h + tstr 008h,0,0,0,0f821h,0,0,0,0,0 ; (256 cycles) + tstr 0,0,0,0,0,0,0,0d7h,0,0 ; (6 cycles) + db 0,0,0,0 ; expected crc + tmsg ' h' + +; l (3072 cycles) +incl: db 0d5h ; flag mask + tstr 02ch,08031h,0a520h,04356h,0b409h,0f4c1h,0dfa2h,0d1h,03ch,03ea2h + tstr 001h,0,0,0,0ffh,0,0,0,0,0 ; (512 cycles) + tstr 0,0,0,0,0,0,0,0d7h,0,0 ; (6 cycles) + db 0,0,0,0 ; expected crc + tmsg ' l' + +; (hl) (3072 cycles) +incm: db 0d5h ; flag mask + tstr 034h,0b856h,00c7ch,0e53eh,msbt,0877eh,0da58h,015h,05ch,01f37h + tstr 001h,0ffh,0,0,0,0,0,0,0,0 ; (512 cycles) + tstr 0,0,0,0,0,0,0,0d7h,0,0 ; (6 cycles) + db 0,0,0,0 ; expected crc + tmsg ' m' + +; sp (1536 cycles) +incsp: db 0d5h ; flag mask + tstr 033h,0346fh,0d482h,0d169h,0deb6h,0a494h,0f476h,053h,002h,0855bh + tstr 008h,0,0,0,0,0,0,0,0,0f821h ; (256 cycles) + tstr 0,0,0,0,0,0,0,0d7h,0,0 ; (6 cycles) + db 0,0,0,0 ; expected crc + tmsg ' sp' + +; ld hl,(nnnn) (16 cycles) +ld162: db 0d5h ; flag mask + tstr <02ah,low msbt,high msbt>,09863h,07830h,02077h,0b1feh,0b9fah,0abb8h,004h,006h,06015h + tstr 0,0,0,0,0,0,0,0,0,0 ; (1 cycle) + tstr 0,-1,0,0,0,0,0,0,0,0 ; (16 cycles) + db 0,0,0,0 ; expected crc + tmsg 'lhld nnnn' + +; ld (nnnn),hl (16 cycles) +ld166: db 0d5h ; flag mask + tstr <022h,low msbt,high msbt>,0d003h,07772h,07f53h,03f72h,064eah,0e180h,010h,02dh,035e9h + tstr 0,0,0,0,0,0,0,0,0,0 ; (1 cycle) + tstr 0,0,0,0,-1,0,0,0,0,0 ; (16 cycles) + db 0,0,0,0 ; expected crc + tmsg 'shld nnnn' + +; ld ,nnnn (64 cycles) +ld16im: db 0d5h ; flag mask + tstr 1,05c1ch,02d46h,08eb9h,06078h,074b1h,0b30eh,046h,0d1h,030cch + tstr 030h,0,0,0,0,0,0,0,0,0 ; (4 cycles) + tstr <0,0ffh,0ffh>,0,0,0,0,0,0,0,0,0 ; (16 cycles) + db 0,0,0,0 ; expected crc + tmsg 'lxi ,nnnn' + +; ld a,<(bc),(de)> (44 cycles) +ld8bd: db 0d5h ; flag mask + tstr 00ah,0b3a8h,01d2ah,07f8eh,042ach,msbt,msbt,0c6h,0b1h,0ef8eh + tstr 010h,0,0,0,0,0,0,0,0,0 ; (2 cycles) + tstr 0,0ffh,0,0,0,0,0,0d7h,-1,0 ; (22 cycles) + db 0,0,0,0 ; expected crc + tmsg 'ldax ' + +; ld ,nn (64 cycles) +ld8im: db 0d5h ; flag mask + tstr 6,0c407h,0f49dh,0d13dh,00339h,0de89h,07455h,053h,0c0h,05509h + tstr 038h,0,0,0,0,0,0,0,0,0 ; (8 cycles) + tstr 0,0,0,0,0,0,0,0,-1,0 ; (8 cycles) + db 0,0,0,0 ; expected crc + tmsg 'mvi ,nn' + +; ld , (3456 cycles) +ld8rr: db 0d5h ; flag mask + tstr 040h,072a4h,0a024h,061ach,msbt,082c7h,0718fh,097h,08fh,0ef8eh + tstr 03fh,0,0,0,0,0,0,0,0,0 ; (64 cycles) + tstr 0,0ffh,0,0,0,-1,-1,0d7h,-1,0 ; (54 cycles) + db 0,0,0,0 ; expected crc + tmsg 'mov ,' + +; ld a,(nnnn) / ld (nnnn),a (44 cycles) +lda: db 0d5h ; flag mask + tstr <032h,low msbt,high msbt>,0fd68h,0f4ech,044a0h,0b543h,00653h,0cdbah,0d2h,04fh,01fd8h + tstr 008h,0,0,0,0,0,0,0,0,0 ; (2 cycle) + tstr 0,0ffh,0,0,0,0,0,0d7h,-1,0 ; (22 cycles) + db 0,0,0,0 ; expected crc + tmsg 'sta nnnn / lda nnnn' + +; (6144 cycles) +rot8080: db 0d5h ; flag mask + tstr 7,0cb92h,06d43h,00a90h,0c284h,00c53h,0f50eh,091h,0ebh,040fch + tstr 018h,0,0,0,0,0,0,0,-1,0 ; (1024 cycles) + tstr 0,0,0,0,0,0,0,0d7h,0,0 ; (6 cycles) + db 0,0,0,0 ; expected crc + tmsg '' + +; ld (),a (96 cycles) +stabd: db 0d5h ; flag mask + tstr 2,00c3bh,0b592h,06cffh,0959eh,msbt,msbt+1,0c1h,021h,0bde7h + tstr 018h,0,0,0,0,0,0,0,0,0 ; (4 cycles) + tstr 0,-1,0,0,0,0,0,0,-1,0 ; (24 cycles) + db 0,0,0,0 ; expected crc + tmsg 'stax ' + +; start test pointed to by (hl) +stt: push h + mov a,m ; get pointer to test + inx h + mov h,m + mov l,a + mov a,m ; flag mask + sta flgmsk+1 + inx h + push h + lxi d,20 + dad d ; point to incmask + lxi d,counter + call initmask + pop h + push h + lxi d,20+20 + dad d ; point to scanmask + lxi d,shifter + call initmask + lxi h,shifter + mvi m,1 ; first bit + pop h + push h + lxi d,iut ; copy initial instruction under test + lxi b,4 + +;#idb ldir replaced with following code +ldir1: mov a,m + stax d + inx h + inx d + dcx b + mov a,b + ora c + jnz ldir1 +;#idb + + lxi d,msbt ; copy initial machine state + lxi b,16 + +;#idb ldir replaced with following code +ldir2: mov a,m + stax d + inx h + inx d + dcx b + mov a,b + ora c + jnz ldir2 +;#idb + + lxi d,20+20+4 ; skip incmask, scanmask and expcrc + dad d + xchg + mvi c,9 + call bdos ; show test name + call initcrc ; initialise crc +; test loop +tlp: lda iut + cpi 076h ; pragmatically avoid halt intructions + jz tlp2 + ani 0dfh + cpi 0ddh + jnz tlp1 + lda iut+1 + cpi 076h +tlp1: cnz test ; execute the test instruction +tlp2: call count ; increment the counter + cnz shift ; shift the scan bit + pop h ; pointer to test case + jz tlp3 ; done if shift returned NZ + lxi d,20+20+20 + dad d ; point to expected crc + call cmpcrc + lxi d,okmsg + jz tlpok + lxi d,ermsg1 + mvi c,9 + call bdos + call phex8 + lxi d,ermsg2 + mvi c,9 + call bdos + lxi h,crcval + call phex8 + lxi d,crlf +tlpok: mvi c,9 + call bdos + pop h + inx h + inx h + ret + +tlp3: push h + mvi a,1 ; initialise count and shift scanners + sta cntbit + sta shfbit + lxi h,counter + shld cntbyt + lxi h,shifter + shld shfbyt + + mvi b,4 ; bytes in iut field + pop h ; pointer to test case + push h + lxi d,iut + call setup ; setup iut + mvi b,16 ; bytes in machine state + lxi d,msbt + call setup ; setup machine state + jmp tlp + +; setup a field of the test case +; b = number of bytes +; hl = pointer to base case +; de = destination +setup: call subyte + inx h + dcr b + jnz setup + ret + +subyte: push b + push d + push h + mov c,m ; get base byte + lxi d,20 + dad d ; point to incmask + mov a,m + cpi 0 + jz subshf + mvi b,8 ; 8 bits +subclp: rrc + push psw + mvi a,0 + cc nxtcbit ; get next counter bit if mask bit was set + xra c ; flip bit if counter bit was set + rrc + mov c,a + pop psw + dcr b + jnz subclp + mvi b,8 +subshf: lxi d,20 + dad d ; point to shift mask + mov a,m + cpi 0 + jz substr + mvi b,8 ; 8 bits +sbshf1: rrc + push psw + mvi a,0 + cc nxtsbit ; get next shifter bit if mask bit was set + xra c ; flip bit if shifter bit was set + rrc + mov c,a + pop psw + dcr b + jnz sbshf1 +substr: pop h + pop d + mov a,c + stax d ; mangled byte to destination + inx d + pop b + ret + +; get next counter bit in low bit of a +cntbit: ds 1 +cntbyt: ds 2 + +nxtcbit: push b + push h + lhld cntbyt + mov b,m + lxi h,cntbit + mov a,m + mov c,a + rlc + mov m,a + cpi 1 + jnz ncb1 + lhld cntbyt + inx h + shld cntbyt +ncb1: mov a,b + ana c + pop h + pop b + rz + mvi a,1 + ret + +; get next shifter bit in low bit of a +shfbit: ds 1 +shfbyt: ds 2 + +nxtsbit: push b + push h + lhld shfbyt + mov b,m + lxi h,shfbit + mov a,m + mov c,a + rlc + mov m,a + cpi 1 + jnz nsb1 + lhld shfbyt + inx h + shld shfbyt +nsb1: mov a,b + ana c + pop h + pop b + rz + mvi a,1 + ret + + +; clear memory at hl, bc bytes +clrmem: push psw + push b + push d + push h + mvi m,0 + mov d,h + mov e,l + inx d + dcx b + +;#idb ldir replaced with following code +ldir3: mov a,m + stax d + inx h + inx d + dcx b + mov a,b + ora c + jnz ldir3 +;#idb + + pop h + pop d + pop b + pop psw + ret + +; initialise counter or shifter +; de = pointer to work area for counter or shifter +; hl = pointer to mask +initmask: + push d + xchg + lxi b,20+20 + call clrmem ; clear work area + xchg + mvi b,20 ; byte counter + mvi c,1 ; first bit + mvi d,0 ; bit counter +imlp: mov e,m +imlp1: mov a,e + ana c + jz imlp2 + inr d +imlp2: mov a,c + rlc + mov c,a + cpi 1 + jnz imlp1 + inx h + dcr b + jnz imlp +; got number of 1-bits in mask in reg d + mov a,d + ani 0f8h + rrc + rrc + rrc ; divide by 8 (get byte offset) + mov l,a + mvi h,0 + mov a,d + ani 7 ; bit offset + inr a + mov b,a + mvi a,080h +imlp3: rlc + dcr b + jnz imlp3 + pop d + dad d + lxi d,20 + dad d + mov m,a + ret + +; multi-byte counter +count: push b + push d + push h + lxi h,counter ; 20 byte counter starts here + lxi d,20 ; somewhere in here is the stop bit + xchg + dad d + xchg +cntlp: inr m + mov a,m + cpi 0 + jz cntlp1 ; overflow to next byte + mov b,a + ldax d + ana b ; test for terminal value + jz cntend + mvi m,0 ; reset to zero +cntend: pop b + pop d + pop h + ret + +cntlp1: inx h + inx d + jmp cntlp + + +; multi-byte shifter +shift: push b + push d + push h + lxi h,shifter ; 20 byte shift register starts here + lxi d,20 ; somewhere in here is the stop bit + xchg + dad d + xchg +shflp: mov a,m + ora a + jz shflp1 + mov b,a + ldax d + ana b + jnz shlpe + mov a,b + rlc + cpi 1 + jnz shflp2 + mvi m,0 + inx h + inx d +shflp2: mov m,a + xra a ; set Z +shlpe: pop h + pop d + pop b + ret +shflp1: inx h + inx d + jmp shflp + +counter: ds 2*20 +shifter: ds 2*20 + +; test harness +test: push psw + push b + push d + push h + if 0 + lxi d,crlf + mvi c,9 + call bdos + lxi h,iut + mvi b,4 + call hexstr + mvi e,' ' + mvi c,2 + call bdos + mvi b,16 + lxi h,msbt + call hexstr + endif + di ; disable interrupts + +;#idb ld (spsav),sp replaced by following code +;#idb All registers and flages are immediately overwritten so +;#idb no need to preserve any state. + lxi h,0 ; save stack pointer + dad sp + shld spsav +;#idb + + lxi sp,msbt+2 ; point to test-case machine state + +;#idb pop iy +;#idb pop ix both replaced by following code +;#idb Just dummy out ix/iy with copies of hl + pop h ; and load all regs + pop h +;#idb + + pop h + pop d + pop b + pop psw + +;#idb ld sp,(spbt) replaced with the following code +;#idb HL is copied/restored before/after load so no state changed + shld temp + lhld spbt + sphl + lhld temp +;#idb + +iut: ds 4 ; max 4 byte instruction under test + +;#idb ld (spat),sp replaced with the following code +;#idb Must be very careful to preserve registers and flag +;#idb state resulting from the test. The temptation is to use the +;#idb stack - but that doesn't work because of the way the app +;#idb uses SP as a quick way of pointing to memory. +;#idb Bit of a code smell, but I can't think of an easier way. + shld temp + lxi h,0 + jc temp1 ;jump on the state of the C flag set in the test + + dad sp ;this code will clear the C flag (0 + nnnn = nc) + jmp temp2 ;C flag is same state as before + +temp1: dad sp ;this code will clear the C flag (0 + nnnn = nc) + stc ;C flage needs re-setting to preserve state + +temp2: shld spat + lhld temp +;#idb + + lxi sp,spat + push psw ; save other registers + push b + push d + push h + +;#idb push ix +;#idb push iy both replaced by following code +;#idb Must match change made to pops made before test + push h + push h +;#idb + +;#idb ld sp,(spsav) replaced with following code +;#idb No need to preserve state + lhld spsav ; restore stack pointer + sphl +;#idb + + ei ; enable interrupts + lhld msbt ; copy memory operand + shld msat + lxi h,flgsat ; flags after test + mov a,m +flgmsk: ani 0ffh ; mask-out irrelevant bits (self-modified code!) + mov m,a + mvi b,16 ; total of 16 bytes of state + lxi d,msat + lxi h,crcval +tcrc: ldax d + inx d + call updcrc ; accumulate crc of this test case + dcr b + jnz tcrc + if 0 + mvi e,' ' + mvi c,2 + call bdos + lxi h,crcval + call phex8 + lxi d,crlf + mvi c,9 + call bdos + lxi h,msat + mvi b,16 + call hexstr + lxi d,crlf + mvi c,9 + call bdos + endif + pop h + pop d + pop b + pop psw + ret + +;#idb Added to store HL state +temp: ds 2 +;#idb + +; machine state after test +msat: ds 14 ; memop,iy,ix,hl,de,bc,af +spat: ds 2 ; stack pointer after test +flgsat equ spat-2 ; flags + +spsav: ds 2 ; saved stack pointer + +; display hex string (pointer in hl, byte count in b) +hexstr: mov a,m + call phex2 + inx h + dcr b + jnz hexstr + ret + +; display hex +; display the big-endian 32-bit value pointed to by hl +phex8: push psw + push b + push h + mvi b,4 +ph8lp: mov a,m + call phex2 + inx h + dcr b + jnz ph8lp + pop h + pop b + pop psw + ret + +; display byte in a +phex2: push psw + rrc + rrc + rrc + rrc + call phex1 + pop psw +; fall through + +; display low nibble in a +phex1: push psw + push b + push d + push h + ani 0fh + cpi 10 + jc ph11 + adi 'a'-'9'-1 +ph11: adi '0' + mov e,a + mvi c,2 + call bdos + pop h + pop d + pop b + pop psw + ret + +bdos: push psw + push b + push d + push h + call 5 + pop h + pop d + pop b + pop psw + ret + +msg1: db '8085 instruction exerciser',10,13,'$' +msg2: db 'Tests complete$' +okmsg: db ' OK',10,13,'$' +ermsg1: db ' ERROR **** crc expected:$' +ermsg2: db ' found:$' +crlf: db 10,13,'$' + +; compare crc +; hl points to value to compare to crcval +cmpcrc: push b + push d + push h + lxi d,crcval + mvi b,4 +cclp: ldax d + cmp m + jnz cce + inx h + inx d + dcr b + jnz cclp +cce: pop h + pop d + pop b + ret + +; 32-bit crc routine +; entry: a contains next byte, hl points to crc +; exit: crc updated +updcrc: push psw + push b + push d + push h + push h + lxi d,3 + dad d ; point to low byte of old crc + xra m ; xor with new byte + mov l,a + mvi h,0 + dad h ; use result as index into table of 4 byte entries + dad h + xchg + lxi h,crctab + dad d ; point to selected entry in crctab + xchg + pop h + lxi b,4 ; c = byte count, b = accumulator +crclp: ldax d + xra b + mov b,m + mov m,a + inx d + inx h + dcr c + jnz crclp + if 0 + lxi h,crcval + call phex8 + lxi d,crlf + mvi c,9 + call bdos + endif + pop h + pop d + pop b + pop psw + ret + +initcrc:push psw + push b + push h + lxi h,crcval + mvi a,0ffh + mvi b,4 +icrclp: mov m,a + inx h + dcr b + jnz icrclp + pop h + pop b + pop psw + ret + +crcval: ds 4 + +crctab: db 000h,000h,000h,000h + db 077h,007h,030h,096h + db 0eeh,00eh,061h,02ch + db 099h,009h,051h,0bah + db 007h,06dh,0c4h,019h + db 070h,06ah,0f4h,08fh + db 0e9h,063h,0a5h,035h + db 09eh,064h,095h,0a3h + db 00eh,0dbh,088h,032h + db 079h,0dch,0b8h,0a4h + db 0e0h,0d5h,0e9h,01eh + db 097h,0d2h,0d9h,088h + db 009h,0b6h,04ch,02bh + db 07eh,0b1h,07ch,0bdh + db 0e7h,0b8h,02dh,007h + db 090h,0bfh,01dh,091h + db 01dh,0b7h,010h,064h + db 06ah,0b0h,020h,0f2h + db 0f3h,0b9h,071h,048h + db 084h,0beh,041h,0deh + db 01ah,0dah,0d4h,07dh + db 06dh,0ddh,0e4h,0ebh + db 0f4h,0d4h,0b5h,051h + db 083h,0d3h,085h,0c7h + db 013h,06ch,098h,056h + db 064h,06bh,0a8h,0c0h + db 0fdh,062h,0f9h,07ah + db 08ah,065h,0c9h,0ech + db 014h,001h,05ch,04fh + db 063h,006h,06ch,0d9h + db 0fah,00fh,03dh,063h + db 08dh,008h,00dh,0f5h + db 03bh,06eh,020h,0c8h + db 04ch,069h,010h,05eh + db 0d5h,060h,041h,0e4h + db 0a2h,067h,071h,072h + db 03ch,003h,0e4h,0d1h + db 04bh,004h,0d4h,047h + db 0d2h,00dh,085h,0fdh + db 0a5h,00ah,0b5h,06bh + db 035h,0b5h,0a8h,0fah + db 042h,0b2h,098h,06ch + db 0dbh,0bbh,0c9h,0d6h + db 0ach,0bch,0f9h,040h + db 032h,0d8h,06ch,0e3h + db 045h,0dfh,05ch,075h + db 0dch,0d6h,00dh,0cfh + db 0abh,0d1h,03dh,059h + db 026h,0d9h,030h,0ach + db 051h,0deh,000h,03ah + db 0c8h,0d7h,051h,080h + db 0bfh,0d0h,061h,016h + db 021h,0b4h,0f4h,0b5h + db 056h,0b3h,0c4h,023h + db 0cfh,0bah,095h,099h + db 0b8h,0bdh,0a5h,00fh + db 028h,002h,0b8h,09eh + db 05fh,005h,088h,008h + db 0c6h,00ch,0d9h,0b2h + db 0b1h,00bh,0e9h,024h + db 02fh,06fh,07ch,087h + db 058h,068h,04ch,011h + db 0c1h,061h,01dh,0abh + db 0b6h,066h,02dh,03dh + db 076h,0dch,041h,090h + db 001h,0dbh,071h,006h + db 098h,0d2h,020h,0bch + db 0efh,0d5h,010h,02ah + db 071h,0b1h,085h,089h + db 006h,0b6h,0b5h,01fh + db 09fh,0bfh,0e4h,0a5h + db 0e8h,0b8h,0d4h,033h + db 078h,007h,0c9h,0a2h + db 00fh,000h,0f9h,034h + db 096h,009h,0a8h,08eh + db 0e1h,00eh,098h,018h + db 07fh,06ah,00dh,0bbh + db 008h,06dh,03dh,02dh + db 091h,064h,06ch,097h + db 0e6h,063h,05ch,001h + db 06bh,06bh,051h,0f4h + db 01ch,06ch,061h,062h + db 085h,065h,030h,0d8h + db 0f2h,062h,000h,04eh + db 06ch,006h,095h,0edh + db 01bh,001h,0a5h,07bh + db 082h,008h,0f4h,0c1h + db 0f5h,00fh,0c4h,057h + db 065h,0b0h,0d9h,0c6h + db 012h,0b7h,0e9h,050h + db 08bh,0beh,0b8h,0eah + db 0fch,0b9h,088h,07ch + db 062h,0ddh,01dh,0dfh + db 015h,0dah,02dh,049h + db 08ch,0d3h,07ch,0f3h + db 0fbh,0d4h,04ch,065h + db 04dh,0b2h,061h,058h + db 03ah,0b5h,051h,0ceh + db 0a3h,0bch,000h,074h + db 0d4h,0bbh,030h,0e2h + db 04ah,0dfh,0a5h,041h + db 03dh,0d8h,095h,0d7h + db 0a4h,0d1h,0c4h,06dh + db 0d3h,0d6h,0f4h,0fbh + db 043h,069h,0e9h,06ah + db 034h,06eh,0d9h,0fch + db 0adh,067h,088h,046h + db 0dah,060h,0b8h,0d0h + db 044h,004h,02dh,073h + db 033h,003h,01dh,0e5h + db 0aah,00ah,04ch,05fh + db 0ddh,00dh,07ch,0c9h + db 050h,005h,071h,03ch + db 027h,002h,041h,0aah + db 0beh,00bh,010h,010h + db 0c9h,00ch,020h,086h + db 057h,068h,0b5h,025h + db 020h,06fh,085h,0b3h + db 0b9h,066h,0d4h,009h + db 0ceh,061h,0e4h,09fh + db 05eh,0deh,0f9h,00eh + db 029h,0d9h,0c9h,098h + db 0b0h,0d0h,098h,022h + db 0c7h,0d7h,0a8h,0b4h + db 059h,0b3h,03dh,017h + db 02eh,0b4h,00dh,081h + db 0b7h,0bdh,05ch,03bh + db 0c0h,0bah,06ch,0adh + db 0edh,0b8h,083h,020h + db 09ah,0bfh,0b3h,0b6h + db 003h,0b6h,0e2h,00ch + db 074h,0b1h,0d2h,09ah + db 0eah,0d5h,047h,039h + db 09dh,0d2h,077h,0afh + db 004h,0dbh,026h,015h + db 073h,0dch,016h,083h + db 0e3h,063h,00bh,012h + db 094h,064h,03bh,084h + db 00dh,06dh,06ah,03eh + db 07ah,06ah,05ah,0a8h + db 0e4h,00eh,0cfh,00bh + db 093h,009h,0ffh,09dh + db 00ah,000h,0aeh,027h + db 07dh,007h,09eh,0b1h + db 0f0h,00fh,093h,044h + db 087h,008h,0a3h,0d2h + db 01eh,001h,0f2h,068h + db 069h,006h,0c2h,0feh + db 0f7h,062h,057h,05dh + db 080h,065h,067h,0cbh + db 019h,06ch,036h,071h + db 06eh,06bh,006h,0e7h + db 0feh,0d4h,01bh,076h + db 089h,0d3h,02bh,0e0h + db 010h,0dah,07ah,05ah + db 067h,0ddh,04ah,0cch + db 0f9h,0b9h,0dfh,06fh + db 08eh,0beh,0efh,0f9h + db 017h,0b7h,0beh,043h + db 060h,0b0h,08eh,0d5h + db 0d6h,0d6h,0a3h,0e8h + db 0a1h,0d1h,093h,07eh + db 038h,0d8h,0c2h,0c4h + db 04fh,0dfh,0f2h,052h + db 0d1h,0bbh,067h,0f1h + db 0a6h,0bch,057h,067h + db 03fh,0b5h,006h,0ddh + db 048h,0b2h,036h,04bh + db 0d8h,00dh,02bh,0dah + db 0afh,00ah,01bh,04ch + db 036h,003h,04ah,0f6h + db 041h,004h,07ah,060h + db 0dfh,060h,0efh,0c3h + db 0a8h,067h,0dfh,055h + db 031h,06eh,08eh,0efh + db 046h,069h,0beh,079h + db 0cbh,061h,0b3h,08ch + db 0bch,066h,083h,01ah + db 025h,06fh,0d2h,0a0h + db 052h,068h,0e2h,036h + db 0cch,00ch,077h,095h + db 0bbh,00bh,047h,003h + db 022h,002h,016h,0b9h + db 055h,005h,026h,02fh + db 0c5h,0bah,03bh,0beh + db 0b2h,0bdh,00bh,028h + db 02bh,0b4h,05ah,092h + db 05ch,0b3h,06ah,004h + db 0c2h,0d7h,0ffh,0a7h + db 0b5h,0d0h,0cfh,031h + db 02ch,0d9h,09eh,08bh + db 05bh,0deh,0aeh,01dh + db 09bh,064h,0c2h,0b0h + db 0ech,063h,0f2h,026h + db 075h,06ah,0a3h,09ch + db 002h,06dh,093h,00ah + db 09ch,009h,006h,0a9h + db 0ebh,00eh,036h,03fh + db 072h,007h,067h,085h + db 005h,000h,057h,013h + db 095h,0bfh,04ah,082h + db 0e2h,0b8h,07ah,014h + db 07bh,0b1h,02bh,0aeh + db 00ch,0b6h,01bh,038h + db 092h,0d2h,08eh,09bh + db 0e5h,0d5h,0beh,00dh + db 07ch,0dch,0efh,0b7h + db 00bh,0dbh,0dfh,021h + db 086h,0d3h,0d2h,0d4h + db 0f1h,0d4h,0e2h,042h + db 068h,0ddh,0b3h,0f8h + db 01fh,0dah,083h,06eh + db 081h,0beh,016h,0cdh + db 0f6h,0b9h,026h,05bh + db 06fh,0b0h,077h,0e1h + db 018h,0b7h,047h,077h + db 088h,008h,05ah,0e6h + db 0ffh,00fh,06ah,070h + db 066h,006h,03bh,0cah + db 011h,001h,00bh,05ch + db 08fh,065h,09eh,0ffh + db 0f8h,062h,0aeh,069h + db 061h,06bh,0ffh,0d3h + db 016h,06ch,0cfh,045h + db 0a0h,00ah,0e2h,078h + db 0d7h,00dh,0d2h,0eeh + db 04eh,004h,083h,054h + db 039h,003h,0b3h,0c2h + db 0a7h,067h,026h,061h + db 0d0h,060h,016h,0f7h + db 049h,069h,047h,04dh + db 03eh,06eh,077h,0dbh + db 0aeh,0d1h,06ah,04ah + db 0d9h,0d6h,05ah,0dch + db 040h,0dfh,00bh,066h + db 037h,0d8h,03bh,0f0h + db 0a9h,0bch,0aeh,053h + db 0deh,0bbh,09eh,0c5h + db 047h,0b2h,0cfh,07fh + db 030h,0b5h,0ffh,0e9h + db 0bdh,0bdh,0f2h,01ch + db 0cah,0bah,0c2h,08ah + db 053h,0b3h,093h,030h + db 024h,0b4h,0a3h,0a6h + db 0bah,0d0h,036h,005h + db 0cdh,0d7h,006h,093h + db 054h,0deh,057h,029h + db 023h,0d9h,067h,0bfh + db 0b3h,066h,07ah,02eh + db 0c4h,061h,04ah,0b8h + db 05dh,068h,01bh,002h + db 02ah,06fh,02bh,094h + db 0b4h,00bh,0beh,037h + db 0c3h,00ch,08eh,0a1h + db 05ah,005h,0dfh,01bh + db 02dh,002h,0efh,08dh + + end + \ No newline at end of file diff --git a/Intel8080/test/roms/CPUTEST.COM b/Intel8080/test/roms/CPUTEST.COM new file mode 100644 index 0000000000000000000000000000000000000000..dd535a4790557bd66431bdf2a7347453c4d21c14 GIT binary patch literal 19200 zcmeHOdw3hwmA@m+NUH$#PpbzM?15($t)k&kdg^*9QExV0Uz`h$cGXv7{X8=!l0~ zLXa)D*;s0gP|WHx%Tn6~*G31lL>gnQp(eSdLk=Znrhn6}U+!2CsxaviThOS#VqOr| zUo&g#9D_p-2>MrSsfPus#Ok9JbM*@QlJcQPgw(KbVWK11*|oB}=OR{*o{S3hLh3nT zw{pFMbk&%YwP>Km#Cw(OOe~M~ELzkQmt!sM5jiAZ<7I|g7{c}m)KRMYP zl@rleBHGc6w5g>d8BLVin4X`J@|$++XO~g)G)^=k=m68McMJ}1AuVW;X{2*ImE?1e zZ$@s9C*^Q+G`u_-Igh2dl;7=lFGl2Ly9I&qh8v-^T~4;NwX`=C#vBX>S+L&(0}#6y zTQc;7sqEkrrbEPPw@1;Z)w^^#UwW);W|L90k%HE459IJCsch%pw-kf$GhU zn|?BUz1h$pM-z#70;_?gwvrXamDC}}m(#%3IIt{oWa?dJGIh|L&5agY9LeTTWeL-F zk+Jn8olQdxwL=5h(b;CSzi3fgv@M?Kk=sH&a${6(3`I1VWl`?{mQor^>q$B7s<7)% zm+4g&*A_?RfTNx%O`_5)x-J#x3IkPnHndRG=a!*+&@g9nUOeg$(@IR-oHrd^Dh^aZ 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+;DONATED TO THE "SIG/M" CP/M USER'S GROUP BY: +;KELLY SMITH, MICROCOSM ASSOCIATES +;3055 WACO AVENUE +;SIMI VALLEY, CALIFORNIA, 93065 +;(805) 527-9321 (MODEM, CP/M-NET (TM)) +;(805) 527-0518 (VERBAL) +; + CPU 8080 + ORG 00100H + + LXI H, LOLZ + CALL MSG + JMP CPU ;JUMP TO 8080 CPU DIAGNOSTIC +; +LOLZ: DB "MICROCOSM ASSOCIATES 8080/8085 CPU DIAGNOSTIC VERSION 1.0 (C) 1980", 0dh, 0ah, 24h +; +BDOS EQU 00005H ;BDOS ENTRY TO CP/M +WBOOT: JMP 0 +; +;MESSAGE OUTPUT ROUTINE +; +MSG: MOV A,M ; Get data + CPI '$' ; End? + RZ + CALL PCHAR ; Output + INX H ; Next + JMP MSG ; Do all +; +; +;CHARACTER OUTPUT ROUTINE +; +PCHAR: PUSH PSW + PUSH D + PUSH H + MOV E,A + MVI C,2 + CALL BDOS + POP H + POP D + POP PSW + RET +; +; +; +BYTEO: PUSH PSW + CALL BYTO1 + MOV E,A + CALL PCHAR + POP PSW + CALL BYTO2 + MOV E,A + JMP PCHAR +BYTO1: RRC + RRC + RRC + RRC +BYTO2: ANI 0FH + CPI 0AH + JM BYTO3 + ADI 7 +BYTO3: ADI 30H + RET +; +; +; +;************************************************************ +; MESSAGE TABLE FOR OPERATIONAL CPU TEST +;************************************************************ +; +OKCPU: DB 0DH,0AH + DB "CPU IS OPERATIONAL$" +; +NGCPU: DB 0DH,0AH + DB " CPU HAS FAILED! ERROR EXIT=$" +; +; +; +;************************************************************ +; 8080/8085 CPU TEST/DIAGNOSTIC +;************************************************************ +; +;NOTE: (1) PROGRAM ASSUMES "CALL",AND "LXI SP" INSTRUCTIONS WORK! +; +; (2) INSTRUCTIONS NOT TESTED ARE "HLT","DI","EI", +; AND "RST 0" THRU "RST 7" +; +; +; +;TEST JUMP INSTRUCTIONS AND FLAGS +; +CPU: LXI SP,STACK ;SET THE STACK POINTER + ANI 0 ;INITIALIZE A REG. AND CLEAR ALL FLAGS + JZ J010 ;TEST "JZ" + CALL CPUER +J010: JNC J020 ;TEST "JNC" + CALL CPUER +J020: JPE J030 ;TEST "JPE" + CALL CPUER +J030: JP J040 ;TEST "JP" + CALL CPUER +J040: JNZ J050 ;TEST "JNZ" + JC J050 ;TEST "JC" + JPO J050 ;TEST "JPO" + JM J050 ;TEST "JM" + JMP J060 ;TEST "JMP" (IT'S A LITTLE LATE,BUT WHAT THE HELL! +J050: CALL CPUER +J060: ADI 6 ;A=6,C=0,P=1,S=0,Z=0 + JNZ J070 ;TEST "JNZ" + CALL CPUER +J070: JC J080 ;TEST "JC" + JPO J080 ;TEST "JPO" + JP J090 ;TEST "JP" +J080: CALL CPUER +J090: ADI 070H ;A=76H,C=0,P=0,S=0,Z=0 + JPO J100 ;TEST "JPO" + CALL CPUER +J100: JM J110 ;TEST "JM" + JZ J110 ;TEST "JZ" + JNC J120 ;TEST "JNC" +J110: CALL CPUER +J120: ADI 081H ;A=F7H,C=0,P=0,S=1,Z=0 + JM J130 ;TEST "JM" + CALL CPUER +J130: JZ J140 ;TEST "JZ" + JC J140 ;TEST "JC" + JPO J150 ;TEST "JPO" +J140: CALL CPUER +J150: ADI 0FEH ;A=F5H,C=1,P=1,S=1,Z=0 + JC J160 ;TEST "JC" + CALL CPUER +J160: JZ J170 ;TEST "JZ" + JPO J170 ;TEST "JPO" + JM AIMM ;TEST "JM" +J170: CALL CPUER +; +; +; +;TEST ACCUMULATOR IMMEDIATE INSTRUCTIONS +; +AIMM: CPI 0 ;A=F5H,C=0,Z=0 + JC CPIE ;TEST "CPI" FOR RE-SET CARRY + JZ CPIE ;TEST "CPI" FOR RE-SET ZERO + CPI 0F5H ;A=F5H,C=0,Z=1 + JC CPIE ;TEST "CPI" FOR RE-SET CARRY ("ADI") + JNZ CPIE ;TEST "CPI" FOR RE-SET ZERO + CPI 0FFH ;A=F5H,C=1,Z=0 + JZ CPIE ;TEST "CPI" FOR RE-SET ZERO + JC ACII ;TEST "CPI" FOR SET CARRY +CPIE: CALL CPUER +ACII: ACI 00AH ;A=F5H+0AH+CARRY(1)=0,C=1 + ACI 00AH ;A=0+0AH+CARRY(0)=0BH,C=0 + CPI 00BH + JZ SUII ;TEST "ACI" + CALL CPUER +SUII: SUI 00CH ;A=FFH,C=0 + SUI 00FH ;A=F0H,C=1 + CPI 0F0H + JZ SBII ;TEST "SUI" + CALL CPUER +SBII: SBI 0F1H ;A=F0H-0F1H-CARRY(0)=FFH,C=1 + SBI 00EH ;A=FFH-OEH-CARRY(1)=F0H,C=0 + CPI 0F0H + JZ ANII ;TEST "SBI" + CALL CPUER +ANII: ANI 055H ;A=F0H55H=50H,C=0,P=1,S=0,Z=0 + CPI 050H + JZ ORII ;TEST "ANI" + CALL CPUER +ORII: ORI 03AH ;A=50H3AH=7AH,C=0,P=0,S=0,Z=0 + CPI 07AH + JZ XRII ;TEST "ORI" + CALL CPUER +XRII: XRI 00FH ;A=7AH0FH=75H,C=0,P=0,S=0,Z=0 + CPI 075H + JZ C010 ;TEST "XRI" + CALL CPUER +; +; +; +;TEST CALLS AND RETURNS +; +C010: ANI 000H ;A=0,C=0,P=1,S=0,Z=1 + CC CPUER ;TEST "CC" + CPO CPUER ;TEST "CPO" + CM CPUER ;TEST "CM" + CNZ CPUER ;TEST "CNZ" + CPI 000H + JZ C020 ;A=0,C=0,P=0,S=0,Z=1 + CALL CPUER +C020: SUI 077H ;A=89H,C=1,P=0,S=1,Z=0 + CNC CPUER ;TEST "CNC" + CPE CPUER ;TEST "CPE" + CP CPUER ;TEST "CP" + CZ CPUER ;TEST "CZ" + CPI 089H + JZ C030 ;TEST FOR "CALLS" TAKING BRANCH + CALL CPUER +C030: ANI 0FFH ;SET FLAGS BACK! + CPO CPOI ;TEST "CPO" + CPI 0D9H + JZ MOVI ;TEST "CALL" SEQUENCE SUCCESS + CALL CPUER +CPOI: RPE ;TEST "RPE" + ADI 010H ;A=99H,C=0,P=0,S=1,Z=0 + CPE CPEI ;TEST "CPE" + ADI 002H ;A=D9H,C=0,P=0,S=1,Z=0 + RPO ;TEST "RPO" + CALL CPUER +CPEI: RPO ;TEST "RPO" + ADI 020H ;A=B9H,C=0,P=0,S=1,Z=0 + CM CMI ;TEST "CM" + ADI 004H ;A=D7H,C=0,P=1,S=1,Z=0 + RPE ;TEST "RPE" + CALL CPUER +CMI: RP ;TEST "RP" + ADI 080H ;A=39H,C=1,P=1,S=0,Z=0 + CP TCPI ;TEST "CP" + ADI 080H ;A=D3H,C=0,P=0,S=1,Z=0 + RM ;TEST "RM" + CALL CPUER +TCPI: RM ;TEST "RM" + ADI 040H ;A=79H,C=0,P=0,S=0,Z=0 + CNC CNCI ;TEST "CNC" + ADI 040H ;A=53H,C=0,P=1,S=0,Z=0 + RP ;TEST "RP" + CALL CPUER +CNCI: RC ;TEST "RC" + ADI 08FH ;A=08H,C=1,P=0,S=0,Z=0 + CC CCI ;TEST "CC" + SUI 002H ;A=13H,C=0,P=0,S=0,Z=0 + RNC ;TEST "RNC" + CALL CPUER +CCI: RNC ;TEST "RNC" + ADI 0F7H ;A=FFH,C=0,P=1,S=1,Z=0 + CNZ CNZI ;TEST "CNZ" + ADI 0FEH ;A=15H,C=1,P=0,S=0,Z=0 + RC ;TEST "RC" + CALL CPUER +CNZI: RZ ;TEST "RZ" + ADI 001H ;A=00H,C=1,P=1,S=0,Z=1 + CZ CZI ;TEST "CZ" + ADI 0D0H ;A=17H,C=1,P=1,S=0,Z=0 + RNZ ;TEST "RNZ" + CALL CPUER +CZI: RNZ ;TEST "RNZ" + ADI 047H ;A=47H,C=0,P=1,S=0,Z=0 + CPI 047H ;A=47H,C=0,P=1,S=0,Z=1 + RZ ;TEST "RZ" + CALL CPUER +; +; +; +;TEST "MOV","INR",AND "DCR" INSTRUCTIONS +; +MOVI: MVI A,077H + INR A + MOV B,A + INR B + MOV C,B + DCR C + MOV D,C + MOV E,D + MOV H,E + MOV L,H + MOV A,L ;TEST "MOV" A,L,H,E,D,C,B,A + DCR A + MOV C,A + MOV E,C + MOV L,E + MOV B,L + MOV D,B + MOV H,D + MOV A,H ;TEST "MOV" A,H,D,B,L,E,C,A + MOV D,A + INR D + MOV L,D + MOV C,L + INR C + MOV H,C + MOV B,H + DCR B + MOV E,B + MOV A,E ;TEST "MOV" A,E,B,H,C,L,D,A + MOV E,A + INR E + MOV B,E + MOV H,B + INR H + MOV C,H + MOV L,C + MOV D,L + DCR D + MOV A,D ;TEST "MOV" A,D,L,C,H,B,E,A + MOV H,A + DCR H + MOV D,H + MOV B,D + MOV L,B + INR L + MOV E,L + DCR E + MOV C,E + MOV A,C ;TEST "MOV" A,C,E,L,B,D,H,A + MOV L,A + DCR L + MOV H,L + MOV E,H + MOV D,E + MOV C,D + MOV B,C + MOV A,B + CPI 077H + CNZ CPUER ;TEST "MOV" A,B,C,D,E,H,L,A +; +; +; +;TEST ARITHMETIC AND LOGIC INSTRUCTIONS +; + XRA A + MVI B,001H + MVI C,003H + MVI D,007H + MVI E,00FH + MVI H,01FH + MVI L,03FH + ADD B + ADD C + ADD D + ADD E + ADD H + ADD L + ADD A + CPI 0F0H + CNZ CPUER ;TEST "ADD" B,C,D,E,H,L,A + SUB B + SUB C + SUB D + SUB E + SUB H + SUB L + CPI 078H + CNZ CPUER ;TEST "SUB" B,C,D,E,H,L + SUB A + CNZ CPUER ;TEST "SUB" A + MVI A,080H + ADD A + MVI B,001H + MVI C,002H + MVI D,003H + MVI E,004H + MVI H,005H + MVI L,006H + ADC B + MVI B,080H + ADD B + ADD B + ADC C + ADD B + ADD B + ADC D + ADD B + ADD B + ADC E + ADD B + ADD B + ADC H + ADD B + ADD B + ADC L + ADD B + ADD B + ADC A + CPI 037H + CNZ CPUER ;TEST "ADC" B,C,D,E,H,L,A + MVI A,080H + ADD A + MVI B,001H + SBB B + MVI B,0FFH + ADD B + SBB C + ADD B + SBB D + ADD B + SBB E + ADD B + SBB H + ADD B + SBB L + CPI 0E0H + CNZ CPUER ;TEST "SBB" B,C,D,E,H,L + MVI A,080H + ADD A + SBB A + CPI 0FFH + CNZ CPUER ;TEST "SBB" A + MVI A,0FFH + MVI B,0FEH + MVI C,0FCH + MVI D,0EFH + MVI E,07FH + MVI H,0F4H + MVI L,0BFH + ANA A + ANA C + ANA D + ANA E + ANA H + ANA L + ANA A + CPI 024H + CNZ CPUER ;TEST "ANA" B,C,D,E,H,L,A + XRA A + MVI B,001H + MVI C,002H + MVI D,004H + MVI E,008H + MVI H,010H + MVI L,020H + ORA B + ORA C + ORA D + ORA E + ORA H + ORA L + ORA A + CPI 03FH + CNZ CPUER ;TEST "ORA" B,C,D,E,H,L,A + MVI A,000H + MVI H,08FH + MVI L,04FH + XRA B + XRA C + XRA D + XRA E + XRA H + XRA L + CPI 0CFH + CNZ CPUER ;TEST "XRA" B,C,D,E,H,L + XRA A + CNZ CPUER ;TEST "XRA" A + MVI B,044H + MVI C,045H + MVI D,046H + MVI E,047H + MVI H,(TEMP0/0FFH) ;HIGH BYTE OF TEST MEMORY LOCATION + MVI L,(TEMP0&0FFH) ;LOW BYTE OF TEST MEMORY LOCATION + MOV M,B + MVI B,000H + MOV B,M + MVI A,044H + CMP B + CNZ CPUER ;TEST "MOV" M,B AND B,M + MOV M,D + MVI D,000H + MOV D,M + MVI A,046H + CMP D + CNZ CPUER ;TEST "MOV" M,D AND D,M + MOV M,E + MVI E,000H + MOV E,M + MVI A,047H + CMP E + CNZ CPUER ;TEST "MOV" M,E AND E,M + MOV M,H + MVI H,(TEMP0/0FFH) + MVI L,(TEMP0&0FFH) + MOV H,M + MVI A,(TEMP0/0FFH) + CMP H + CNZ CPUER ;TEST "MOV" M,H AND H,M + MOV M,L + MVI H,(TEMP0/0FFH) + MVI L,(TEMP0&0FFH) + MOV L,M + MVI A,(TEMP0&0FFH) + CMP L + CNZ CPUER ;TEST "MOV" M,L AND L,M + MVI H,(TEMP0/0FFH) + MVI L,(TEMP0&0FFH) + MVI A,032H + MOV M,A + CMP M + CNZ CPUER ;TEST "MOV" M,A + ADD M + CPI 064H + CNZ CPUER ;TEST "ADD" M + XRA A + MOV A,M + CPI 032H + CNZ CPUER ;TEST "MOV" A,M + MVI H,(TEMP0/0FFH) + MVI L,(TEMP0&0FFH) + MOV A,M + SUB M + CNZ CPUER ;TEST "SUB" M + MVI A,080H + ADD A + ADC M + CPI 033H + CNZ CPUER ;TEST "ADC" M + MVI A,080H + ADD A + SBB M + CPI 0CDH + CNZ CPUER ;TEST "SBB" M + ANA M + CNZ CPUER ;TEST "ANA" M + MVI A,025H + ORA M + CPI 037H + CNZ CPUER ;TEST "ORA" M + XRA M + CPI 005H + CNZ CPUER ;TEST "XRA" M + MVI M,055H + INR M + DCR M + ADD M + CPI 05AH + CNZ CPUER ;TEST "INR","DCR",AND "MVI" M + LXI B,12FFH + LXI D,12FFH + LXI H,12FFH + INX B + INX D + INX H + MVI A,013H + CMP B + CNZ CPUER ;TEST "LXI" AND "INX" B + CMP D + CNZ CPUER ;TEST "LXI" AND "INX" D + CMP H + CNZ CPUER ;TEST "LXI" AND "INX" H + MVI A,000H + CMP C + CNZ CPUER ;TEST "LXI" AND "INX" B + CMP E + CNZ CPUER ;TEST "LXI" AND "INX" D + CMP L + CNZ CPUER ;TEST "LXI" AND "INX" H + DCX B + DCX D + DCX H + MVI A,012H + CMP B + CNZ CPUER ;TEST "DCX" B + CMP D + CNZ CPUER ;TEST "DCX" D + CMP H + CNZ CPUER ;TEST "DCX" H + MVI A,0FFH + CMP C + CNZ CPUER ;TEST "DCX" B + CMP E + CNZ CPUER ;TEST "DCX" D + CMP L + CNZ CPUER ;TEST "DCX" H + STA TEMP0 + XRA A + LDA TEMP0 + CPI 0FFH + CNZ CPUER ;TEST "LDA" AND "STA" + LHLD TEMPP + SHLD TEMP0 + LDA TEMPP + MOV B,A + LDA TEMP0 + CMP B + CNZ CPUER ;TEST "LHLD" AND "SHLD" + LDA TEMPP+1 + MOV B,A + LDA TEMP0+1 + CMP B + CNZ CPUER ;TEST "LHLD" AND "SHLD" + MVI A,0AAH + STA TEMP0 + MOV B,H + MOV C,L + XRA A + LDAX B + CPI 0AAH + CNZ CPUER ;TEST "LDAX" B + INR A + STAX B + LDA TEMP0 + CPI 0ABH + CNZ CPUER ;TEST "STAX" B + MVI A,077H + STA TEMP0 + LHLD TEMPP + LXI D,00000H + XCHG + XRA A + LDAX D + CPI 077H + CNZ CPUER ;TEST "LDAX" D AND "XCHG" + XRA A + ADD H + ADD L + CNZ CPUER ;TEST "XCHG" + MVI A,0CCH + STAX D + LDA TEMP0 + CPI 0CCH + STAX D + LDA TEMP0 + CPI 0CCH + CNZ CPUER ;TEST "STAX" D + LXI H,07777H + DAD H + MVI A,0EEH + CMP H + CNZ CPUER ;TEST "DAD" H + CMP L + CNZ CPUER ;TEST "DAD" H + LXI H,05555H + LXI B,0FFFFH + DAD B + MVI A,055H + CNC CPUER ;TEST "DAD" B + CMP H + CNZ CPUER ;TEST "DAD" B + MVI A,054H + CMP L + CNZ CPUER ;TEST "DAD" B + LXI H,0AAAAH + LXI D,03333H + DAD D + MVI A,0DDH + CMP H + CNZ CPUER ;TEST "DAD" D + CMP L + CNZ CPUER ;TEST "DAD" B + STC + CNC CPUER ;TEST "STC" + CMC + CC CPUER ;TEST "CMC + MVI A,0AAH + CMA + CPI 055H + CNZ CPUER ;TEST "CMA" + ORA A ;RE-SET AUXILIARY CARRY + DAA + CPI 055H + CNZ CPUER ;TEST "DAA" + MVI A,088H + ADD A + DAA + CPI 076H + CNZ CPUER ;TEST "DAA" + XRA A + MVI A,0AAH + DAA + CNC CPUER ;TEST "DAA" + CPI 010H + CNZ CPUER ;TEST "DAA" + XRA A + MVI A,09AH + DAA + CNC CPUER ;TEST "DAA" + CNZ CPUER ;TEST "DAA" + STC + MVI A,042H + RLC + CC CPUER ;TEST "RLC" FOR RE-SET CARRY + RLC + CNC CPUER ;TEST "RLC" FOR SET CARRY + CPI 009H + CNZ CPUER ;TEST "RLC" FOR ROTATION + RRC + CNC CPUER ;TEST "RRC" FOR SET CARRY + RRC + CPI 042H + CNZ CPUER ;TEST "RRC" FOR ROTATION + RAL + RAL + CNC CPUER ;TEST "RAL" FOR SET CARRY + CPI 008H + CNZ CPUER ;TEST "RAL" FOR ROTATION + RAR + RAR + CC CPUER ;TEST "RAR" FOR RE-SET CARRY + CPI 002H + CNZ CPUER ;TEST "RAR" FOR ROTATION + LXI B,01234H + LXI D,0AAAAH + LXI H,05555H + XRA A + PUSH B + PUSH D + PUSH H + PUSH PSW + LXI B,00000H + LXI D,00000H + LXI H,00000H + MVI A,0C0H + ADI 0F0H + POP PSW + POP H + POP D + POP B + CC CPUER ;TEST "PUSH PSW" AND "POP PSW" + CNZ CPUER ;TEST "PUSH PSW" AND "POP PSW" + CPO CPUER ;TEST "PUSH PSW" AND "POP PSW" + CM CPUER ;TEST "PUSH PSW" AND "POP PSW" + MVI A,012H + CMP B + CNZ CPUER ;TEST "PUSH B" AND "POP B" + MVI A,034H + CMP C + CNZ CPUER ;TEST "PUSH B" AND "POP B" + MVI A,0AAH + CMP D + CNZ CPUER ;TEST "PUSH D" AND "POP D" + CMP E + CNZ CPUER ;TEST "PUSH D" AND "POP D" + MVI A,055H + CMP H + CNZ CPUER ;TEST "PUSH H" AND "POP H" + CMP L + CNZ CPUER ;TEST "PUSH H" AND "POP H" + LXI H,00000H + DAD SP + SHLD SAVSTK ;SAVE THE "OLD" STACK-POINTER! + LXI SP,TEMP4 + DCX SP + DCX SP + INX SP + DCX SP + MVI A,055H + STA TEMP2 + CMA + STA TEMP3 + POP B + CMP B + CNZ CPUER ;TEST "LXI","DAD","INX",AND "DCX" SP + CMA + CMP C + CNZ CPUER ;TEST "LXI","DAD","INX", AND "DCX" SP + LXI H,TEMP4 + SPHL + LXI H,07733H + DCX SP + DCX SP + XTHL + LDA TEMP3 + CPI 077H + CNZ CPUER ;TEST "SPHL" AND "XTHL" + LDA TEMP2 + CPI 033H + CNZ CPUER ;TEST "SPHL" AND "XTHL" + MVI A,055H + CMP L + CNZ CPUER ;TEST "SPHL" AND "XTHL" + CMA + CMP H + CNZ CPUER ;TEST "SPHL" AND "XTHL" + LHLD SAVSTK ;RESTORE THE "OLD" STACK-POINTER + SPHL + LXI H,CPUOK + PCHL ;TEST "PCHL" +; +; +; +CPUER: LXI H,NGCPU ;OUTPUT "CPU HAS FAILED ERROR EXIT=" TO CONSOLE + CALL MSG + XTHL + MOV A,H + CALL BYTEO ;SHOW ERROR EXIT ADDRESS HIGH BYTE + MOV A,L + CALL BYTEO ;SHOW ERROR EXIT ADDRESS LOW BYTE + JMP WBOOT ;EXIT TO CP/M WARM BOOT +; +; +; +CPUOK: LXI H,OKCPU ;OUTPUT "CPU IS OPERATIONAL" TO CONSOLE + CALL MSG + JMP WBOOT ;EXIT TO CP/M WARM BOOT +; +; +; +TEMPP: DW TEMP0 ;POINTER USED TO TEST "LHLD","SHLD", + ; AND "LDAX" INSTRUCTIONS +; +TEMP0: DS 1 ;TEMPORARY STORAGE FOR CPU TEST MEMORY LOCATIONS +TEMP1: DS 1 ;TEMPORARY STORAGE FOR CPU TEST MEMORY LOCATIONS +TEMP2 DS 1 ;TEMPORARY STORAGE FOR CPU TEST MEMORY LOCATIONS +TEMP3: DS 1 ;TEMPORARY STORAGE FOR CPU TEST MEMORY LOCATIONS +TEMP4: DS 1 ;TEMPORARY STORAGE FOR CPU TEST MEMORY LOCATIONS +SAVSTK: DS 2 ;TEMPORARY STACK-POINTER STORAGE LOCATION +; +; +; +STACK EQU TEMPP+256 ;DE-BUG STACK POINTER STORAGE AREA +; + END + diff --git a/Intel8080/test/roms/TEST.COM b/Intel8080/test/roms/TEST.COM new file mode 100644 index 0000000000000000000000000000000000000000..a02ab70f2a003675354a7b9f1fb2f8ab144dace2 GIT binary patch literal 1793 zcmeH{dr(wW9LMju3kO+&g*C9}a#s<8Y+MFHke88{kq*N$!BFWCO3ixHDvQl-HVCVY zR-4(fO32h@2*UM-R3USDUPiPs$;WYZG^ry{jTZZ?X!7*=nixJ1&Ye9u-Z>elMKur@ z57eO=Uo}#}HLRk_>3SqZNEw~cO16jDCRi$sR=pj5U0EHU(2{Rs#itF{2Le#j1R;BZ)H5}pq2gxMt|hfTK`@~qbj=5 zzh91WXIyy5g=bv&INQp9n5n(aQ!aebg(qCN3)BXGr|b<4_44#5f3^ZF7o^yWL0;kq zfd?gFW|Wu0E&z{7;>0vBiBrH+Qt>IQkc!8E`=rJ*YDF*K4csmLd0eBAXdiHggu2oc zQgwl82U7Uw6yXkKg#fowl3xo2V0x;lU_Ikr1I#B`4~N#BJN3-LbQtjzQq1mtWcY z>T7fp;2Urgu^ya!fzs zNoIMFU@!1S#*Y#2F<^!y%h?RLi{1~Tr;cV_*6UsefHS{HvuEL58UXm1EtY&MAM^_v z4y&6SIm>p@H9#n&jti-^A+=(`VzPi0!^&Wr67G8#St)GW`PbY))c*>H{u$2lVo$yo z%e_i#!i&5(zX_W_VJZ1X0guT@+~6#&@F=Mp0xNiya}bC)L5IXRj{D7X_3Sg=v6BV5 z)XZ~v1VQU`rjk)sAS+AjaG+2qk~rY+EEjE;Rku4XJNqi~^PDXg!bR{N5O+FtK-!TM zc_O>(Q|ME$_7HapSZJ)w`xpb|l9C8WieQmQSgQb3v;=73LZ;0FN=yU?<$+L+I?nBe zf;>N*K0k>#4$h+GIMOPOjh{W)1~xDa$uHt;CrJ+LAaS#Xvo;gQT)B|8d{GOOKELjI)s1Gy4dIW b+~&YKv;}UT1!?!lA8ZTq;?V!sfA7HG-=n?X literal 0 HcmV?d00001 diff --git a/Intel8080/test/stdafx.cpp b/Intel8080/test/stdafx.cpp new file mode 100644 index 0000000..fd4f341 --- /dev/null +++ b/Intel8080/test/stdafx.cpp @@ -0,0 +1 @@ +#include "stdafx.h" diff --git a/Intel8080/test/stdafx.h b/Intel8080/test/stdafx.h new file mode 100644 index 0000000..113a094 --- /dev/null +++ b/Intel8080/test/stdafx.h @@ -0,0 +1,24 @@ +#ifdef _MSC_VER +#pragma once +#endif + +#include +#include +#include +#include +#include + +#include + +#include +#include +#include + +//#include +//#include +// +//#ifdef _MSC_VER +//#pragma comment(lib, "SDL2.lib") +//#pragma comment(lib, "SDL2main.lib") +//#pragma comment(lib, "SDL2_mixer.lib") +//#endif diff --git a/Intel8080/test/test.cpp b/Intel8080/test/test.cpp new file mode 100644 index 0000000..4fa905c --- /dev/null +++ b/Intel8080/test/test.cpp @@ -0,0 +1,19 @@ +#include "stdafx.h" +#include "Game.h" +#include "Configuration.h" + +int main(int, char*[]) { + + Configuration configuration; + +#ifdef _DEBUG + configuration.setDebugMode(true); + configuration.setProfileMode(true); +#endif + + Game game(configuration); + game.initialise(); + game.runLoop(); + + return 0; +} \ No newline at end of file diff --git a/Intel8080/test/test_Intel8080.vcxproj b/Intel8080/test/test_Intel8080.vcxproj new file mode 100644 index 0000000..3d9103d --- /dev/null +++ b/Intel8080/test/test_Intel8080.vcxproj @@ -0,0 +1,177 @@ + + + + + Debug + Win32 + + + Release + Win32 + + + Debug + x64 + + + Release + x64 + + + + 15.0 + {391D3B95-D9DA-47E5-9F61-70483F6BB396} + Win32Proj + test_Intel8080 + + + + Application + true + v140 + Unicode + + + Application + false + v140 + true + Unicode + + + Application + true + v140 + Unicode + + + Application + false + v140 + true + Unicode + + + + + + + + + + + + + + + + + + + + + true + ..\inc;..\..\inc;$(IncludePath) + + + true + ..\inc;..\..\inc;$(IncludePath) + + + false + ..\inc;..\..\inc;$(IncludePath) + + + false + ..\inc;..\..\inc;$(IncludePath) + + + + Use + Level3 + Disabled + WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) + + + Console + + + + + Use + Level3 + Disabled + _DEBUG;_CONSOLE;%(PreprocessorDefinitions) + + + Console + + + + + Level3 + Use + MaxSpeed + true + true + WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) + AnySuitable + Speed + false + AdvancedVectorExtensions + + + Console + true + true + + + + + Level3 + Use + MaxSpeed + true + true + NDEBUG;_CONSOLE;%(PreprocessorDefinitions) + AnySuitable + Speed + false + AdvancedVectorExtensions + + + Console + true + true + + + + + + + + + + + + + + Create + Create + Create + Create + + + + + + {a9c24bd9-0cb4-4c84-b09b-46b815f9da47} + + + {93bdc8d8-9f0d-44ed-94fb-1be6ac4b6bd6} + + + + + + \ No newline at end of file diff --git a/Intel8080/test/test_Intel8080.vcxproj.filters b/Intel8080/test/test_Intel8080.vcxproj.filters new file mode 100644 index 0000000..191f058 --- /dev/null +++ b/Intel8080/test/test_Intel8080.vcxproj.filters @@ -0,0 +1,44 @@ + + + + + {4FC737F1-C7A5-4376-A066-2A32D752A2FF} + cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx + + + {93995380-89BD-4b04-88EB-625FBE52EBFB} + h;hh;hpp;hxx;hm;inl;inc;xsd + + + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + \ No newline at end of file