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Add some more 6809 documentation.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
This commit is contained in:
Adrian Conlon
parent
d7763d8215
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479
MC6809/documentation/6809cyc.txt
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479
MC6809/documentation/6809cyc.txt
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@ -0,0 +1,479 @@
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MC6809 Cycle-By-Cycle Performance
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=================================
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This document is based on Arto Salmi's work.
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(salmiarto@gmail.com, http://koti.mbnet.fi/~atjs/mc6809/Information/6809cyc.txt). Additional information by ALeX Kazik.
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This information is taken from Motorola Semiconductor Technical Data: MC6809E 8-bit microprocessing unit
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http://www.funet.fi/pub/cbm/documents/chipdata/6809/index.html (6809-21.gif - 6809-25.gif).
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Interrupt information is taken from HD6809E, HD68A09E, HD68B09E datasheet.
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Please mail me if you find errors, something is missing etc... (salmiarto@gmail.com)
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V1.0 2000-10-19 atjs first version (there must be errors)
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V1.1 2000-11-03 atjs tabs -> spaces, clean up, now normal text file (no MS-DOS), added LEA, stack writes
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and interrupts.
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V1.2 2000-11-30 atjs fixed LBRA, LBSR cycles
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V1.3 2015-10-21 ALeX restructured the document
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added [,R]
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added reset (soft- & hardware) characteristics
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Format
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------
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- Cycle (1, 2, ...)
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- Read/Write (R/W)
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- Data Bus
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- Address Bus
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Address Bus
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-----------
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$xxxx: fixed Address
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PC: Program Counter
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SP: Hardware Stack Pointer (aka S)
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US: User Stack Pointer (aka U)
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EA: Effective Address
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IX: Indexed Indirect Address
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Z: Tri-Stated bus
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########################################################
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Immediate, Direct, Extended and Indexed Addressing Modes
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########################################################
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ASL, ASR, CLR, COM, DEC, INC, LSL, LSR, NEG, ROL, ROR
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----------------------------|-----------------------------|-----------------------------|----------------------------
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| Direct Addressing Mode | Extended Addressing Mode | Indexed Addressing Mode
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----------------------------|-----------------------------|-----------------------------|----------------------------
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| 1 R Opcode Fetch PC | 1 R Opcode Fetch PC | 1 R Opcode Fetch PC
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| 2 R Address Low PC+1 | 2 R Address High PC+1 | 2 R Post Byte PC+1
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| 3 R Don't Care $ffff | 3 R Address Low PC+2 | Based on Index Mode
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| 4 R Data EA | 4 R Don't Care $ffff | ? R Data EA
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| 5 R Don't Care $ffff | 5 R Data EA | ? R Don't Care $ffff
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| 6 W Data EA | 6 R Don't Care $ffff | ? W Data EA
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| | 7 W Data EA |
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TST
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----------------------------|-----------------------------|-----------------------------|----------------------------
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| Direct Addressing Mode | Extended Addressing Mode | Indexed Addressing Mode
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----------------------------|-----------------------------|-----------------------------|----------------------------
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| 1 R Opcode Fetch PC | 1 R Opcode Fetch PC | 1 R Opcode Fetch PC
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| 2 R Address Low PC+1 | 2 R Address High PC+1 | 2 R Post Byte PC+1
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| 3 R Don't Care $ffff | 3 R Address Low PC+2 | Based on Index Mode
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| 4 R Data EA | 4 R Don't Care $ffff | ? R Data EA
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| 5 R Don't Care $ffff | 5 R Data EA | ? R Don't Care $ffff
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| 6 R Don't Care $ffff | 6 R Don't Care $ffff | ? R Don't Care $ffff
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| | 7 R Don't Care $ffff |
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ADCA, ADCB, ADDA, ADDB, ANDA, ANDB, BITA, BITB, CMPA, CMPB, EORA, EORB, LDA, LDB, ORA, ORB, SBCA, SBCB, SUBA, SUBB
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----------------------------|-----------------------------|-----------------------------|----------------------------
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Immediate Addressing Mode | Direct Addressing Mode | Extended Addressing Mode | Indexed Addressing Mode
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----------------------------|-----------------------------|-----------------------------|----------------------------
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1 R Opcode Fetch PC | 1 R Opcode Fetch PC | 1 R Opcode Fetch PC | 1 R Opcode Fetch PC
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2 R Data PC+1 | 2 R Address Low PC+1 | 2 R Address High PC+1 | 2 R Post Byte PC+1
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| 3 R Don't Care $ffff | 3 R Address Low PC+2 | Based on Index Mode
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| 4 R Data EA | 4 R Don't Care $ffff | ? R Data EA
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| | 5 R Data EA |
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ANDCC, ORCC
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----------------------------|-----------------------------|-----------------------------|----------------------------
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Immediate Addressing Mode | | |
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----------------------------|-----------------------------|-----------------------------|----------------------------
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1 R Opcode Fetch PC | | |
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2 R Data PC+1 | | |
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3 R Don't Care $ffff | | |
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STA, STB
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----------------------------|-----------------------------|-----------------------------|----------------------------
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| Direct Addressing Mode | Extended Addressing Mode | Indexed Addressing Mode
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----------------------------|-----------------------------|-----------------------------|----------------------------
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| 1 R Opcode Fetch PC | 1 R Opcode Fetch PC | 1 R Opcode Fetch PC
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| 2 R Address Low PC+1 | 2 R Address High PC+1 | 2 R Post Byte PC+1
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| 3 R Don't Care $ffff | 3 R Address Low PC+2 | Based on Index Mode
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| 4 W Register EA | 4 R Don't Care $ffff | ? W Register EA
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| | 5 W Register EA |
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ADDD, CMPX, SUBD
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----------------------------|-----------------------------|-----------------------------|----------------------------
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Immediate Addressing Mode | Direct Addressing Mode | Extended Addressing Mode | Indexed Addressing Mode
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----------------------------|-----------------------------|-----------------------------|----------------------------
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1 R Opcode Fetch PC | 1 R Opcode Fetch PC | 1 R Opcode Fetch PC | 1 R Opcode Fetch PC
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2 R Data High PC+1 | 2 R Address Low PC+1 | 2 R Address High PC+1 | 2 R Post Byte PC+1
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3 R Data Low PC+2 | 3 R Don't Care $ffff | 3 R Address Low PC+2 | Based on Index Mode
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4 R Don't Care $ffff | 4 R Data High EA | 4 R Don't Care $ffff | ? R Data High EA
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| 5 R Data Low EA+1 | 5 R Data High EA | ? R Data Low EA+1
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| 6 R Don't Care $ffff | 6 R Data Low EA+1 | ? R Don't Care $ffff
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| | 7 R Don't Care $ffff |
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CMPY, CMPD, CMPS, CMPU
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----------------------------|-----------------------------|-----------------------------|----------------------------
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Immediate Addressing Mode | Direct Addressing Mode | Extended Addressing Mode | Indexed Addressing Mode
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----------------------------|-----------------------------|-----------------------------|----------------------------
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1 R Opcode Fetch PC | 1 R Opcode Fetch PC | 1 R Opcode Fetch PC | 1 R Opcode Fetch PC
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2 R Opcode 2nd Byte PC+1 | 2 R Opcode 2nd Byte PC+1 | 2 R Opcode 2nd Byte PC+1 | 2 R Opcode 2nd Byte PC+1
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3 R Data High PC+2 | 3 R Address Low PC+2 | 3 R Address High PC+2 | 3 R Post Byte PC+2
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4 R Data Low PC+3 | 4 R Don't Care $ffff | 4 R Address Low PC+3 | Based on Index Mode; see Note
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5 R Don't Care $ffff | 5 R Data High EA | 5 R Don't Care $ffff | ? R Data High EA
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| 6 R Data Low EA+1 | 6 R Data High EA | ? R Data Low EA+1
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| 7 R Don't Care $ffff | 7 R Data Low EA+1 | ? R Don't Care $ffff
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| | 8 R Don't Care $ffff |
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LDD, LDU, LDX
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----------------------------|-----------------------------|-----------------------------|----------------------------
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Immediate Addressing Mode | Direct Addressing Mode | Extended Addressing Mode | Indexed Addressing Mode
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----------------------------|-----------------------------|-----------------------------|----------------------------
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1 R Opcode Fetch PC | 1 R Opcode Fetch PC | 1 R Opcode Fetch PC | 1 R Opcode Fetch PC
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2 R Register High PC+1 | 2 R Address Low PC+1 | 2 R Address High PC+1 | 2 R Post Byte PC+1
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3 R Register Low PC+2 | 3 R Don't Care $ffff | 3 R Address Low PC+2 | Based on Index Mode
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| 4 R Register High EA | 4 R Don't Care $ffff | ? R Register High EA
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| 5 R Register Low EA+1 | 5 R Register High EA | ? R Register Low EA+1
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| | 6 R Register Low EA+1 |
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LDS, LDY
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----------------------------|-----------------------------|-----------------------------|----------------------------
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Immediate Addressing Mode | Direct Addressing Mode | Extended Addressing Mode | Indexed Addressing Mode
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----------------------------|-----------------------------|-----------------------------|----------------------------
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1 R Opcode Fetch PC | 1 R Opcode Fetch PC | 1 R Opcode Fetch PC | 1 R Opcode Fetch PC
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2 R Opcode 2nd Byte PC+1 | 2 R Opcode 2nd Byte PC+1 | 2 R Opcode 2nd Byte PC+1 | 2 R Opcode 2nd Byte PC+1
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3 R Register High PC+2 | 3 R Address Low PC+2 | 3 R Address High PC+2 | 3 R Post Byte PC+2
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4 R Register Low PC+3 | 4 R Don't Care $ffff | 4 R Address Low PC+3 | Based on Index Mode; see Note
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| 5 R Register High EA | 5 R Don't Care $ffff | ? R Register High EA
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| 6 R Register Low EA+1 | 6 R Register High EA | ? R Register Low EA+1
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| | 7 R Register Low EA+1 |
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STD, STU, STX
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----------------------------|-----------------------------|-----------------------------|----------------------------
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| Direct Addressing Mode | Extended Addressing Mode | Indexed Addressing Mode
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----------------------------|-----------------------------|-----------------------------|----------------------------
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| 1 R Opcode Fetch PC | 1 R Opcode Fetch PC | 1 R Opcode Fetch PC
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| 2 R Address Low PC+1 | 2 R Address High PC+1 | 2 R Post Byte PC+1
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| 3 R Don't Care $ffff | 3 R Address Low PC+2 | Based on Index Mode
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| 4 W Register High EA | 4 R Don't Care $ffff | ? W Register High EA
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| 5 W Register Low EA+1 | 5 W Register High EA | ? W Register Low EA+1
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| | 6 W Register Low EA+1 |
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STS, STY
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----------------------------|-----------------------------|-----------------------------|----------------------------
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| Direct Addressing Mode | Extended Addressing Mode | Indexed Addressing Mode
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----------------------------|-----------------------------|-----------------------------|----------------------------
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| 1 R Opcode Fetch PC | 1 R Opcode Fetch PC | 1 R Opcode Fetch PC
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| 2 R Opcode 2nd Byte PC+1 | 2 R Opcode 2nd Byte PC+1 | 2 R Opcode 2nd Byte PC+1
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| 3 R Address Low PC+2 | 3 R Address High PC+2 | 3 R Post Byte PC+2
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| 4 R Don't Care $ffff | 4 R Address Low PC+3 | Based on Index Mode; see Note
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| 5 W Register High EA | 5 R Don't Care $ffff | ? W Register High EA
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| 6 W Register Low EA+1 | 6 W Register High EA | ? W Register Low EA+1
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| | 7 W Register Low EA+1 |
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LEAS, LEAU, LEAX, LEAY
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----------------------------|-----------------------------|-----------------------------|----------------------------
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| | | Indexed Addressing Mode
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----------------------------|-----------------------------|-----------------------------|----------------------------
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| | | 1 R Opcode Fetch PC
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| | | 2 R Post Byte PC+1
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| | | Based on Index Mode
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| | | ? R Don't Care $ffff
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JMP
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----------------------------|-----------------------------|-----------------------------|----------------------------
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| Direct Addressing Mode | Extended Addressing Mode | Indexed Addressing Mode
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----------------------------|-----------------------------|-----------------------------|----------------------------
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| 1 R Opcode Fetch PC | 1 R Opcode Fetch PC | 1 R Opcode Fetch PC
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| 2 R Address Low PC+1 | 2 R Address High PC+1 | 2 R Post Byte PC+1
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| 3 R Don't Care $ffff | 3 R Address Low PC+2 | Based on Index Mode
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| | 4 R Don't Care $ffff |
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JSR
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----------------------------|-----------------------------|-----------------------------|----------------------------
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| Direct Addressing Mode | Extended Addressing Mode | Indexed Addressing Mode
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----------------------------|-----------------------------|-----------------------------|----------------------------
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| 1 R Opcode Fetch PC | 1 R Opcode Fetch PC | 1 R Opcode Fetch PC
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| 2 R Address Low PC+1 | 2 R Address High PC+1 | 2 R Post Byte PC+1
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| 3 R Don't Care $ffff | 3 R Address Low PC+2 | Based on Index Mode
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| 4 R Don't Care EA | 4 R Don't Care $ffff | ? R Don't Care EA
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| 5 R Don't Care $ffff | 5 R Don't Care EA | ? R Don't Care $ffff
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| 6 W PC Low SP-1 | 6 R Don't Care $ffff | ? W PC Low SP-1
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| 7 W PC High SP-2 | 7 W PC Low SP-1 | ? W PC High SP-2
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| | 8 W PC High SP-2 |
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#########################
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Relative Addressing Modes
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#########################
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BCC, BCS, BEQ, BGE, BGT, BHI, BHS, BLE, BLO, BLS, BLT, BMI, BNE, BPL, BRA, BRN, BVC, BVS
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---------------------------
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1 R Opcode Fetch PC
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2 R Offset PC+1
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3 R Don't Care $ffff
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LBCC, LBCS, LBEQ, LBGE, LBGT, LBHI, LBHS, LBLE, LBLO, LBLS, LBLT, LBMI, LBNE, LBPL, LBRN, LBVC, LBVS
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---------------------------------------------------------------------------------------
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1 R Opcode Fetch PC | |
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2 R Opcode 2nd Byte PC+1 | |
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3 R Offset High PC+2 | |
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4 R Offset Low PC+3 | |
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5 R Don't Care $ffff | |
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Depends on branching | IF Branch is not taken | IF Branch is taken
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| | 6 R Don't Care $ffff
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BSR | LBSR | LBRA
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----------------------------|-----------------------------|----------------------------
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1 R Opcode Fetch PC | 1 R Opcode Fetch PC | 1 R Opcode Fetch PC
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2 R Offset PC+1 | 2 R Offset High PC+1 | 2 R Offset High PC+1
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3 R Don't Care $ffff | 3 R Offset Low PC+2 | 3 R Offset Low PC+2
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4 R Don't Care EA | 4 R Don't Care $ffff | 4 R Don't Care $ffff
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5 R Don't Care $ffff | 5 R Don't Care $ffff | 5 R Don't Care $ffff
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6 W Return Addr Low SP-1 | 6 R Don't Care EA |
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7 W Return Addr High SP-2 | 7 R Don't Care $ffff |
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| 8 W Return Addr Low SP-1 |
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| 9 W Return Addr High SP-2 |
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#########################
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Inherent Addressing Modes
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#########################
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ASLA, ASRA, CLRA, COMA, DECA, INCA, LSLA, LSRA, NEGA, ROLA, RORA, TSTA
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ASLB, ASRB, CLRB, COMB, DECB, INCB, LSLB, LSRB, NEGB, ROLB, RORB, TSTB
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DAA, NOP, SEX
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---------------------------
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1 R Opcode Fetch PC
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2 R Don't Care PC+1
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ABX | MUL
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----------------------------|----------------------------
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1 R Opcode Fetch PC | 1 R Opcode Fetch PC
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2 R Don't Care PC+1 | 2 R Don't Care PC+1
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3 R Don't Care $ffff | 3 R Don't Care $ffff
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| 4 R Don't Care $ffff
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| 5 R Don't Care $ffff
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| 6 R Don't Care $ffff
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| 7 R Don't Care $ffff
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| 8 R Don't Care $ffff
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| 9 R Don't Care $ffff
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| 10 R Don't Care $ffff
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| 11 R Don't Care $ffff
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EXG | TFR
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----------------------------|----------------------------
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1 R Opcode Fetch PC | 1 R Opcode Fetch PC
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2 R Post Byte PC+1 | 2 R Post Byte PC+1
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3 R Don't Care $ffff | 3 R Don't Care $ffff
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4 R Don't Care $ffff | 4 R Don't Care $ffff
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5 R Don't Care $ffff | 5 R Don't Care $ffff
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6 R Don't Care $ffff | 6 R Don't Care $ffff
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7 R Don't Care $ffff |
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8 R Don't Care $ffff |
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RTS | RTI
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----------------------------|----------------------------------------------------------------------------------------
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1 R Opcode Fetch PC | 1 R Opcode Fetch PC | |
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2 R Don't Care PC+1 | 2 R Don't Care PC+1 | |
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3 R PC High SP | 3 R CCR SP | |
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4 R PC Low SP+1 | Depends on E, see right | IF E=0 | IF E=1
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5 R Don't Care $ffff | | 4 R PC High SP+1 | 4 R A Register SP+1
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| | 5 R PC Low SP+2 | 5 R B Register SP+2
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| | 6 R Don't Care $ffff | 6 R DP Register SP+3
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| | | 7 R X Register High SP+4
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| | | 8 R X Register Low SP+5
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| | | 9 R Y Register High SP+6
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| | | 10 R Y Register Low SP+7
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| | | 11 R User Stack High SP+8
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| | | 12 R User Stack Low SP+9
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| | | 13 R PC High SP+10
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| | | 14 R PC Low SP+11
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| | | 15 R Don't Care $ffff
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PSHS | PSHU | PULS | PULU
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----------------------------|-----------------------------|-----------------------------|----------------------------
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1 R Opcode Fetch PC | 1 R Opcode Fetch PC | 1 R Opcode Fetch PC | 1 R Opcode Fetch PC
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2 R Post Byte PC+1 | 2 R Post Byte PC+1 | 2 R Post Byte PC+1 | 2 R Post Byte PC+1
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3 R Don't Care $ffff | 3 R Don't Care $ffff | 3 R Don't Care $ffff | 3 R Don't Care $ffff
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4 R Don't Care $ffff | 4 R Don't Care $ffff | 4 R Don't Care $ffff | 4 R Don't Care $ffff
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5 R Don't Care SP | 5 R Don't Care US | PULL 0-12 Bytes (0-8 Regs) | PULL 0-12 Bytes (0-8 Regs)
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PUSH 0-12 Bytes (0-8 Regs) | PUSH 0-12 Bytes (0-8 Regs) | ? R Register ? SP | ? R Register ? US
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? W Register ? SP-1 | ? W Register ? US-1 | ? R Register ? SP+1 | ? R Register ? US+1
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? W Register ? SP-2 | ? W Register ? US-2 | ? R Register ? SP+2 | ? R Register ? US+2
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? W Register ? SP-3 | ? W Register ? US-3 | ? R ... | ? R ...
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? W ... | ? W ... | END LOOP | END LOOP
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END LOOP | END LOOP | ? R Don't Care SP+X | ? R Don't Care US+X
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SWI | SWI2 | SWI3 | RESET (undocumented Op $3e)
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----------------------------|-----------------------------|-----------------------------|----------------------------
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1 R Opcode Fetch PC | 1 R Opcode Fetch PC | 1 R Opcode Fetch PC | 1 R Opcode Fetch PC
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2 R Don't Care PC+1 | 2 R Opcode 2nd Byte PC+1 | 2 R Opcode 2nd Byte PC+1 | 2 R Don't Care PC+1
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3 R Don't Care $ffff | 3 R Don't Care PC+2 | 3 R Don't Care PC+2 | 3 R Don't Care $ffff
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4 W PC Low SP-1 | 4 R Don't Care $ffff | 4 R Don't Care $ffff | 4 W PC Low SP-1
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5 W PC High SP-2 | 5 W PC Low SP-1 | 5 W PC Low SP-1 | 5 W PC High SP-2
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6 W User Stack Low SP-3 | 6 W PC High SP-2 | 6 W PC High SP-2 | 6 W User Stack Low SP-3
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7 W User Stack High SP-4 | 7 W User Stack Low SP-3 | 7 W User Stack Low SP-3 | 7 W User Stack High SP-4
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8 W Y Register Low SP-5 | 8 W User Stack High SP-4 | 8 W User Stack High SP-4 | 8 W Y Register Low SP-5
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9 W Y Register High SP-6 | 9 W Y Register Low SP-5 | 9 W Y Register Low SP-5 | 9 W Y Register High SP-6
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10 W X Register Low SP-7 | 10 W Y Register High SP-6 | 10 W Y Register High SP-6 | 10 W X Register Low SP-7
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11 W X Register High SP-8 | 11 W X Register Low SP-7 | 11 W X Register Low SP-7 | 11 W X Register High SP-8
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12 W DP Register SP-9 | 12 W X Register High SP-8 | 12 W X Register High SP-8 | 12 W DP Register SP-9
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13 W B Register SP-10 | 13 W DP Register SP-9 | 13 W DP Register SP-9 | 13 W B Register SP-10
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14 W A Register SP-11 | 14 W B Register SP-10 | 14 W B Register SP-10 | 14 W A Register SP-11
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15 W CC Register SP-12 | 15 W A Register SP-11 | 15 W A Register SP-11 | 15 W CC Register SP-12
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16 R Don't Care $ffff | 16 W CC Register SP-12 | 16 W CC Register SP-12 | 16 R Don't Care $ffff
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17 R Int. Vector High $fffa | 17 R Don't Care $ffff | 17 R Don't Care $ffff | 17 R Int. Vector High $fffe
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18 R Int. Vector Low $fffb | 18 R Int. Vector High $fff4 | 18 R Int. Vector High $fff2 | 18 R Int. Vector Low $ffff
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19 R Don't Care $ffff | 19 R Int. Vector Low $fff5 | 19 R Int. Vector Low $fff3 | 19 R Don't Care $ffff
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| 20 R Don't Care $ffff | 20 R Don't Care $ffff |
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CWAI | SYNC
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----------------------------|----------------------------
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1 R Opcode Fetch PC | 1 R Opcode Fetch PC
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2 R CC Mask PC+1 | 2 R Don't Care PC+1
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3 R Don't Care PC+2 | DO
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4 R Don't Care $ffff | ? R Don't Care Z
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5 W PC Low SP-1 | WHILE Interrupt Not Present
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6 W PC High SP-2 | ? R Don't Care Z
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7 W User Stack Low SP-3 |
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8 W User Stack High SP-4 |
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9 W Y Register Low SP-5 |
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10 W Y Register High SP-6 |
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11 W X Register Low SP-7 |
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12 W X Register High SP-8 |
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13 W DP Register SP-9 |
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14 W B Register SP-10 |
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15 W A Register SP-11 |
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16 W CC Register SP-12 |
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DO |
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? R Don't Care $ffff |
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WHILE Interrupt Not Present |
|
||||
? R Int. Vector High $fffx |
|
||||
? R Int. Vector Low $fffy |
|
||||
? R Don't Care $ffff |
|
||||
|
||||
|
||||
###################
|
||||
Hardware Interrupts
|
||||
###################
|
||||
|
||||
FIRQ | IRQ | NMI | RESET
|
||||
----------------------------|-----------------------------|-----------------------------|----------------------------
|
||||
1 R ? PC | 1 R ? PC | 1 R ? PC | DO
|
||||
2 R ? PC | 2 R ? PC | 2 R ? PC | ? R Don't Care $fffe
|
||||
3 R Don't Care $ffff | 3 R Don't Care $ffff | 3 R Don't Care $ffff | WHILE Reset Line is Low
|
||||
4 W PC Low SP-1 | 4 W PC Low SP-1 | 4 W PC Low SP-1 | ? R Don't Care $fffe
|
||||
5 W PC High SP-2 | 5 W PC High SP-2 | 5 W PC High SP-2 | ? R Don't Care $fffe
|
||||
6 W CC Register SP-3 | 6 W User Stack Low SP-3 | 6 W User Stack Low SP-3 | ? R Don't Care $fffe
|
||||
7 R Don't Care $ffff | 7 W User Stack High SP-4 | 7 W User Stack High SP-4 | ? R Int. Vector High $fffe
|
||||
8 R Int. Vector High $fff6 | 8 W Y Register Low SP-5 | 8 W Y Register Low SP-5 | ? R Int. Vector Low $ffff
|
||||
9 R Int. Vector Low $fff7 | 9 W Y Register High SP-6 | 9 W Y Register High SP-6 | ? R Don't Care $ffff
|
||||
10 R Don't Care $ffff | 10 W X Register Low SP-7 | 10 W X Register Low SP-7 |
|
||||
| 11 W X Register High SP-8 | 11 W X Register High SP-8 |
|
||||
| 12 W DP Register SP-9 | 12 W DP Register SP-9 |
|
||||
| 13 W B Register SP-10 | 13 W B Register SP-10 |
|
||||
| 14 W A Register SP-11 | 14 W A Register SP-11 |
|
||||
| 15 W CC Register SP-12 | 15 W CC Register SP-12 |
|
||||
| 16 R Don't Care $ffff | 16 R Don't Care $ffff |
|
||||
| 17 R Int. Vector Low $fff8 | 17 R Int. Vector Low $fffc |
|
||||
| 18 R Int. Vector High $fff9 | 18 R Int. Vector High $fffd |
|
||||
| 19 R Don't Care $ffff | 19 R Don't Care $ffff |
|
||||
|
||||
|
||||
################################
|
||||
Index Addressing Mode variations
|
||||
################################
|
||||
|
||||
NOTE: For opcodes $10xx and $11xx cycle and PC
|
||||
has to be increased by 1 to get correct values.
|
||||
|
||||
,R | [,R]
|
||||
----------------------------|----------------------------
|
||||
3 R Don't Care PC+2 | 3 R Don't Care PC+2
|
||||
| 4 R Indirect High IX
|
||||
| 5 R Indirect Low IX+1
|
||||
| 6 R Don't Care $ffff
|
||||
|
||||
5n,R |
|
||||
----------------------------|----------------------------
|
||||
3 R Don't Care PC+2 |
|
||||
4 R Don't Care $ffff |
|
||||
|
||||
8n,R | [8n,R]
|
||||
----------------------------|----------------------------
|
||||
3 R Offset PC+2 | 3 R Offset PC+2
|
||||
4 R Don't Care $ffff | 4 R Don't Care $ffff
|
||||
| 5 R Indirect High IX
|
||||
| 6 R Indirect Low IX+1
|
||||
| 7 R Don't Care $ffff
|
||||
|
||||
16n,R | [16n,R]
|
||||
----------------------------|----------------------------
|
||||
3 R Offset High PC+2 | 3 R Offset High PC+2
|
||||
4 R Offset Low PC+3 | 4 R Offset Low PC+3
|
||||
5 R Don't Care PC+4 | 5 R Don't Care PC+4
|
||||
6 R Don't Care $ffff | 6 R Don't Care $ffff
|
||||
7 R Don't Care $ffff | 7 R Don't Care $ffff
|
||||
| 8 R Indirect High IX
|
||||
| 9 R Indirect Low IX+1
|
||||
| 10 R Don't Care $ffff
|
||||
|
||||
A,R / B,R | [A,R] / [B,R]
|
||||
----------------------------|----------------------------
|
||||
3 R Don't Care PC+2 | 3 R Don't Care PC+2
|
||||
4 R Don't Care $ffff | 4 R Don't Care $ffff
|
||||
| 5 R Indirect High IX
|
||||
| 6 R Indirect Low IX+1
|
||||
| 7 R Don't Care $ffff
|
||||
|
||||
D,R | [D,R]
|
||||
----------------------------|----------------------------
|
||||
3 R Don't Care PC+2 | 3 R Don't Care PC+2
|
||||
4 R Don't Care PC+3 | 4 R Don't Care PC+3
|
||||
5 R Don't Care PC+4 | 5 R Don't Care PC+4
|
||||
6 R Don't Care $ffff | 6 R Don't Care $ffff
|
||||
7 R Don't Care $ffff | 7 R Don't Care $ffff
|
||||
| 8 R Indirect High IX
|
||||
| 9 R Indirect Low IX+1
|
||||
| 10 R Don't Care $ffff
|
||||
|
||||
,R+ / ,-R |
|
||||
----------------------------|----------------------------
|
||||
3 R Don't Care PC+2 |
|
||||
4 R Don't Care $ffff |
|
||||
5 R Don't Care $ffff |
|
||||
|
||||
,R++ / ,--R | [,R++] / [,--R]
|
||||
----------------------------|----------------------------
|
||||
3 R Don't Care PC+2 | 3 R Don't Care PC+2
|
||||
4 R Don't Care $ffff | 4 R Don't Care $ffff
|
||||
5 R Don't Care $ffff | 5 R Don't Care $ffff
|
||||
6 R Don't Care $ffff | 6 R Don't Care $ffff
|
||||
| 7 R Indirect High IX
|
||||
| 8 R Indirect Low IX+1
|
||||
| 9 R Don't Care $ffff
|
||||
|
||||
8n,PC | [8n,PC]
|
||||
----------------------------|----------------------------
|
||||
3 R Offset PC+2 | 3 R Offset PC+2
|
||||
4 R Don't Care $ffff | 4 R Don't Care $ffff
|
||||
| 5 R Indirect High IX
|
||||
| 6 R Indirect Low IX+1
|
||||
| 7 R Don't Care $ffff
|
||||
|
||||
16n,PC | [16n,PC]
|
||||
----------------------------|----------------------------
|
||||
3 R Offset High PC+2 | 3 R Offset High PC+2
|
||||
4 R Offset Low PC+3 | 4 R Offset Low PC+3
|
||||
5 R Don't Care PC+4 | 5 R Don't Care PC+4
|
||||
6 R Don't Care $ffff | 6 R Don't Care $ffff
|
||||
7 R Don't Care $ffff | 7 R Don't Care $ffff
|
||||
8 R Don't Care $ffff | 8 R Don't Care $ffff
|
||||
| 9 R Indirect High IX
|
||||
| 10 R Indirect Low IX+1
|
||||
| 11 R Don't Care $ffff
|
||||
|
||||
| [Addr]
|
||||
----------------------------|----------------------------
|
||||
| 3 R Address High PC+2
|
||||
| 4 R Address Low PC+3
|
||||
| 5 R Don't Care PC+4
|
||||
| 6 R Indirect High IX
|
||||
| 7 R Indirect Low IX+1
|
||||
| 8 R Don't Care $ffff
|
||||
|
||||
Loading…
Reference in New Issue
Block a user