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More address mode simplifications

This commit is contained in:
Adrian Conlon 2024-03-06 21:30:27 +00:00
parent ee9d2bd02b
commit 7bfadb05b4
2 changed files with 37 additions and 67 deletions
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9
M6502/inc/mos6502.h
View File

@ -267,13 +267,8 @@ namespace EightBit {
// Undocumented compound instructions
void anc(uint8_t value) noexcept;
void asr(uint8_t value) noexcept;
void axs(uint8_t value) noexcept;
void rla(uint8_t value) noexcept;
void rra(uint8_t value) noexcept;
void slo(uint8_t value) noexcept;
void sre(uint8_t value) noexcept;
void anc() noexcept;
void axs() noexcept;
void jam() noexcept;
// Undocumented complicated mode implementations

95
M6502/src/mos6502.cpp
View File

@ -131,113 +131,113 @@ int EightBit::MOS6502::execute() noexcept {
case 0x00: swallow_fetch(); interrupt(); break; // BRK (implied)
case 0x01: AM_IndexedIndirectX(); orr(); break; // ORA (indexed indirect X)
case 0x02: jam(); break; // *JAM
case 0x03: slo(AM_IndexedIndirectX()); break; // *SLO (indexed indirect X)
case 0x03: RMW(Address_IndexedIndirectX, asl); orr(); break; // *SLO (indexed indirect X)
case 0x04: AM_ZeroPage(); break; // *NOP (zero page)
case 0x05: AM_ZeroPage(); orr(); break; // ORA (zero page)
case 0x06: RMW(Address_ZeroPage, asl); break; // ASL (zero page)
case 0x07: slo(AM_ZeroPage()); break; // *SLO (zero page)
case 0x07: RMW(Address_ZeroPage, asl); orr(); break; // *SLO (zero page)
case 0x08: swallow(); php(); break; // PHP (implied)
case 0x09: AM_Immediate(); orr(); break; // ORA (immediate)
case 0x0a: swallow(); A() = asl(A()); break; // ASL A (implied)
case 0x0b: anc(AM_Immediate()); break; // *ANC (immediate)
case 0x0b: AM_Immediate(); anc(); break; // *ANC (immediate)
case 0x0c: { auto ignored = Address_Absolute(); } break; // *NOP (absolute)
case 0x0d: AM_Absolute(); orr(); break; // ORA (absolute)
case 0x0e: RMW(Address_Absolute, asl); break; // ASL (absolute)
case 0x0f: slo(AM_Absolute()); break; // *SLO (absolute)
case 0x0f: RMW(Address_Absolute, asl); orr(); break; // *SLO (absolute)
case 0x10: branch(negative() == 0); break; // BPL (relative)
case 0x11: AM_IndirectIndexedY(); orr(); break; // ORA (indirect indexed Y)
case 0x12: jam(); break; // *JAM
case 0x13: fixup(Address_IndirectIndexedY()); slo(memoryRead()); break; // *SLO (indirect indexed Y)
case 0x13: FIXUP_RMW(Address_IndirectIndexedY, asl); orr(); break; // *SLO (indirect indexed Y)
case 0x14: AM_ZeroPageX(); break; // *NOP (zero page, X)
case 0x15: AM_ZeroPageX(); orr(); break; // ORA (zero page, X)
case 0x16: RMW(Address_ZeroPageX, asl); break; // ASL (zero page, X)
case 0x17: slo(AM_ZeroPageX()); break; // *SLO (zero page, X)
case 0x17: RMW(Address_ZeroPageX, asl); orr(); break; // *SLO (zero page, X)
case 0x18: swallow(); reset_flag(CF); break; // CLC (implied)
case 0x19: AM_AbsoluteY(); orr(); break; // ORA (absolute, Y)
case 0x1a: swallow(); break; // *NOP (implied)
case 0x1b: fixup(Address_AbsoluteY()); slo(memoryRead()); break; // *SLO (absolute, Y)
case 0x1b: FIXUP_RMW(Address_AbsoluteY, asl); orr(); break; // *SLO (absolute, Y)
case 0x1c: fixup(Address_AbsoluteX()); break; // *NOP (absolute, X)
case 0x1d: AM_AbsoluteX(); orr(); break; // ORA (absolute, X)
case 0x1e: FIXUP_RMW(Address_AbsoluteX, asl); break; // ASL (absolute, X)
case 0x1f: fixup(Address_AbsoluteX()); slo(memoryRead()); break; // *SLO (absolute, X)
case 0x1f: FIXUP_RMW(Address_AbsoluteX, asl); orr(); break; // *SLO (absolute, X)
case 0x20: jsr(); break; // JSR (absolute)
case 0x21: AM_IndexedIndirectX(); andr(); break; // AND (indexed indirect X)
case 0x22: jam(); break; // *JAM
case 0x23: rla(AM_IndexedIndirectX()); break; // *RLA (indexed indirect X)
case 0x23: RMW(Address_IndexedIndirectX, rol); andr(); break; // *RLA (indexed indirect X)
case 0x24: bit(A(), AM_ZeroPage()); break; // BIT (zero page)
case 0x25: AM_ZeroPage(); andr(); break; // AND (zero page)
case 0x26: RMW(Address_ZeroPage, rol); break; // ROL (zero page)
case 0x27: rla(AM_ZeroPage()); break; // *RLA (zero page)
case 0x27: RMW(Address_ZeroPage, rol); andr(); break; // *RLA (zero page)
case 0x28: swallow(); plp(); break; // PLP (implied)
case 0x29: AM_Immediate(); andr(); break; // AND (immediate)
case 0x2a: swallow(); A() = rol(A()); break; // ROL A (implied)
case 0x2b: anc(AM_Immediate()); break; // *ANC (immediate)
case 0x2b: AM_Immediate(); anc(); break; // *ANC (immediate)
case 0x2c: bit(A(), AM_Absolute()); break; // BIT (absolute)
case 0x2d: AM_Absolute(); andr(); break; // AND (absolute)
case 0x2e: RMW(Address_Absolute, rol); break; // ROL (absolute)
case 0x2f: rla(AM_Absolute()); break; // *RLA (absolute)
case 0x2f: RMW(Address_Absolute, rol); andr(); break; // *RLA (absolute)
case 0x30: branch(negative()); break; // BMI (relative)
case 0x31: AM_IndirectIndexedY(); andr(); break; // AND (indirect indexed Y)
case 0x32: jam(); break; // *JAM
case 0x33: fixup(Address_IndirectIndexedY()); rla(memoryRead()); break; // *RLA (indirect indexed Y)
case 0x33: FIXUP_RMW(Address_IndirectIndexedY, rol); andr(); break; // *RLA (indirect indexed Y)
case 0x34: AM_ZeroPageX(); break; // *NOP (zero page, X)
case 0x35: AM_ZeroPageX(); andr(); break; // AND (zero page, X)
case 0x36: RMW(Address_ZeroPageX, rol); break; // ROL (zero page, X)
case 0x37: rla(AM_ZeroPageX()); break; // *RLA (zero page, X)
case 0x37: RMW(Address_ZeroPageX, rol); andr(); break; // *RLA (zero page, X)
case 0x38: swallow(); set_flag(CF); break; // SEC (implied)
case 0x39: AM_AbsoluteY(); andr(); break; // AND (absolute, Y)
case 0x3a: swallow(); break; // *NOP (implied)
case 0x3b: fixup(Address_AbsoluteY()); rla(memoryRead()); break; // *RLA (absolute, Y)
case 0x3b: FIXUP_RMW(Address_AbsoluteY, rol); andr(); break; // *RLA (absolute, Y)
case 0x3c: fixup(Address_AbsoluteX()); break; // *NOP (absolute, X)
case 0x3d: AM_AbsoluteX(); andr(); break; // AND (absolute, X)
case 0x3e: FIXUP_RMW(Address_AbsoluteX, rol); break; // ROL (absolute, X)
case 0x3f: fixup(Address_AbsoluteX()); rla(memoryRead()); break; // *RLA (absolute, X)
case 0x3f: FIXUP_RMW(Address_AbsoluteX, rol); andr(); break; // *RLA (absolute, X)
case 0x40: swallow(); rti(); break; // RTI (implied)
case 0x41: AM_IndexedIndirectX(); eorr(); break; // EOR (indexed indirect X)
case 0x42: jam(); break; // *JAM
case 0x43: sre(AM_IndexedIndirectX()); break; // *SRE (indexed indirect X)
case 0x43: RMW(Address_IndexedIndirectX, lsr); eorr(); break; // *SRE (indexed indirect X)
case 0x44: AM_ZeroPage(); break; // *NOP (zero page)
case 0x45: AM_ZeroPage(); eorr(); break; // EOR (zero page)
case 0x46: RMW(Address_ZeroPage, lsr); break; // LSR (zero page)
case 0x47: sre(AM_ZeroPage()); break; // *SRE (zero page)
case 0x47: RMW(Address_ZeroPage, lsr); eorr(); break; // *SRE (zero page)
case 0x48: swallow(); push(A()); break; // PHA (implied)
case 0x49: AM_Immediate(); eorr(); break; // EOR (immediate)
case 0x4a: swallow(); A() = lsr(A()); break; // LSR A (implied)
case 0x4b: asr(AM_Immediate()); break; // *ASR (immediate)
case 0x4b: AM_Immediate(); andr(); A() = lsr(A()); break; // *ASR (immediate)
case 0x4c: jump(Address_Absolute()); break; // JMP (absolute)
case 0x4d: AM_Absolute(); eorr(); break; // EOR (absolute)
case 0x4e: RMW(Address_Absolute, lsr); break; // LSR (absolute)
case 0x4f: sre(AM_Absolute()); break; // *SRE (absolute)
case 0x4f: RMW(Address_Absolute, lsr); eorr(); break; // *SRE (absolute)
case 0x50: branch(overflow() == 0); break; // BVC (relative)
case 0x51: AM_IndirectIndexedY(); eorr(); break; // EOR (indirect indexed Y)
case 0x52: jam(); break; // *JAM
case 0x53: fixup(Address_IndirectIndexedY()); sre(memoryRead()); break; // *SRE (indirect indexed Y)
case 0x53: FIXUP_RMW(Address_IndirectIndexedY, lsr); eorr(); break; // *SRE (indirect indexed Y)
case 0x54: AM_ZeroPageX(); break; // *NOP (zero page, X)
case 0x55: AM_ZeroPageX(); eorr(); break; // EOR (zero page, X)
case 0x56: RMW(Address_ZeroPageX, lsr); break; // LSR (zero page, X)
case 0x57: sre(AM_ZeroPageX()); break; // *SRE (zero page, X)
case 0x57: RMW(Address_ZeroPageX, lsr); eorr(); break; // *SRE (zero page, X)
case 0x58: swallow(); reset_flag(IF); break; // CLI (implied)
case 0x59: AM_AbsoluteY(); eorr(); break; // EOR (absolute, Y)
case 0x5a: swallow(); break; // *NOP (implied)
case 0x5b: fixup(Address_AbsoluteY()); sre(memoryRead()); break; // *SRE (absolute, Y)
case 0x5b: FIXUP_RMW(Address_AbsoluteY, lsr); eorr(); break; // *SRE (absolute, Y)
case 0x5c: fixup(Address_AbsoluteX()); break; // *NOP (absolute, X)
case 0x5d: AM_AbsoluteX(); eorr(); break; // EOR (absolute, X)
case 0x5e: FIXUP_RMW(Address_AbsoluteX, lsr); break; // LSR (absolute, X)
case 0x5f: fixup(Address_AbsoluteX()); sre(memoryRead()); break; // *SRE (absolute, X)
case 0x5f: FIXUP_RMW(Address_AbsoluteX, lsr); eorr(); break; // *SRE (absolute, X)
case 0x60: swallow(); rts(); break; // RTS (implied)
case 0x61: AM_IndexedIndirectX(); adc(); break; // ADC (indexed indirect X)
case 0x62: jam(); break; // *JAM
case 0x63: rra(AM_IndexedIndirectX()); break; // *RRA (indexed indirect X)
case 0x63: RMW(Address_IndexedIndirectX, ror); adc(); break; // *RRA (indexed indirect X)
case 0x64: AM_ZeroPage(); break; // *NOP (zero page)
case 0x65: AM_ZeroPage(); adc(); break; // ADC (zero page)
case 0x66: RMW(Address_ZeroPage, ror); break; // ROR (zero page)
case 0x67: rra(AM_ZeroPage()); break; // *RRA (zero page)
case 0x67: RMW(Address_ZeroPage, ror); adc(); break; // *RRA (zero page)
case 0x68: swallow(); swallow_stack(); A() = through(pop()); break; // PLA (implied)
case 0x69: AM_Immediate(); adc(); break; // ADC (immediate)
case 0x6a: swallow(); A() = ror(A()); break; // ROR A (implied)
@ -245,24 +245,24 @@ int EightBit::MOS6502::execute() noexcept {
case 0x6c: jump(Address_Indirect()); break; // JMP (indirect)
case 0x6d: AM_Absolute(); adc(); break; // ADC (absolute)
case 0x6e: RMW(Address_Absolute, ror); break; // ROR (absolute)
case 0x6f: rra(AM_Absolute()); break; // *RRA (absolute)
case 0x6f: RMW(Address_Absolute, ror); adc(); break; // *RRA (absolute)
case 0x70: branch(overflow()); break; // BVS (relative)
case 0x71: AM_IndirectIndexedY(); adc(); break; // ADC (indirect indexed Y)
case 0x72: jam(); break; // *JAM
case 0x73: fixup(Address_IndirectIndexedY()); rra(memoryRead()); break; // *RRA (indirect indexed Y)
case 0x73: FIXUP_RMW(Address_IndirectIndexedY, ror); adc(); break; // *RRA (indirect indexed Y)
case 0x74: AM_ZeroPageX(); break; // *NOP (zero page, X)
case 0x75: AM_ZeroPageX(); adc(); break; // ADC (zero page, X)
case 0x76: RMW(Address_ZeroPageX, ror); break; // ROR (zero page, X)
case 0x77: rra(AM_ZeroPageX()); break; // *RRA (zero page, X)
case 0x77: RMW(Address_ZeroPageX, ror); adc(); break; // *RRA (zero page, X)
case 0x78: swallow(); set_flag(IF); break; // SEI (implied)
case 0x79: AM_AbsoluteY(); adc(); break; // ADC (absolute, Y)
case 0x7a: swallow(); break; // *NOP (implied)
case 0x7b: fixup(Address_AbsoluteY()); rra(memoryRead()); break; // *RRA (absolute, Y)
case 0x7b: FIXUP_RMW(Address_AbsoluteY, ror); adc(); break; // *RRA (absolute, Y)
case 0x7c: fixup(Address_AbsoluteX()); break; // *NOP (absolute, X)
case 0x7d: AM_AbsoluteX(); adc(); break; // ADC (absolute, X)
case 0x7e: FIXUP_RMW(Address_AbsoluteX, ror); break; // ROR (absolute, X)
case 0x7f: fixup(Address_AbsoluteX()); rra(memoryRead()); break; // *RRA (absolute, X)
case 0x7f: FIXUP_RMW(Address_AbsoluteX, ror); adc(); break; // *RRA (absolute, X)
case 0x80: AM_Immediate(); break; // *NOP (immediate)
case 0x81: memoryWrite(Address_IndexedIndirectX(), A()); break; // STA (indexed indirect X)
@ -343,7 +343,7 @@ int EightBit::MOS6502::execute() noexcept {
case 0xc8: swallow(); Y() = inc(Y()); break; // INY (implied)
case 0xc9: AM_Immediate(); cmp(A()); break; // CMP (immediate)
case 0xca: swallow(); X() = dec(X()); break; // DEX (implied)
case 0xcb: axs(AM_Immediate()); break; // *AXS (immediate)
case 0xcb: AM_Immediate(); axs(); break; // *AXS (immediate)
case 0xcc: AM_Absolute(); cmp(Y()); break; // CPY (absolute)
case 0xcd: AM_Absolute(); cmp(A()); break; // CMP (absolute)
case 0xce: RMW(Address_Absolute, dec); break; // DEC (absolute)
@ -620,7 +620,7 @@ void EightBit::MOS6502::rts() noexcept {
// Undocumented compound instructions
void EightBit::MOS6502::anc(const uint8_t value) noexcept {
void EightBit::MOS6502::anc() noexcept {
andr();
set_flag(CF, A() & Bit7);
}
@ -655,36 +655,11 @@ void EightBit::MOS6502::arr_b(const uint8_t value) noexcept {
set_flag(VF, overflow((A() ^ (A() << 1))));
}
void EightBit::MOS6502::asr(const uint8_t value) noexcept {
andr();
A() = lsr(A());
}
void EightBit::MOS6502::axs(const uint8_t value) noexcept {
X() = through(sub_b(A() & X(), value));
void EightBit::MOS6502::axs() noexcept {
X() = through(sub_b(A() & X(), BUS().DATA()));
reset_flag(CF, m_intermediate.high);
}
void EightBit::MOS6502::rla(const uint8_t value) noexcept {
memoryModifyWrite(rol(value));
andr();
}
void EightBit::MOS6502::rra(const uint8_t value) noexcept {
memoryModifyWrite(ror(value));
adc();
}
void EightBit::MOS6502::slo(const uint8_t value) noexcept {
memoryModifyWrite(asl(value));
orr();
}
void EightBit::MOS6502::sre(const uint8_t value) noexcept {
memoryModifyWrite(lsr(value));
eorr();
}
void EightBit::MOS6502::jam() noexcept {
swallow();
swallow();