mirror of
https://github.com/MoleskiCoder/EightBit.git
synced 2025-01-01 11:29:17 +00:00
Sync with .Net version
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
This commit is contained in:
Adrian Conlon
parent
2d7f87018c
commit
acf6cf6c71
@ -69,7 +69,19 @@ namespace EightBit {
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[[nodiscard]] auto& IYH() { return IY().high; }
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[[nodiscard]] auto& IYL() { return IY().low; }
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// ** From the Z80 CPU User Manual
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// Memory Refresh(R) Register.The Z80 CPU contains a memory refresh counter,
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// enabling dynamic memories to be used with the same ease as static memories.Seven bits
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// of this 8-bit register are automatically incremented after each instruction fetch.The eighth
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// bit remains as programmed, resulting from an LD R, A instruction. The data in the refresh
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// counter is sent out on the lower portion of the address bus along with a refresh control
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// signal while the CPU is decoding and executing the fetched instruction. This mode of refresh
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// is transparent to the programmer and does not slow the CPU operation.The programmer
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// can load the R register for testing purposes, but this register is normally not used by the
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// programmer. During refresh, the contents of the I Register are placed on the upper eight
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// bits of the address bus.
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[[nodiscard]] auto& REFRESH() { return m_refresh; }
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[[nodiscard]] auto& IV() { return iv; }
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[[nodiscard]] auto& IM() { return m_interruptMode; }
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[[nodiscard]] auto& IFF1() { return m_iff1; }
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@ -85,6 +97,13 @@ namespace EightBit {
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DECLARE_PIN_INPUT(NMI)
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DECLARE_PIN_OUTPUT(M1)
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// ** From the Z80 CPU User Manual
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// RFSH.Refresh(output, active Low). RFSH, together with MREQ, indicates that the lower
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// seven bits of the system’s address bus can be used as a refresh address to the system’s
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// dynamic memories.
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DECLARE_PIN_OUTPUT(RFSH)
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DECLARE_PIN_OUTPUT(MREQ)
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DECLARE_PIN_OUTPUT(IORQ)
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DECLARE_PIN_OUTPUT(RD)
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@ -137,10 +156,37 @@ namespace EightBit {
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m_displacement = fetchByte();
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}
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uint8_t fetchInitialOpCode() {
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// ** From the Z80 CPU User Manual
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// Figure 5 depicts the timing during an M1 (op code fetch) cycle. The Program Counter is
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// placed on the address bus at the beginning of the M1 cycle. One half clock cycle later, the
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// MREQ signal goes active. At this time, the address to memory has had time to stabilize so
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// that the falling edge of MREQ can be used directly as a chip enable clock to dynamic
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// memories. The RD line also goes active to indicate that the memory read data should be
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// enabled onto the CPU data bus. The CPU samples the data from the memory space on the
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// data bus with the rising edge of the clock of state T3, and this same edge is used by the
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// CPU to turn off the RD and MREQ signals. As a result, the data is sampled by the CPU
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// before the RD signal becomes inactive. Clock states T3 and T4 of a fetch cycle are used to
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// refresh dynamic memories. The CPU uses this time to decode and execute the fetched
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// instruction so that no other concurrent operation can be performed.
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uint8_t readInitialOpCode() {
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lowerM1();
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const auto returned = fetchByte();
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const auto returned = IntelProcessor::busRead(PC());
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raiseM1();
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tick(2);
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BUS().ADDRESS().low = REFRESH();
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BUS().ADDRESS().high = IV();
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lowerRFSH();
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lowerMREQ();
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tick();
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raiseMREQ();
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raiseRFSH();
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tick();
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return returned;
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}
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uint8_t fetchInitialOpCode() {
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const auto returned = readInitialOpCode();
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++PC();
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return returned;
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}
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126
Z80/src/Z80.cpp
126
Z80/src/Z80.cpp
@ -28,13 +28,14 @@ EightBit::Z80::Z80(Bus& bus, InputOutput& ports)
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m_prefixCB = m_prefixDD = m_prefixED = m_prefixFD = false;
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});
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LoweredM1.connect([this](EventArgs) {
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RaisedM1.connect([this](EventArgs) {
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++REFRESH();
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});
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}
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DEFINE_PIN_LEVEL_CHANGERS(NMI, Z80);
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DEFINE_PIN_LEVEL_CHANGERS(M1, Z80);
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DEFINE_PIN_LEVEL_CHANGERS(RFSH, Z80);
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DEFINE_PIN_LEVEL_CHANGERS(MREQ, Z80);
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DEFINE_PIN_LEVEL_CHANGERS(IORQ, Z80);
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DEFINE_PIN_LEVEL_CHANGERS(RD, Z80);
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@ -725,12 +726,28 @@ int EightBit::Z80::step() {
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handleNMI();
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handled = true;
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} else if (lowered(INT())) {
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raiseINT();
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raiseHALT();
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if (IFF1()) {
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handleINT();
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handled = true;
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}
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} else if (lowered(HALT())) {
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// ** From the Z80 CPU User Manual
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// When a software HALT instruction is executed, the CPU executes NOPs until an interrupt
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// is received(either a nonmaskable or a maskable interrupt while the interrupt flip-flop is
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// enabled). The two interrupt lines are sampled with the rising clock edge during each T4
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// state as depicted in Figure 11.If a nonmaskable interrupt is received or a maskable interrupt
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// is received and the interrupt enable flip-flop is set, then the HALT state is exited on
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// the next rising clock edge.The following cycle is an interrupt acknowledge cycle corresponding
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// to the type of interrupt that was received.If both are received at this time, then
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// the nonmaskable interrupt is acknowledged because it is the highest priority.The purpose
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// of executing NOP instructions while in the HALT state is to keep the memory refresh signals
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// active.Each cycle in the HALT state is a normal M1(fetch) cycle except that the data
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// received from the memory is ignored and an NOP instruction is forced internally to the
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// CPU.The HALT acknowledge signal is active during this time indicating that the processor
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// is in the HALT state.
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const auto discarded = readInitialOpCode();
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execute(0); // NOP
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handled = true;
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}
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@ -800,10 +817,10 @@ void EightBit::Z80::executeCB(const int x, const int y, const int z) {
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UNREACHABLE;
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}
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F() = adjustSZP<Z80>(F(), operand);
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tick(8);
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tick(4);
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break;
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} case 1: // BIT y, r[z]
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tick(8);
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tick(4);
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bit(F(), y, operand);
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if (indirect) {
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F() = adjustXY<Z80>(F(), MEMPTR().high);
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@ -813,11 +830,11 @@ void EightBit::Z80::executeCB(const int x, const int y, const int z) {
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}
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break;
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case 2: // RES y, r[z]
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tick(8);
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tick(4);
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operand = res(y, operand);
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break;
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case 3: // SET y, r[z]
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tick(8);
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tick(4);
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operand = set(y, operand);
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break;
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default:
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@ -843,7 +860,6 @@ void EightBit::Z80::executeED(const int x, const int y, const int z, const int p
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switch (x) {
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case 0:
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case 3: // Invalid instruction, equivalent to NONI followed by NOP
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tick(8);
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break;
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case 1:
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switch (z) {
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@ -854,7 +870,7 @@ void EightBit::Z80::executeED(const int x, const int y, const int z, const int p
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R(y, BUS().DATA());
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F() = adjustSZPXY<Z80>(F(), BUS().DATA());
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F() = clearBit(F(), NF | HC);
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tick(12);
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tick(4);
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break;
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case 1: // Output to port with 16-bit address
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(MEMPTR() = BUS().ADDRESS() = BC())++;
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@ -863,7 +879,7 @@ void EightBit::Z80::executeED(const int x, const int y, const int z, const int p
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else // OUT (C),r[y]
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BUS().DATA() = R(y);
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writePort();
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tick(12);
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tick(4);
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break;
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case 2: // 16-bit add/subtract with carry
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switch (q) {
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@ -876,7 +892,7 @@ void EightBit::Z80::executeED(const int x, const int y, const int z, const int p
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default:
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UNREACHABLE;
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}
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tick(15);
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tick(7);
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break;
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case 3: // Retrieve/store register pair from/to immediate address
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BUS().ADDRESS() = fetchWord();
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@ -890,11 +906,10 @@ void EightBit::Z80::executeED(const int x, const int y, const int z, const int p
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default:
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UNREACHABLE;
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}
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tick(20);
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tick(12);
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break;
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case 4: // Negate accumulator
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A() = neg(F(), A());
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tick(8);
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break;
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case 5: // Return from interrupt
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switch (y) {
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@ -905,7 +920,7 @@ void EightBit::Z80::executeED(const int x, const int y, const int z, const int p
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retn(); // RETN
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break;
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}
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tick(14);
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tick(6);
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break;
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case 6: // Set interrupt mode
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switch (y) {
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@ -926,41 +941,39 @@ void EightBit::Z80::executeED(const int x, const int y, const int z, const int p
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default:
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UNREACHABLE;
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}
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tick(8);
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break;
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case 7: // Assorted ops
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switch (y) {
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case 0: // LD I,A
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IV() = A();
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tick(9);
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tick();
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break;
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case 1: // LD R,A
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REFRESH() = A();
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tick(9);
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tick();
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break;
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case 2: // LD A,I
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F() = adjustSZXY<Z80>(F(), A() = IV());
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F() = clearBit(F(), NF | HC);
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F() = setBit(F(), PF, IFF2());
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tick(9);
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tick();
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break;
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case 3: // LD A,R
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F() = adjustSZXY<Z80>(F(), A() = REFRESH());
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F() = clearBit(F(), NF | HC);
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F() = setBit(F(), PF, IFF2());
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tick(9);
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tick();
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break;
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case 4: // RRD
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rrd(F(), HL(), A());
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tick(18);
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tick(10);
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break;
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case 5: // RLD
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rld(F(), HL(), A());
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tick(18);
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tick(10);
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break;
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case 6: // NOP
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case 7: // NOP
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tick(4);
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break;
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default:
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UNREACHABLE;
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@ -1067,7 +1080,7 @@ void EightBit::Z80::executeED(const int x, const int y, const int z, const int p
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}
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break;
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}
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tick(16);
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tick(8);
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break;
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}
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}
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@ -1081,22 +1094,18 @@ void EightBit::Z80::executeOther(const int x, const int y, const int z, const in
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case 0: // Relative jumps and assorted ops
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switch (y) {
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case 0: // NOP
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if (m_prefixDD)
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tick(4);
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tick(4);
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break;
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case 1: // EX AF AF'
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exxAF();
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tick(4);
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break;
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case 2: // DJNZ d
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if (jrConditional(--B()))
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tick(5);
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tick(8);
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tick(4);
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break;
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case 3: // JR d
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jr(fetchByte());
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tick(12);
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tick(8);
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break;
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case 4: // JR cc,d
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case 5:
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@ -1104,7 +1113,7 @@ void EightBit::Z80::executeOther(const int x, const int y, const int z, const in
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case 7:
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if (jrConditionalFlag(F(), y - 4))
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tick(5);
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tick(5);
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tick(3);
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break;
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default:
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UNREACHABLE;
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@ -1114,11 +1123,11 @@ void EightBit::Z80::executeOther(const int x, const int y, const int z, const in
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switch (q) {
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case 0: // LD rp,nn
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RP(p) = fetchWord();
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tick(10);
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tick(6);
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break;
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case 1: // ADD HL,rp
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HL2() = add(F(), HL2(), RP(p));
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tick(11);
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tick(7);
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break;
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default:
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UNREACHABLE;
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@ -1132,24 +1141,24 @@ void EightBit::Z80::executeOther(const int x, const int y, const int z, const in
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(MEMPTR() = BUS().ADDRESS() = BC())++;
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MEMPTR().high = BUS().DATA() = A();
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busWrite();
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tick(7);
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tick(3);
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break;
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case 1: // LD (DE),A
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(MEMPTR() = BUS().ADDRESS() = DE())++;
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MEMPTR().high = BUS().DATA() = A();
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busWrite();
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tick(7);
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tick(3);
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break;
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case 2: // LD (nn),HL
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BUS().ADDRESS() = fetchWord();
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setWord(HL2());
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tick(16);
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tick(12);
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break;
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case 3: // LD (nn),A
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(MEMPTR() = BUS().ADDRESS() = fetchWord())++;
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MEMPTR().high = BUS().DATA() = A();
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busWrite();
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tick(13);
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tick(9);
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break;
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default:
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UNREACHABLE;
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@ -1160,22 +1169,22 @@ void EightBit::Z80::executeOther(const int x, const int y, const int z, const in
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case 0: // LD A,(BC)
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(MEMPTR() = BUS().ADDRESS() = BC())++;
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A() = busRead();
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tick(7);
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tick(3);
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break;
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case 1: // LD A,(DE)
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(MEMPTR() = BUS().ADDRESS() = DE())++;
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A() = busRead();
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tick(7);
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tick(3);
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break;
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case 2: // LD HL,(nn)
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BUS().ADDRESS() = fetchWord();
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HL2() = getWord();
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tick(16);
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tick(12);
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break;
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case 3: // LD A,(nn)
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(MEMPTR() = BUS().ADDRESS() = fetchWord())++;
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A() = busRead();
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tick(13);
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tick(9);
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break;
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default:
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UNREACHABLE;
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@ -1196,13 +1205,12 @@ void EightBit::Z80::executeOther(const int x, const int y, const int z, const in
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default:
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UNREACHABLE;
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}
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tick(6);
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tick(2);
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break;
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case 4: // 8-bit INC
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if (m_displaced && memoryY)
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fetchDisplacement();
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R(y, increment(F(), R(y)));
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tick(4);
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break;
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case 5: // 8-bit DEC
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if (memoryY) {
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@ -1211,7 +1219,6 @@ void EightBit::Z80::executeOther(const int x, const int y, const int z, const in
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fetchDisplacement();
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}
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R(y, decrement(F(), R(y)));
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tick(4);
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break;
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case 6: // 8-bit load immediate
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if (memoryY) {
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@ -1220,7 +1227,7 @@ void EightBit::Z80::executeOther(const int x, const int y, const int z, const in
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fetchDisplacement();
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}
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R(y, fetchByte()); // LD r,n
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tick(7);
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tick(3);
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break;
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case 7: // Assorted operations on accumulator/flags
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switch (y) {
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@ -1251,7 +1258,6 @@ void EightBit::Z80::executeOther(const int x, const int y, const int z, const in
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default:
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UNREACHABLE;
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}
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tick(4);
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break;
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default:
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UNREACHABLE;
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@ -1295,7 +1301,6 @@ void EightBit::Z80::executeOther(const int x, const int y, const int z, const in
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if (memoryY || memoryZ) // M operations
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tick(3);
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}
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tick(4);
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break;
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case 2: { // Operate on accumulator and register/memory location
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if (memoryZ) {
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@ -1332,7 +1337,6 @@ void EightBit::Z80::executeOther(const int x, const int y, const int z, const in
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default:
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UNREACHABLE;
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}
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tick(4);
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break;
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}
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case 3:
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@ -1340,31 +1344,28 @@ void EightBit::Z80::executeOther(const int x, const int y, const int z, const in
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case 0: // Conditional return
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if (returnConditionalFlag(F(), y))
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tick(6);
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tick(5);
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tick(1);
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break;
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case 1: // POP & various ops
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switch (q) {
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case 0: // POP rp2[p]
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RP2(p) = popWord();
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tick(10);
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tick(6);
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break;
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case 1:
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switch (p) {
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case 0: // RET
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ret();
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tick(10);
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tick(6);
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break;
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case 1: // EXX
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exx();
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tick(4);
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break;
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case 2: // JP (HL)
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jump(HL2());
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tick(4);
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break;
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case 3: // LD SP,HL
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SP() = HL2();
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tick(4);
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break;
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default:
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UNREACHABLE;
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@ -1376,13 +1377,13 @@ void EightBit::Z80::executeOther(const int x, const int y, const int z, const in
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break;
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case 2: // Conditional jump
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jumpConditionalFlag(F(), y);
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tick(10);
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tick(6);
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break;
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case 3: // Assorted operations
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switch (y) {
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case 0: // JP nn
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jump(MEMPTR() = fetchWord());
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tick(10);
|
||||
tick(6);
|
||||
break;
|
||||
case 1: // CB prefix
|
||||
m_prefixCB = true;
|
||||
@ -1395,27 +1396,24 @@ void EightBit::Z80::executeOther(const int x, const int y, const int z, const in
|
||||
break;
|
||||
case 2: // OUT (n),A
|
||||
writePort(fetchByte());
|
||||
tick(11);
|
||||
tick(7);
|
||||
break;
|
||||
case 3: // IN A,(n)
|
||||
A() = readPort(fetchByte());
|
||||
tick(11);
|
||||
tick(7);
|
||||
break;
|
||||
case 4: // EX (SP),HL
|
||||
xhtl(HL2());
|
||||
tick(19);
|
||||
tick(15);
|
||||
break;
|
||||
case 5: // EX DE,HL
|
||||
std::swap(DE(), HL());
|
||||
tick(4);
|
||||
break;
|
||||
case 6: // DI
|
||||
di();
|
||||
tick(4);
|
||||
break;
|
||||
case 7: // EI
|
||||
ei();
|
||||
tick(4);
|
||||
break;
|
||||
default:
|
||||
UNREACHABLE;
|
||||
@ -1424,19 +1422,19 @@ void EightBit::Z80::executeOther(const int x, const int y, const int z, const in
|
||||
case 4: // Conditional call: CALL cc[y], nn
|
||||
if (callConditionalFlag(F(), y))
|
||||
tick(7);
|
||||
tick(10);
|
||||
tick(6);
|
||||
break;
|
||||
case 5: // PUSH & various ops
|
||||
switch (q) {
|
||||
case 0: // PUSH rp2[p]
|
||||
pushWord(RP2(p));
|
||||
tick(11);
|
||||
tick(7);
|
||||
break;
|
||||
case 1:
|
||||
switch (p) {
|
||||
case 0: // CALL nn
|
||||
call(MEMPTR() = fetchWord());
|
||||
tick(17);
|
||||
tick(13);
|
||||
break;
|
||||
case 1: // DD prefix
|
||||
m_displaced = m_prefixDD = true;
|
||||
@ -1488,12 +1486,12 @@ void EightBit::Z80::executeOther(const int x, const int y, const int z, const in
|
||||
default:
|
||||
UNREACHABLE;
|
||||
}
|
||||
tick(7);
|
||||
tick(3);
|
||||
break;
|
||||
}
|
||||
case 7: // Restart: RST y * 8
|
||||
restart(y << 3);
|
||||
tick(11);
|
||||
tick(7);
|
||||
break;
|
||||
default:
|
||||
UNREACHABLE;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user