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https://github.com/MoleskiCoder/EightBit.git
synced 2026-10-22 07:02:37 +00:00
Reflect that the I/O for Intel style processors isn't part of the CPU, but attached to the Bus and access controlled by the CPU.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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+27
-12
@@ -6,7 +6,6 @@
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#include <stdexcept>
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#include <Bus.h>
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#include <InputOutput.h>
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#include <IntelProcessor.h>
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#include <EventArgs.h>
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#include <Signal.h>
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@@ -23,7 +22,7 @@ namespace EightBit {
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CF = Bit0,
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};
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Intel8080(Bus& bus, InputOutput& ports);
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Intel8080(Bus& bus);
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Signal<Intel8080> ExecutingInstruction;
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Signal<Intel8080> ExecutedInstruction;
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@@ -36,14 +35,30 @@ namespace EightBit {
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virtual register16_t& DE() final;
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virtual register16_t& HL() final;
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bool requestingIO() { return m_requestIO; }
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bool requestingMemory() { return m_requestMemory; }
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bool requestingRead() { return raised(DBIN()); }
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bool requestingWrite() { return lowered(WR()); }
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DECLARE_PIN_OUTPUT(DBIN) // Active high
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DECLARE_PIN_OUTPUT(WR) // Active low
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protected:
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virtual void handleRESET() final;
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virtual void handleINT() final;
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void handleRESET() final;
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void handleINT() final;
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void memoryWrite() final;
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uint8_t memoryRead() final;
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void busWrite() final;
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uint8_t busRead() final;
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private:
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bool m_interruptEnable = false;
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bool m_requestIO = false;
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bool m_requestMemory = false;
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InputOutput& m_ports;
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bool m_interruptEnable = false;
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register16_t af;
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register16_t bc = Mask16;
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@@ -65,7 +80,7 @@ namespace EightBit {
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case 0b101:
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return L();
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case 0b110:
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return busRead(HL());
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return IntelProcessor::memoryRead(HL());
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case 0b111:
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return A();
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default:
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@@ -94,7 +109,7 @@ namespace EightBit {
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L() = value;
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break;
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case 0b110:
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busWrite(HL(), value);
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IntelProcessor::memoryWrite(HL(), value);
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break;
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case 0b111:
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A() = value;
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@@ -179,10 +194,10 @@ namespace EightBit {
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void xhtl(register16_t& exchange);
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void writePort(uint8_t port);
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void writePort();
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void portWrite(uint8_t port);
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void portWrite();
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uint8_t readPort(uint8_t port);
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uint8_t readPort();
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uint8_t portRead(uint8_t port);
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uint8_t portRead();
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};
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}
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+56
-25
@@ -1,11 +1,13 @@
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#include "stdafx.h"
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#include "Intel8080.h"
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EightBit::Intel8080::Intel8080(Bus& bus, InputOutput& ports)
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: IntelProcessor(bus),
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m_ports(ports) {
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EightBit::Intel8080::Intel8080(Bus& bus)
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: IntelProcessor(bus){
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}
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DEFINE_PIN_LEVEL_CHANGERS(DBIN, Intel8080);
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DEFINE_PIN_LEVEL_CHANGERS(WR, Intel8080);
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EightBit::register16_t& EightBit::Intel8080::AF() {
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af.low = (af.low | Bit1) & ~(Bit5 | Bit3);
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return af;
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@@ -23,6 +25,31 @@ EightBit::register16_t& EightBit::Intel8080::HL() {
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return hl;
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}
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void EightBit::Intel8080::memoryWrite() {
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m_requestMemory = true;
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IntelProcessor::memoryWrite();
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m_requestMemory = false;
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}
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uint8_t EightBit::Intel8080::memoryRead() {
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m_requestMemory = true;
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return IntelProcessor::memoryRead();
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m_requestMemory = false;
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}
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void EightBit::Intel8080::busWrite() {
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lowerWR();
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IntelProcessor::busWrite();
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raiseWR();
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}
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uint8_t EightBit::Intel8080::busRead() {
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raiseDBIN();
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const auto returned = IntelProcessor::busRead();
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lowerDBIN();
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return returned;
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}
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void EightBit::Intel8080::handleRESET() {
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IntelProcessor::handleRESET();
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di();
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@@ -236,33 +263,37 @@ void EightBit::Intel8080::cmc() {
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}
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void EightBit::Intel8080::xhtl(register16_t& exchange) {
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MEMPTR().low = busRead(SP());
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MEMPTR().low = IntelProcessor::memoryRead(SP());
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++BUS().ADDRESS();
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MEMPTR().high = busRead();
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busWrite(exchange.high);
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MEMPTR().high = memoryRead();
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IntelProcessor::memoryWrite(exchange.high);
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exchange.high = MEMPTR().high;
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--BUS().ADDRESS();
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busWrite(exchange.low);
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IntelProcessor::memoryWrite(exchange.low);
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exchange.low = MEMPTR().low;
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}
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void EightBit::Intel8080::writePort(const uint8_t port) {
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BUS().ADDRESS() = register16_t(port, A());
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BUS().DATA() = A();
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writePort();
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void EightBit::Intel8080::portWrite(const uint8_t port) {
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BUS().ADDRESS() = { port, port };
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portWrite();
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}
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void EightBit::Intel8080::writePort() {
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m_ports.write(BUS().ADDRESS().low, BUS().DATA());
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void EightBit::Intel8080::portWrite() {
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m_requestIO = true;
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busWrite();
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m_requestIO = false;
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}
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uint8_t EightBit::Intel8080::readPort(const uint8_t port) {
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BUS().ADDRESS() = register16_t(port, A());
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return readPort();
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uint8_t EightBit::Intel8080::portRead(const uint8_t port) {
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BUS().ADDRESS() = { port, port };
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return portRead();
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}
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uint8_t EightBit::Intel8080::readPort() {
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return BUS().DATA() = m_ports.read(BUS().ADDRESS().low);
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uint8_t EightBit::Intel8080::portRead() {
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m_requestIO = true;
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const auto returned = busRead();
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m_requestIO = false;
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return returned;
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}
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int EightBit::Intel8080::step() {
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@@ -330,11 +361,11 @@ void EightBit::Intel8080::execute(const int x, const int y, const int z, const i
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case 0:
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switch (p) {
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case 0: // LD (BC),A
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busWrite(BC(), A());
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IntelProcessor::memoryWrite(BC(), A());
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tick(7);
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break;
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case 1: // LD (DE),A
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busWrite(DE(), A());
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IntelProcessor::memoryWrite(DE(), A());
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tick(7);
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break;
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case 2: // LD (nn),HL
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@@ -344,7 +375,7 @@ void EightBit::Intel8080::execute(const int x, const int y, const int z, const i
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break;
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case 3: // LD (nn),A
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BUS().ADDRESS() = fetchWord();
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busWrite(A());
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IntelProcessor::memoryWrite(A());
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tick(13);
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break;
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default:
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@@ -354,11 +385,11 @@ void EightBit::Intel8080::execute(const int x, const int y, const int z, const i
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case 1:
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switch (p) {
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case 0: // LD A,(BC)
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A() = busRead(BC());
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A() = IntelProcessor::memoryRead(BC());
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tick(7);
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break;
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case 1: // LD A,(DE)
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A() = busRead(DE());
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A() = IntelProcessor::memoryRead(DE());
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tick(7);
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break;
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case 2: // LD HL,(nn)
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@@ -534,11 +565,11 @@ void EightBit::Intel8080::execute(const int x, const int y, const int z, const i
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tick(10);
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break;
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case 2: // OUT (n),A
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writePort(fetchByte());
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portWrite(fetchByte());
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tick(11);
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break;
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case 3: // IN A,(n)
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A() = readPort(fetchByte());
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A() = portRead(fetchByte());
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tick(11);
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break;
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case 4: // EX (SP),HL
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@@ -6,7 +6,7 @@
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Board::Board(const Configuration& configuration)
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: m_configuration(configuration),
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m_cpu(EightBit::Intel8080(*this, m_ports)),
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m_cpu(EightBit::Intel8080(*this)),
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m_disassembler(*this) {
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}
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