mirror of
https://github.com/MoleskiCoder/EightBit.git
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Refactor the 6809 a little to shift large blocks of code from the header.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
This commit is contained in:
Adrian Conlon
parent
a7835b943a
commit
cca7453e35
@ -12,26 +12,42 @@ namespace EightBit {
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class mc6809 : public BigEndianProcessor {
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public:
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enum StatusBits {
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EF = Bit7, // Entire flag: set if the complete machine state was saved in the stack.
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// If this bit is not set then only program counter and condition code
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// registers were saved in the stack. This bit is used by interrupt
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// handling routines only.
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// The bit is cleared by fast interrupts, and set by all other interrupts.
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FF = Bit6, // Fast interrupt mask: set if the FIRQ interrupt is disabled.
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HF = Bit5, // Half carry: set if there was a carry from bit 3 to bit 4 of the result
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// during the last add operation.
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IF = Bit4, // Interrupt mask: set if the IRQ interrupt is disabled.
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NF = Bit3, // Negative: set if the most significant bit of the result is set.
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// This bit can be set not only by arithmetic and logical operations,
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// but also by load / store operations.
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ZF = Bit2, // Zero: set if the result is zero. Like the N bit, this bit can be
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// set not only by arithmetic and logical operations, but also
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// by load / store operations.
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VF = Bit1, // Overflow: set if there was an overflow during last result calculation.
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// Logical, load and store operations clear this bit.
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CF = Bit0, // Carry: set if there was a carry from the bit 7 during last add
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// operation, or if there was a borrow from last subtract operation,
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// or if bit 7 of the A register was set during last MUL operation.
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// Entire flag: set if the complete machine state was saved in the stack.
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// If this bit is not set then only program counter and condition code
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// registers were saved in the stack. This bit is used by interrupt
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// handling routines only.
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// The bit is cleared by fast interrupts, and set by all other interrupts.
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EF = Bit7,
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// Fast interrupt mask: set if the FIRQ interrupt is disabled.
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FF = Bit6,
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// Half carry: set if there was a carry from bit 3 to bit 4 of the result
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// during the last add operation.
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HF = Bit5,
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// Interrupt mask: set if the IRQ interrupt is disabled.
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IF = Bit4,
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// Negative: set if the most significant bit of the result is set.
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// This bit can be set not only by arithmetic and logical operations,
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// but also by load / store operations.
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NF = Bit3,
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// Zero: set if the result is zero. Like the N bit, this bit can be
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// set not only by arithmetic and logical operations, but also
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// by load / store operations.
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ZF = Bit2,
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// Overflow: set if there was an overflow during last result calculation.
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// Logical, load and store operations clear this bit.
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VF = Bit1,
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// Carry: set if there was a carry from the bit 7 during last add
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// operation, or if there was a borrow from last subtract operation,
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// or if bit 7 of the A register was set during last MUL operation.
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CF = Bit0,
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};
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mc6809(Bus& bus);
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@ -71,131 +87,19 @@ namespace EightBit {
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const uint8_t SWI3vector = 0xf2;
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const uint8_t RESERVEDvector = 0xf0;
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//
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// Register selection for "indexed"
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register16_t& RR(int which);
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void Address_direct() {
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BUS().ADDRESS() = register16_t(fetchByte(), DP());
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}
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// Addressing modes
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void Address_direct();
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void Address_indexed();
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void Address_extended();
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register16_t& RR(int which) {
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ASSUME(which >= 0);
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ASSUME(which <= 3);
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switch (which) {
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case 0b00:
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return X();
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case 0b01:
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return Y();
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case 0b10:
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return U();
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case 0b11:
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return S();
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default:
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UNREACHABLE;
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}
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}
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void Address_indexed() {
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const auto type = fetchByte();
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auto& rr = RR(type & (Bit6 | Bit5));
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switch (type & Bit7) {
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case 0: // EA = ,R + 5-bit offset
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addCycle();
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BUS().ADDRESS() = rr + (type & Mask5);
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break;
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case Bit7: {
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const auto indirect = type & Bit4;
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switch (type & Mask4) {
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case 0b0000: // , R+
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ASSUME(!indirect);
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addCycles(2);
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BUS().ADDRESS() = rr++;
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break;
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case 0b0001: // , R++
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addCycles(3);
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BUS().ADDRESS() = rr;
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rr += 2;
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break;
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case 0b0010: // , -R
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ASSUME(!indirect);
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addCycles(2);
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BUS().ADDRESS() = --rr;
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break;
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case 0b0011: // , --R
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addCycles(3);
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rr -= 2;
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BUS().ADDRESS() = rr;
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break;
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case 0b0100: // , R
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BUS().ADDRESS() = rr;
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break;
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case 0b0101: // B, R
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addCycles(1);
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BUS().ADDRESS() = rr + (int8_t)B();
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break;
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case 0b0110: // A, R
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addCycles(1);
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BUS().ADDRESS() = rr + (int8_t)A();
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break;
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case 0b1000: // n, R (eight-bit)
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addCycles(1);
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BUS().ADDRESS() = rr + (int8_t)fetchByte();
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break;
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case 0b1001: // n, R (sixteen-bit)
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addCycles(4);
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BUS().ADDRESS() = rr + fetchWord();
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break;
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case 0b1011: // D, R
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addCycles(4);
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BUS().ADDRESS() = rr + D();
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break;
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case 0b1100: // n, PCR (eight-bit)
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addCycles(1);
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BUS().ADDRESS() = PC() + (int8_t)fetchByte();
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break;
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case 0b1101: // n, PCR (sixteen-bit)
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addCycles(1);
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BUS().ADDRESS() = PC() + (int16_t)fetchWord().word;
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break;
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default:
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ASSUME(false);
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}
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if (indirect) {
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addCycles(3);
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BUS().ADDRESS() = fetchWord();
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}
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}
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break;
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default:
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UNREACHABLE;
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}
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}
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void Address_extended() {
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BUS().ADDRESS() = fetchWord();
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}
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//
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uint8_t AM_immediate() {
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return fetchByte();
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}
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uint8_t AM_direct() {
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Address_direct();
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return BUS().read();
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}
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uint8_t AM_indexed() {
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Address_indexed();
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return BUS().read();
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}
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uint8_t AM_extended() {
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Address_extended();
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return BUS().read();
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}
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//
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// Addressing mode readers
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uint8_t AM_immediate();
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uint8_t AM_direct();
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uint8_t AM_indexed();
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uint8_t AM_extended();
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void abx();
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uint8_t adc(uint8_t operand, uint8_t data);
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@ -51,7 +51,7 @@ int EightBit::mc6809::execute(uint8_t cell) {
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case 0x70: addCycles(7); BUS().write(neg(AM_extended())); break; // NEG (extended)
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default:
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ASSUME(false);
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UNREACHABLE;
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}
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ASSUME(cycles() > 0);
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@ -60,6 +60,126 @@ int EightBit::mc6809::execute(uint8_t cell) {
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//
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EightBit::register16_t& EightBit::mc6809::RR(int which) {
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ASSUME(which >= 0);
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ASSUME(which <= 3);
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switch (which) {
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case 0b00:
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return X();
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case 0b01:
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return Y();
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case 0b10:
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return U();
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case 0b11:
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return S();
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default:
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UNREACHABLE;
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}
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}
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void EightBit::mc6809::Address_direct() {
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BUS().ADDRESS() = register16_t(fetchByte(), DP());
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}
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void EightBit::mc6809::Address_indexed() {
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const auto type = fetchByte();
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auto& r = RR((type & (Bit6 | Bit5)) >> 5);
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if (type & Bit7) {
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const auto indirect = type & Bit4;
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switch (type & Mask4) {
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case 0b0000: // ,R+
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ASSUME(!indirect);
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addCycles(2);
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BUS().ADDRESS() = r++;
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break;
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case 0b0001: // ,R++
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addCycles(3);
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BUS().ADDRESS() = r;
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r += 2;
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break;
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case 0b0010: // ,-R
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ASSUME(!indirect);
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addCycles(2);
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BUS().ADDRESS() = --r;
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break;
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case 0b0011: // ,--R
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addCycles(3);
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r -= 2;
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BUS().ADDRESS() = r;
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break;
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case 0b0100: // ,R
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BUS().ADDRESS() = r;
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break;
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case 0b0101: // B,R
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addCycles(1);
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BUS().ADDRESS() = r + (int8_t)B();
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break;
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case 0b0110: // A,R
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addCycles(1);
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BUS().ADDRESS() = r + (int8_t)A();
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break;
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case 0b1000: // n,R (eight-bit)
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addCycles(1);
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BUS().ADDRESS() = r + (int8_t)fetchByte();
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break;
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case 0b1001: // n,R (sixteen-bit)
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addCycles(4);
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BUS().ADDRESS() = r + (int16_t)fetchWord().word;
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break;
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case 0b1011: // D,R
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addCycles(4);
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BUS().ADDRESS() = r + D();
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break;
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case 0b1100: // n,PCR (eight-bit)
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addCycles(1);
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BUS().ADDRESS() = PC() + (int8_t)fetchByte();
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break;
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case 0b1101: // n,PCR (sixteen-bit)
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addCycles(1);
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BUS().ADDRESS() = PC() + (int16_t)fetchWord().word;
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break;
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default:
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UNREACHABLE;
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}
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if (indirect) {
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addCycles(3);
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BUS().ADDRESS() = fetchWord();
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}
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} else {
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// EA = ,R + 5-bit offset
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addCycle();
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BUS().ADDRESS() = r + (type & Mask5);
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}
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}
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void EightBit::mc6809::Address_extended() {
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BUS().ADDRESS() = fetchWord();
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}
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//
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uint8_t EightBit::mc6809::AM_immediate() {
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return fetchByte();
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}
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uint8_t EightBit::mc6809::AM_direct() {
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Address_direct();
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return BUS().read();
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}
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uint8_t EightBit::mc6809::AM_indexed() {
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Address_indexed();
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return BUS().read();
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}
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uint8_t EightBit::mc6809::AM_extended() {
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Address_extended();
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return BUS().read();
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}
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//
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void EightBit::mc6809::abx() {
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X() += B();
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}
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