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85 Commits

Author SHA1 Message Date
Adrian.Conlon
329fd269ed Share some more code from the 6502 processor implementation. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-28 18:52:48 +01:00
Adrian.Conlon
73a34f4fae Start a more careful documentation of the I/O registers. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-26 09:46:53 +01:00
Adrian.Conlon
4cbab14750 Remove unused StatusFlags.h header. Not sure why that was still there! 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-25 22:37:10 +01:00
Adrian.Conlon
ae4106ce5a Preliminary MBC1 support. Enough to run cpu_instrs.gb to completion. Hurrah! 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-24 23:23:40 +01:00
Adrian.Conlon
9964070b85 Refactor to allow peek/poke/reference to share a common implementation as much as possible. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-24 11:28:01 +01:00
Adrian.Conlon
448ee2f09f Refactor the MBC implementation to allow a single point of definition. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-24 10:28:31 +01:00
Adrian.Conlon
2c7e32aa78 First stab at implementing MBC1 support for LR35902. Not complete, but all old tests still work. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-23 23:17:45 +01:00
Adrian.Conlon
42b0fdc23d Implement DIV timer (TBC) 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-20 09:52:26 +01:00
Adrian.Conlon
75b17e47a8 Better method of enabling/disabling boot ROM. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-19 17:33:28 +01:00
Adrian.Conlon
86a4e22ae1 First stab at implementing GB timer control. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-18 19:00:10 +01:00
Adrian.Conlon
0457dffba4 Rewrite GB interrupt handling to properly document the trigger sequence. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-18 09:49:06 +01:00
Adrian.Conlon
7948962d70 Because of its boot room, the LR35902 needs a custom clear mechanism. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-10 20:30:37 +01:00
Adrian.Conlon
88d773708c Correct some outstanding LR35902 problems arising. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-06 22:04:13 +01:00
Adrian.Conlon
016b3bca59 Switch to a memory read/write event driven model. All tests passing. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-06 17:06:48 +01:00
Adrian.Conlon
261433bd6e Remove unneeded 16-bit operations. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-27 21:44:24 +01:00
Adrian.Conlon
b6dd48ca63 Some more small clarifications of shared processor implementation. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-25 18:56:43 +01:00
Adrian.Conlon
9a264c7c06 Bring the LR35902 and i8080 increment/decrement implementations in line with the Z80. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-22 10:23:13 +01:00
Adrian.Conlon
0a02c32695 Some things (namely shift.rotate instructions) don't need to be quite so close to the Z80 implementation. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-21 19:23:36 +01:00
Adrian.Conlon
7c3fc469a8 Bring LR35902 a little closer to the Z80 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-20 12:37:54 +01:00
Adrian.Conlon
36fbee35fb Bring the various IntelProcessor derived processors a little closer together. 
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
 2017-07-19 13:59:28 +01:00
Adrian.Conlon
758574007d Ensure GB register accesses pass through bus notification code. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-18 21:41:10 +01:00
Adrian.Conlon
35def4184a Start adding enough infrastructure to support memory mapped IO on LR35902. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-18 00:13:41 +01:00
Adrian.Conlon
af375ab10f Some more shared code. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-22 19:00:53 +01:00
Adrian.Conlon
c9bf24d1fa Tidy up register and static method access. 
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
 2017-06-19 13:53:00 +01:00
Adrian.Conlon
23108a8536 Bring performance back to par by: inlining and static flag register access, where possible. 
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
 2017-06-18 18:14:39 +01:00
Adrian.Conlon
5f288cf0e3 Some more small tidy ups. 
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
 2017-06-16 20:31:32 +01:00
Adrian.Conlon
327d391ecb Remove another chunk of shared code. This time by ensuring the basic layout of registers is consistent. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-16 13:52:10 +01:00
Adrian.Conlon
71e6902aeb Simplify and remove a bunch of code. Getting there! 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-15 22:21:26 +01:00
Adrian.Conlon
66d3a5ae29 Couple of small simplifications. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-13 23:43:21 +01:00
Adrian.Conlon
0291970427 Further work on uniting the 8080 family processor family. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-11 21:08:40 +01:00
Adrian.Conlon
627e41bf35 Introduce an IntelProcessor base class to allow known good implementation to be shared. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-11 09:45:34 +01:00
Adrian.Conlon
838580cc3d More changes to bring LR35902 in line with the Z80 implementation. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-09 16:01:12 +01:00
Adrian.Conlon
93bac42547 Bring LR35902 a little more in line with the Z80 implementation. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-09 11:42:32 +01:00
Adrian.Conlon
f3fe475d44 Implement enough changes to build LR35902 2017-06-09 10:23:51 +01:00
Adrian.Conlon
105032f08a Dump of all my C++ emulators, only Intel8080 integrated so far... 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-04 21:38:34 +01:00