Adrian.Conlon
9964070b85
Refactor to allow peek/poke/reference to share a common implementation as much as possible.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-08-24 11:28:01 +01:00
Adrian.Conlon
448ee2f09f
Refactor the MBC implementation to allow a single point of definition.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-08-24 10:28:31 +01:00
Adrian.Conlon
2c7e32aa78
First stab at implementing MBC1 support for LR35902. Not complete, but all old tests still work.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-08-23 23:17:45 +01:00
Adrian.Conlon
8716035396
Second stage halt implementation: allow halt state to be exited by an interrupt.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-08-20 20:09:21 +01:00
Adrian.Conlon
7948962d70
Because of its boot room, the LR35902 needs a custom clear mechanism.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-08-10 20:30:37 +01:00
Adrian.Conlon
016b3bca59
Switch to a memory read/write event driven model. All tests passing.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-08-06 17:06:48 +01:00
Adrian.Conlon
b6dd48ca63
Some more small clarifications of shared processor implementation.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-07-25 18:56:43 +01:00
Adrian.Conlon
beca76d733
Share instruction decoding mechanism between Intel derived processors.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-07-21 13:33:17 +01:00
Adrian.Conlon
99e3454527
Memory locking is dependent on the GB hardware, not the size of the program, so allow lock ranges to be manually specified.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-07-18 21:40:29 +01:00
Adrian.Conlon
35def4184a
Start adding enough infrastructure to support memory mapped IO on LR35902.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-07-18 00:13:41 +01:00
Adrian.Conlon
017b2a6442
Tidy up memory event handling to make it a bit easier to verify read/write events.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-07-17 21:00:05 +01:00
Adrian.Conlon
4f491f110e
Make the 6502 a little more compatible with other processor implementations.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-07-17 13:46:06 +01:00
Adrian.Conlon
8c81a27224
"Modernise" the 6502 emulator a little. Not complete, but does successfully complete Klaus Dormann tests.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-07-11 21:34:01 +01:00
Adrian.Conlon
3001a97128
Don't bother wiring up memory events that the 6502 doesn't need (I think!)
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-07-08 09:41:07 +01:00
Adrian.Conlon
8256d97b60
Modified to work with my builds of the Klaus Dormann 6502 test suite.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-07-08 01:04:20 +01:00
Adrian.Conlon
3c0a1697fd
Fetching bytes/words and stack access are more processor specific than I thought.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-07-07 09:27:06 +01:00
Adrian.Conlon
f970c45005
Get the loop exit conditions worked out.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-07-06 21:32:52 +01:00
Adrian.Conlon
d4b133e9ac
Show cycles per second as MHz
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-07-05 19:15:58 +01:00
Adrian.Conlon
6db32ae7c5
Small consistency change in the 8-bit memory model.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-07-05 17:44:47 +01:00
Adrian.Conlon
0e7ad4dd01
Correct a couple of inconsistencies in the test harness.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-07-05 17:40:16 +01:00
Adrian.Conlon
983639d530
Correct a couple of header issues in the test harness.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-07-04 13:00:23 +01:00
Adrian.Conlon
88d3e4fd47
Initial stab at getting MOS6502 imported to the EightBit library.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-07-02 22:03:33 +01:00
Adrian.Conlon
6af1857cb0
A few minor consistency tweaks to the i8080 and z80 processors.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-07-02 17:38:19 +01:00
Adrian.Conlon
954887217f
Performance mods: probably about 30% speedup: the best yet.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-06-29 00:50:34 +01:00
Adrian.Conlon
c803387023
A few modifications:
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1) Simplify REFRESH register handling via bit fields.
2) Use static methods in the Z80 emulator, if at all possible
3) Use a decoded opcode lookup, rather than decoding per instruction
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-06-26 23:22:32 +01:00
Adrian.Conlon
d22b695682
Modify test harness to show host CPU cycle efficiency.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-06-25 23:48:15 +01:00
Adrian.Conlon
f776379e96
Share flag adjustments across implementations using templated methods.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-06-22 16:57:38 +01:00
Adrian.Conlon
23b5a5d579
Tidy the test harness a little.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-06-22 10:16:02 +01:00
Adrian.Conlon
8927f412d4
Use a shared test harness.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-06-21 23:55:25 +01:00
Adrian.Conlon
052df61250
Remove get/getWord and set/setWord from memory class. Just use address and data lines on the memory.
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Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
2017-06-20 14:09:44 +01:00
Adrian.Conlon
a4f8770eb0
Correct a couple of small compilation issues.
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Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
2017-06-19 18:08:13 +01:00
Adrian.Conlon
c9bf24d1fa
Tidy up register and static method access.
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Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
2017-06-19 13:53:00 +01:00
Adrian.Conlon
23108a8536
Bring performance back to par by: inlining and static flag register access, where possible.
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Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
2017-06-18 18:14:39 +01:00
Adrian.Conlon
327d391ecb
Remove another chunk of shared code. This time by ensuring the basic layout of registers is consistent.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-06-16 13:52:10 +01:00
Adrian.Conlon
71e6902aeb
Simplify and remove a bunch of code. Getting there!
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-06-15 22:21:26 +01:00
Adrian.Conlon
66d3a5ae29
Couple of small simplifications.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-06-13 23:43:21 +01:00
Adrian.Conlon
828e081a6e
More tidying of shareable code
2017-06-12 14:33:00 +01:00
Adrian.Conlon
0291970427
Further work on uniting the 8080 family processor family.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-06-11 21:08:40 +01:00
Adrian.Conlon
627e41bf35
Introduce an IntelProcessor base class to allow known good implementation to be shared.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-06-11 09:45:34 +01:00
Adrian.Conlon
b1aa523dcc
Small simplifications to base Processor class.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-06-10 12:42:55 +01:00
Adrian.Conlon
f3fe475d44
Implement enough changes to build LR35902
2017-06-09 10:23:51 +01:00
Adrian.Conlon
d8977d32d3
More MEMPTR clarifications.
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This time to avoid temporary variables, in a similar manner to Z80 hardware.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-06-07 22:54:55 +01:00
Adrian.Conlon
211c75d84d
Add Z80 processor and tests.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-06-05 22:39:15 +01:00
Adrian.Conlon
46b7acb69a
Sort out shared pre-compiled header usage
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-06-04 23:37:25 +01:00
Adrian.Conlon
105032f08a
Dump of all my C++ emulators, only Intel8080 integrated so far...
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-06-04 21:38:34 +01:00