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8716035396
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78 Commits

Author SHA1 Message Date
Adrian.Conlon
8716035396 Second stage halt implementation: allow halt state to be exited by an interrupt. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-20 20:09:21 +01:00
Adrian.Conlon
57e48e389f First stage "halt" reimplementation: allow the clock to run during halt, but nothing else. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-20 19:44:57 +01:00
Adrian.Conlon
42b0fdc23d Implement DIV timer (TBC) 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-20 09:52:26 +01:00
Adrian.Conlon
75b17e47a8 Better method of enabling/disabling boot ROM. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-19 17:33:28 +01:00
Adrian.Conlon
86a4e22ae1 First stab at implementing GB timer control. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-18 19:00:10 +01:00
Adrian.Conlon
0457dffba4 Rewrite GB interrupt handling to properly document the trigger sequence. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-18 09:49:06 +01:00
Adrian.Conlon
039545bd08 Rearrange some of the shift/rotate code a little to make it easier to read. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-16 22:51:15 +01:00
Adrian.Conlon
54ab96ea38 Correct expected test results, now we know the zero flag is cleared for shift/rotate operations. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-15 23:35:27 +01:00
Adrian.Conlon
87e97eea8c Fixes rotates and shifts zero flag use (i.e. 09 - op r,r,s now runs successfully) 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-15 23:27:46 +01:00
Adrian.Conlon
2bbb021176 Correct case error in LR35902 disassembler 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-14 22:57:46 +01:00
Adrian.Conlon
6506b33436 Add comment noting GB: unique instruction. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-14 18:41:51 +01:00
Adrian.Conlon
c7dafb5f75 Another GB test corrected. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-14 18:11:19 +01:00
Adrian.Conlon
00f6c14703 Another couple of tests fixed. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-14 10:54:44 +01:00
Adrian.Conlon
a8c3c46709 Fix broken GB pop af test, to take low order flags mask. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-14 10:42:34 +01:00
Adrian.Conlon
043b7f3338 Another tested GB instruction. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-14 10:36:19 +01:00
Adrian.Conlon
e7116c5b56 Another GB test fixed. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-14 10:22:22 +01:00
Adrian.Conlon
4d322aeeb3 More GB tests fixed 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-13 23:01:52 +01:00
Adrian.Conlon
4a0d2dd930 Miscellaneous GB tests fixed. No surprises. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-13 22:51:15 +01:00
Adrian.Conlon
e6c4199b2a More miscellaneous GB tests fixed. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-13 22:11:43 +01:00
Adrian.Conlon
fb13d9fdce Correct GB: SWAP r operation. The demoted high nibble was being effectively zeroed each time. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-13 21:34:19 +01:00
Adrian.Conlon
c10dced63e Add test for GB SWAP r instructions. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-13 21:31:28 +01:00
Adrian.Conlon
6bbd7392dc LR35902 clears the half-carry flag on a CCF 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-13 19:51:42 +01:00
Adrian.Conlon
f41050b60c Add working test for 3a: LDD A,(HL) 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-13 12:52:30 +01:00
Adrian.Conlon
ca1176f0bb Fix test 32: LDD (HL),A from GB programming manual. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-13 12:02:45 +01:00
Adrian.Conlon
3355179884 Fix test for 2a: LDI A,(HL) 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-13 11:48:01 +01:00
Adrian.Conlon
a739c0eddf Use daa examples from GB programming manual for tests. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-13 11:07:01 +01:00
Adrian.Conlon
c84b757ad9 Move GB documentation to be closer to the LR35902 implementation. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-12 23:55:56 +01:00
Adrian.Conlon
dd873d9761 Start adding LR35902 tests, where wrong. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-12 23:54:53 +01:00
Adrian.Conlon
a24581caee Add comments pointing out GB specific instructions in the test input suite. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-12 15:48:15 +01:00
Adrian.Conlon
37c86fa5cf All comments in the LR35902 test input file 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-12 15:47:03 +01:00
Adrian.Conlon
0084d962c1 Unused Z80 prefixes removed from the test suite. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-12 14:49:32 +01:00
Adrian.Conlon
78e5451f93 Remove remaining Z80 -> LR35902 test translation code. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-12 14:29:12 +01:00
Adrian.Conlon
e7001b2425 Now runs the first pass of the translated Z80 tests as LR35902 style instructions 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-12 14:22:10 +01:00
Adrian.Conlon
5526892e2f Adjust for the differences between Z80 LR35902 flags (TBC!) 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-11 23:16:24 +01:00
Adrian.Conlon
42b1b7dc53 Add a one off converter for Z80 -> LR35902 fuse tests (TBC!) 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-10 23:46:41 +01:00
Adrian.Conlon
f0515ae65f First stab at a port of the fuse tests to LR35902. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-10 20:34:17 +01:00
Adrian.Conlon
7948962d70 Because of its boot room, the LR35902 needs a custom clear mechanism. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-10 20:30:37 +01:00
Adrian.Conlon
9fcb349e1f Brought the LR35902 a little closer to the Z80 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-08 13:32:51 +01:00
Adrian.Conlon
88d773708c Correct some outstanding LR35902 problems arising. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-06 22:04:13 +01:00
Adrian.Conlon
016b3bca59 Switch to a memory read/write event driven model. All tests passing. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-06 17:06:48 +01:00
Adrian.Conlon
261433bd6e Remove unneeded 16-bit operations. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-27 21:44:24 +01:00
Adrian.Conlon
569e1925ce Merge branch 'master' of https://github.com/MoleskiCoder/EightBit 2017-07-25 21:23:27 +01:00
Adrian.Conlon
b6dd48ca63 Some more small clarifications of shared processor implementation. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-25 18:56:43 +01:00
Adrian.Conlon
99c1e8e2f1 Correct 8-bit signed integer display problem in disassembler. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-22 14:07:26 +01:00
Adrian.Conlon
9a264c7c06 Bring the LR35902 and i8080 increment/decrement implementations in line with the Z80. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-22 10:23:13 +01:00
Adrian.Conlon
0a02c32695 Some things (namely shift.rotate instructions) don't need to be quite so close to the Z80 implementation. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-21 19:23:36 +01:00
Adrian.Conlon
beca76d733 Share instruction decoding mechanism between Intel derived processors. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-21 13:33:17 +01:00
Adrian.Conlon
7c3fc469a8 Bring LR35902 a little closer to the Z80 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-20 12:37:54 +01:00
Adrian.Conlon
1ee9a010b5 Finally: a working daa 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-20 10:42:18 +01:00
Adrian.Conlon
9c240b7ea8 Correct for CF not being the first bit of the flags register (why!!!!) 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-19 23:16:17 +01:00