Adrian.Conlon
dfc02c7e54
Remove pointless comment.
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Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
2017-07-24 22:02:55 +01:00
Adrian.Conlon
19966f6ad8
Z80 eight bit increment/decrement can be simplified a little
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-07-22 10:05:35 +01:00
Adrian.Conlon
beca76d733
Share instruction decoding mechanism between Intel derived processors.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-07-21 13:33:17 +01:00
Adrian.Conlon
36fbee35fb
Bring the various IntelProcessor derived processors a little closer together.
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Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
2017-07-19 13:59:28 +01:00
Adrian.Conlon
f52edaf8bc
Tidy up 16-bit add/subtract to properly use MEMPTR.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-07-03 21:42:18 +01:00
Adrian.Conlon
6af1857cb0
A few minor consistency tweaks to the i8080 and z80 processors.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-07-02 17:38:19 +01:00
Adrian.Conlon
8f57fac3ee
Use the same optimisation techniques on the Z80 header. Up to 233Mhz now.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-06-29 21:35:52 +01:00
Adrian.Conlon
954887217f
Performance mods: probably about 30% speedup: the best yet.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-06-29 00:50:34 +01:00
Adrian.Conlon
7582d65ea3
Lots more method tidy ups in search of performance.
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Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
2017-06-28 15:39:31 +01:00
Adrian.Conlon
35efc86195
Simplify the use of the REFRESH register
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Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
2017-06-27 14:02:29 +01:00
Adrian.Conlon
c803387023
A few modifications:
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1) Simplify REFRESH register handling via bit fields.
2) Use static methods in the Z80 emulator, if at all possible
3) Use a decoded opcode lookup, rather than decoding per instruction
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-06-26 23:22:32 +01:00
Adrian.Conlon
f776379e96
Share flag adjustments across implementations using templated methods.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-06-22 16:57:38 +01:00
Adrian.Conlon
67fa2a7afe
Incorporate disassembly into address profile output.
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Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
2017-06-19 17:37:41 +01:00
Adrian.Conlon
c9bf24d1fa
Tidy up register and static method access.
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Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
2017-06-19 13:53:00 +01:00
Adrian.Conlon
23108a8536
Bring performance back to par by: inlining and static flag register access, where possible.
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Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
2017-06-18 18:14:39 +01:00
Adrian.Conlon
5f288cf0e3
Some more small tidy ups.
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Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
2017-06-16 20:31:32 +01:00
Adrian.Conlon
327d391ecb
Remove another chunk of shared code. This time by ensuring the basic layout of registers is consistent.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-06-16 13:52:10 +01:00
Adrian.Conlon
71e6902aeb
Simplify and remove a bunch of code. Getting there!
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-06-15 22:21:26 +01:00
Adrian.Conlon
828e081a6e
More tidying of shareable code
2017-06-12 14:33:00 +01:00
Adrian.Conlon
0291970427
Further work on uniting the 8080 family processor family.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-06-11 21:08:40 +01:00
Adrian.Conlon
627e41bf35
Introduce an IntelProcessor base class to allow known good implementation to be shared.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-06-11 09:45:34 +01:00
Adrian.Conlon
d8977d32d3
More MEMPTR clarifications.
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This time to avoid temporary variables, in a similar manner to Z80 hardware.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-06-07 22:54:55 +01:00
Adrian.Conlon
211c75d84d
Add Z80 processor and tests.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-06-05 22:39:15 +01:00
Adrian.Conlon
105032f08a
Dump of all my C++ emulators, only Intel8080 integrated so far...
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-06-04 21:38:34 +01:00
