033969bbe3
Add profile guided optimisation to build configuration (profile/profiled)
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Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com >
2017-11-30 14:59:24 +00:00
a0f7d584b6
Correct a few warnings reported by "clang"
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Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com >
2017-11-30 14:37:18 +00:00
11062607e6
Start sharing parts of the linux build system.
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Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com >
2017-11-26 22:10:17 +00:00
c513f0cab1
GSL was too problematic when used with GCC. Removed.
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Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com >
2017-11-20 19:17:49 +00:00
67c27d4a3e
GSL + CPP core guidelines changes.
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Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com >
2017-11-18 14:29:30 +00:00
dea1847280
Unify more VS2017 build configurations
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Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com >
2017-11-12 10:38:05 +00:00
d010e3ca2f
Start incorporating CPP core guidelines (as an experiment!)
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Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com >
2017-11-10 22:41:50 +00:00
b3114ed520
Correct some possible one definition rule issues.
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Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com >
2017-11-05 14:48:15 +00:00
7a0ebb9198
Port to VS2015
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Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com >
2017-11-05 14:47:38 +00:00
c292fb552e
A whole bunch of consistency changes. No functional changes.
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Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com >
2017-11-03 22:05:01 +00:00
ff2f44bbd2
... and some more linux compatibility changes.
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Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com >
2017-10-29 20:15:49 +00:00
a134d935db
More linux compatibility
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Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com >
2017-10-29 19:53:15 +00:00
e43801ae4b
More linux compatibility updates.
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Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com >
2017-10-29 19:48:47 +00:00
899b84baa2
Linux compatibility.
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Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com >
2017-10-29 18:47:23 +00:00
b232e6992c
Get the Z80 test suite up and running again.
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Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com >
2017-10-28 13:06:10 +01:00
2c92e4d389
Updated for appveyor library location compatibility.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com >
2017-09-12 13:30:56 +01:00
cae34d61d1
Ensure the Z80 unit tests run successfully to completion.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com >
2017-09-07 01:04:09 +01:00
9b43b74c28
Rationalise some of the reset/initialise logic across pProcessor implementations.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com >
2017-09-01 16:01:40 +01:00
1eb127ed72
Add power support to processor base class.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com >
2017-08-31 12:13:00 +01:00
e70686c5de
Some more rationalisation of processor execution/stepping strategies.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com >
2017-08-30 23:17:34 +01:00
91c8855183
Share i8080 and Z80 I/O implementations.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com >
2017-08-28 21:41:10 +01:00
329fd269ed
Share some more code from the 6502 processor implementation.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com >
2017-08-28 18:52:48 +01:00
19c0b93262
Changes to the "const"ness of peek necessitate some changes.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com >
2017-08-24 11:06:23 +01:00
2c7e32aa78
First stab at implementing MBC1 support for LR35902. Not complete, but all old tests still work.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com >
2017-08-23 23:17:45 +01:00
787d9dd799
Missed an easy "assume" entry
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com >
2017-08-08 13:38:27 +01:00
ab20fc6107
Place Z80 documentation close to the Z80 emulator.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com >
2017-08-07 09:30:04 +01:00
016b3bca59
Switch to a memory read/write event driven model. All tests passing.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com >
2017-08-06 17:06:48 +01:00
b6dd48ca63
Some more small clarifications of shared processor implementation.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com >
2017-07-25 18:56:43 +01:00
dfc02c7e54
Remove pointless comment.
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Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com >
2017-07-24 22:02:55 +01:00
19966f6ad8
Z80 eight bit increment/decrement can be simplified a little
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com >
2017-07-22 10:05:35 +01:00
beca76d733
Share instruction decoding mechanism between Intel derived processors.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com >
2017-07-21 13:33:17 +01:00
d0e98fa585
Fix a missing file issue in the fuse test project.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com >
2017-07-20 12:17:37 +01:00
bbbde22322
Modify some of the Z80 daa code to better reflect bool/integer differences.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com >
2017-07-20 12:17:03 +01:00
36fbee35fb
Bring the various IntelProcessor derived processors a little closer together.
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Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com >
2017-07-19 13:59:28 +01:00
179ec7435f
Whoops: adjustment of the block output flag handling was quite wrong! Thanks fuse test suite!
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com >
2017-07-07 20:55:32 +01:00
3c0a1697fd
Fetching bytes/words and stack access are more processor specific than I thought.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com >
2017-07-07 09:27:06 +01:00
4cd2dc68e1
Correct some (but not all!) project configuration anomalies.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com >
2017-07-05 19:36:25 +01:00
0e7ad4dd01
Correct a couple of inconsistencies in the test harness.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com >
2017-07-05 17:40:16 +01:00
f52edaf8bc
Tidy up 16-bit add/subtract to properly use MEMPTR.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com >
2017-07-03 21:42:18 +01:00
6af1857cb0
A few minor consistency tweaks to the i8080 and z80 processors.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com >
2017-07-02 17:38:19 +01:00
8f57fac3ee
Use the same optimisation techniques on the Z80 header. Up to 233Mhz now.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com >
2017-06-29 21:35:52 +01:00
3439523865
Some more optimisations, up to 225Mhz now.
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Reordered if statements to give "then" case "expected"
Better use of "__assume" in switch statements
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com >
2017-06-29 21:25:58 +01:00
366c3fc601
Simplification of bitwise operators.
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Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com >
2017-06-29 12:19:22 +01:00
ea4588992d
Whoops: missing switch/break was falling into an assume(0). Caused two fuse tests to fail...
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Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com >
2017-06-29 10:18:07 +01:00
954887217f
Performance mods: probably about 30% speedup: the best yet.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com >
2017-06-29 00:50:34 +01:00
7582d65ea3
Lots more method tidy ups in search of performance.
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Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com >
2017-06-28 15:39:31 +01:00
35efc86195
Simplify the use of the REFRESH register
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Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com >
2017-06-27 14:02:29 +01:00
c803387023
A few modifications:
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1) Simplify REFRESH register handling via bit fields.
2) Use static methods in the Z80 emulator, if at all possible
3) Use a decoded opcode lookup, rather than decoding per instruction
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com >
2017-06-26 23:22:32 +01:00
a7d9cb0116
Fix an optimisation instruction ordering issue: fetchByte on both rhs/lhs.
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This caused two failing tests in the debug build of the fuse test suite.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com >
2017-06-24 21:38:42 +01:00
993fe5d2b4
Correct position of fuse test input.
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Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com >
2017-06-24 11:00:19 +01:00
Adrian Conlon
Adrian.Conlon