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216 Commits

Author SHA1 Message Date
Adrian Conlon
c105ee37bf Have a stab at sorting out processor pin handling. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-08-25 12:09:26 +01:00
Adrian Conlon
6d4223c368 Start moving towards reset being just another style of interrupt. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-08-25 01:34:30 +01:00
Adrian Conlon
2a3b0a5291 Add JMP and JSR instructions to the 6809 processor. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-08-21 18:10:38 +01:00
Adrian Conlon
15e1258f40 Rearrange the 6809 code such that I can fire memory events. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-08-19 00:55:59 +01:00
Adrian Conlon
ab1d84703b Add a skeletal 6809 processor. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-08-19 00:18:08 +01:00
Adrian Conlon
51e6adc5f4 Whoops: remove Rom.h 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-08-19 00:09:00 +01:00
Adrian Conlon
cc64e114a9 Start refactoring the processor classes to allow big/little endian processors to be specified. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-08-17 21:53:49 +01:00
Adrian Conlon
ed76038bfa More memptr adjustments 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-08-17 13:59:59 +01:00
Adrian Conlon
1abe3ae456 Adding a couple of const member accessors allows some event handlers to be marked const 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-08-12 17:08:03 +01:00
Adrian Conlon
70c70af969 Sort out some exception and member initialisation rules. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-08-11 21:19:19 +01:00
Adrian Conlon
b640da1910 Add some noexcept specifications. Just to experiment. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-08-07 23:06:15 +01:00
Adrian Conlon
e40240694f More removal of duplicated code. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-06-24 22:33:02 +01:00
Adrian Conlon
cac871cf2b Remove duplicated code (from const definitions) the performance benefit isn't worth the amount of duplicated code. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-06-24 20:58:20 +01:00
Adrian Conlon
67487b5b6e Simplify the usage of the register16_t union. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-06-16 00:55:32 +01:00
Adrian Conlon
fbf098ae00 Simplify memory event handlers and ROM recognition a little (bit of speed difference) 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-06-10 22:00:52 +01:00
Adrian Conlon
3e854c7c49 Const some more bus/processor usage, and ensure the data bus is a member, not a reference to memory. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-06-10 00:40:56 +01:00
Adrian Conlon
116f9961c4 Add a higher/lower nibble mask 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-05-25 22:36:10 +01:00
Adrian Conlon
3e87f8a191 Whoops: correct parity definition 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-05-02 03:31:05 +01:00
Adrian Conlon
0b2c1fa084 Gameboy, some random tidy ups. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-05-02 02:47:47 +01:00
Adrian Conlon
9de0f597f6 Remove some "tricksy" code from the Z80 emulator chain. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-04-14 09:39:06 +01:00
Adrian Conlon
d818095815 MEMPTR is really only a concept of Intel style processors. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-03-18 22:40:23 +00:00
Adrian Conlon
45dc274167 Get rid of wrappers for bus access: i.e. make it clearer where the bus is being read/written. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-03-10 01:53:57 +00:00
Adrian Conlon
adf506a41e Optimisation: Prefer return by value to return by reference. ~10% speed-up! 
Just watch a video by Chandler Carruth from 2015, where he talked about C++ optimisers...

Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-02-25 19:48:01 +00:00
Adrian Conlon
7f501ff29c Temporarily perhaps, reintroduce post-read and pre-write bus events (for the NES) 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-02-07 23:00:38 +00:00
Adrian Conlon
9524cf4c6b Adjust memory loaders, to allow easier usage (default arguments) 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-01-25 22:24:08 +00:00
Adrian Conlon
21bd8a06e6 Power on conditions are chip specific and *not* directly related to construction/destruction. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-01-18 17:50:15 +00:00
Adrian Conlon
29edc46966 Simplify some MEMPTR usage in Intel processors. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-01-10 23:08:14 +00:00
Adrian Conlon
108f66632e Performance: watch out for unnecessary virtualised methods. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2018-01-06 17:13:02 +00:00
Adrian Conlon
d4782a66db Some small changes for NES support: hopefully not broken anything! 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-12-26 22:46:16 +00:00
Adrian Conlon
637c0c68fa Correct a couple of merge issues. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-12-12 23:12:45 +00:00
Adrian Conlon
c8dd6e7267 Merge branch 'master' of https://github.com/MoleskiCoder/EightBit 
# Conflicts:
#	inc/EightBitCompilerDefinitions.h
 2017-12-12 23:08:34 +00:00
Adrian Conlon
c5b7b06e59 Whoops: correct macro expansion. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-12-12 23:05:54 +00:00
Adrian Conlon
697bfb636d A more succinct definition of the LR35902 interrupt mechanism. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-12-12 22:29:37 +00:00
Adrian Conlon
1edabd79f3 More pinout oriented method of executing instructions (especially interrupts) 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-12-10 21:41:48 +00:00
Adrian Conlon
4f5e231dc4 Merge branch 'master' of https://github.com/MoleskiCoder/EightBit 2017-12-02 23:55:44 +00:00
Adrian Conlon
7e3957d4db Rewrite i8080 interrupts to be more closely related to the hardware. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-12-02 23:50:59 +00:00
Adrian Conlon
def14493cb Allow fallback for where intrinsics aren't available. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-12-02 19:01:07 +00:00
Adrian Conlon
d70f6b375b Ensure each header file has a newline on its own at the end of each file. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-11-30 23:19:17 +00:00
Adrian Conlon
12385dcc6f More clang warnings corrected. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-11-30 23:15:40 +00:00
Adrian Conlon
4b2d84dba3 Whoops: missed clang warning. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-11-30 16:55:10 +00:00
Adrian Conlon
a0f7d584b6 Correct a few warnings reported by "clang" 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-11-30 14:37:18 +00:00
Adrian Conlon
f50c83ad36 Whoops: missed GCC problem. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-11-20 20:54:17 +00:00
Adrian Conlon
c513f0cab1 GSL was too problematic when used with GCC. Removed. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-11-20 19:17:49 +00:00
Adrian Conlon
67c27d4a3e GSL + CPP core guidelines changes. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-11-18 14:29:30 +00:00
Adrian Conlon
47446a617d the "run" method is probably better off not being overridden. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-11-11 15:50:55 +00:00
Adrian Conlon
0b6ef3d4dd VS2017 and CPP core guidelines updates 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-11-11 15:13:26 +00:00
Adrian Conlon
d010e3ca2f Start incorporating CPP core guidelines (as an experiment!) 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-11-10 22:41:50 +00:00
Adrian Conlon
8143f8a506 Try to correct "one definition rule" problems: 
1) No forward declarations
2) No virtual methods defined inline.

Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-11-05 12:47:42 +00:00
Adrian Conlon
926ac48224 Move to VS2017 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-11-04 23:15:55 +00:00
Adrian Conlon
c292fb552e A whole bunch of consistency changes. No functional changes. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-11-03 22:05:01 +00:00
Adrian Conlon
a22e59546b Tidy the gameboy core a little. Mainly by moving the execution loops into the bus class. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-10-24 00:04:13 +01:00
Adrian Conlon
daa8eabb49 Merge branch 'master' of https://github.com/MoleskiCoder/EightBit 2017-10-22 21:37:21 +01:00
Adrian Conlon
fa03e8dc55 Simplify I/O port event handling. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-10-22 21:31:20 +01:00
Adrian Conlon
90b0673259 Correct a couple of header file issues in the base EightBit library 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-10-22 21:24:28 +01:00
Adrian Conlon
10913bf1b8 Remove some unused signals. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2017-10-01 22:22:25 +01:00
Adrian.Conlon
b445457b37 Fire pre/post memory read/write events 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-09-14 15:00:57 +01:00
Adrian.Conlon
a77e57e5fc Add pre/post read/write memory events. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-09-13 23:12:47 +01:00
Adrian.Conlon
b0923bd472 (Coverity) Initialise Bus variables in constructor. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-09-07 13:45:16 +01:00
Adrian.Conlon
0665de5951 Make the base BUS architecture a little easier to work with. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-09-07 00:53:22 +01:00
Adrian.Conlon
64b7335a79 Attempted move to a "BUS" oriented memory architecture (TBC!) 
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
 2017-09-06 13:22:23 +01:00
Adrian.Conlon
da806bddcb Tidy some more Windows/Linux compatibility issues. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-09-03 21:30:46 +01:00
Adrian.Conlon
640b2be670 Parts of the EightBit library become linux compatible (TBC!) 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-09-03 12:11:14 +01:00
Adrian.Conlon
57cfd79c44 Tidy header file usage a little. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-09-01 16:41:50 +01:00
Adrian.Conlon
9b43b74c28 Rationalise some of the reset/initialise logic across pProcessor implementations. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-09-01 16:01:40 +01:00
Adrian.Conlon
1eb127ed72 Add power support to processor base class. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-31 12:13:00 +01:00
Adrian.Conlon
e70686c5de Some more rationalisation of processor execution/stepping strategies. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-30 23:17:34 +01:00
Adrian.Conlon
ec15a2c90c Correct SP arithmetic methods: All Blargg CPU tests now pass. Hurrah! 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-28 23:04:25 +01:00
Adrian.Conlon
91c8855183 Share i8080 and Z80 I/O implementations. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-28 21:41:10 +01:00
Adrian.Conlon
d710a28526 More consolidation of instruction implementations. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-28 21:18:08 +01:00
Adrian.Conlon
329fd269ed Share some more code from the 6502 processor implementation. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-28 18:52:48 +01:00
Adrian.Conlon
59e9adf57c Share more of push/pop implementation across processors. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-28 13:19:17 +01:00
Adrian.Conlon
9964070b85 Refactor to allow peek/poke/reference to share a common implementation as much as possible. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-24 11:28:01 +01:00
Adrian.Conlon
448ee2f09f Refactor the MBC implementation to allow a single point of definition. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-24 10:28:31 +01:00
Adrian.Conlon
2c7e32aa78 First stab at implementing MBC1 support for LR35902. Not complete, but all old tests still work. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-23 23:17:45 +01:00
Adrian.Conlon
8716035396 Second stage halt implementation: allow halt state to be exited by an interrupt. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-20 20:09:21 +01:00
Adrian.Conlon
7948962d70 Because of its boot room, the LR35902 needs a custom clear mechanism. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-10 20:30:37 +01:00
Adrian.Conlon
016b3bca59 Switch to a memory read/write event driven model. All tests passing. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-08-06 17:06:48 +01:00
Adrian.Conlon
b6dd48ca63 Some more small clarifications of shared processor implementation. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-25 18:56:43 +01:00
Adrian.Conlon
beca76d733 Share instruction decoding mechanism between Intel derived processors. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-21 13:33:17 +01:00
Adrian.Conlon
99e3454527 Memory locking is dependent on the GB hardware, not the size of the program, so allow lock ranges to be manually specified. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-18 21:40:29 +01:00
Adrian.Conlon
35def4184a Start adding enough infrastructure to support memory mapped IO on LR35902. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-18 00:13:41 +01:00
Adrian.Conlon
017b2a6442 Tidy up memory event handling to make it a bit easier to verify read/write events. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-17 21:00:05 +01:00
Adrian.Conlon
4f491f110e Make the 6502 a little more compatible with other processor implementations. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-17 13:46:06 +01:00
Adrian.Conlon
8c81a27224 "Modernise" the 6502 emulator a little. Not complete, but does successfully complete Klaus Dormann tests. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-11 21:34:01 +01:00
Adrian.Conlon
3001a97128 Don't bother wiring up memory events that the 6502 doesn't need (I think!) 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-08 09:41:07 +01:00
Adrian.Conlon
8256d97b60 Modified to work with my builds of the Klaus Dormann 6502 test suite. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-08 01:04:20 +01:00
Adrian.Conlon
3c0a1697fd Fetching bytes/words and stack access are more processor specific than I thought. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-07 09:27:06 +01:00
Adrian.Conlon
f970c45005 Get the loop exit conditions worked out. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-06 21:32:52 +01:00
Adrian.Conlon
d4b133e9ac Show cycles per second as MHz 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-05 19:15:58 +01:00
Adrian.Conlon
6db32ae7c5 Small consistency change in the 8-bit memory model. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-05 17:44:47 +01:00
Adrian.Conlon
0e7ad4dd01 Correct a couple of inconsistencies in the test harness. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-05 17:40:16 +01:00
Adrian.Conlon
983639d530 Correct a couple of header issues in the test harness. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-04 13:00:23 +01:00
Adrian.Conlon
88d3e4fd47 Initial stab at getting MOS6502 imported to the EightBit library. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-02 22:03:33 +01:00
Adrian.Conlon
6af1857cb0 A few minor consistency tweaks to the i8080 and z80 processors. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-07-02 17:38:19 +01:00
Adrian.Conlon
954887217f Performance mods: probably about 30% speedup: the best yet. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-29 00:50:34 +01:00
Adrian.Conlon
c803387023 A few modifications: 
1) Simplify REFRESH register handling via bit fields.
2) Use static methods in the Z80 emulator, if at all possible
3) Use a decoded opcode lookup, rather than decoding per instruction

Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-26 23:22:32 +01:00
Adrian.Conlon
d22b695682 Modify test harness to show host CPU cycle efficiency. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-25 23:48:15 +01:00
Adrian.Conlon
f776379e96 Share flag adjustments across implementations using templated methods. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-22 16:57:38 +01:00
Adrian.Conlon
23b5a5d579 Tidy the test harness a little. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-22 10:16:02 +01:00
Adrian.Conlon
8927f412d4 Use a shared test harness. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-21 23:55:25 +01:00
Adrian.Conlon
052df61250 Remove get/getWord and set/setWord from memory class. Just use address and data lines on the memory. 
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
 2017-06-20 14:09:44 +01:00
Adrian.Conlon
a4f8770eb0 Correct a couple of small compilation issues. 
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
 2017-06-19 18:08:13 +01:00
Adrian.Conlon
c9bf24d1fa Tidy up register and static method access. 
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
 2017-06-19 13:53:00 +01:00
Adrian.Conlon
23108a8536 Bring performance back to par by: inlining and static flag register access, where possible. 
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
 2017-06-18 18:14:39 +01:00
Adrian.Conlon
327d391ecb Remove another chunk of shared code. This time by ensuring the basic layout of registers is consistent. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-16 13:52:10 +01:00
Adrian.Conlon
71e6902aeb Simplify and remove a bunch of code. Getting there! 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-15 22:21:26 +01:00
Adrian.Conlon
66d3a5ae29 Couple of small simplifications. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-13 23:43:21 +01:00
Adrian.Conlon
828e081a6e More tidying of shareable code 2017-06-12 14:33:00 +01:00
Adrian.Conlon
0291970427 Further work on uniting the 8080 family processor family. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-11 21:08:40 +01:00
Adrian.Conlon
627e41bf35 Introduce an IntelProcessor base class to allow known good implementation to be shared. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-11 09:45:34 +01:00
Adrian.Conlon
b1aa523dcc Small simplifications to base Processor class. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-10 12:42:55 +01:00
Adrian.Conlon
f3fe475d44 Implement enough changes to build LR35902 2017-06-09 10:23:51 +01:00
Adrian.Conlon
d8977d32d3 More MEMPTR clarifications. 
This time to avoid temporary variables, in a similar manner to Z80 hardware.

Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-07 22:54:55 +01:00
Adrian.Conlon
211c75d84d Add Z80 processor and tests. 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-05 22:39:15 +01:00
Adrian.Conlon
46b7acb69a Sort out shared pre-compiled header usage 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-04 23:37:25 +01:00
Adrian.Conlon
105032f08a Dump of all my C++ emulators, only Intel8080 integrated so far... 
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
 2017-06-04 21:38:34 +01:00