Commit Graph

69 Commits

Author SHA1 Message Date
Adrian Conlon
ff2f44bbd2 ... and some more linux compatibility changes.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
2017-10-29 20:15:49 +00:00
Adrian Conlon
a134d935db More linux compatibility
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
2017-10-29 19:53:15 +00:00
Adrian Conlon
e43801ae4b More linux compatibility updates.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
2017-10-29 19:48:47 +00:00
Adrian Conlon
899b84baa2 Linux compatibility.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
2017-10-29 18:47:23 +00:00
Adrian Conlon
b232e6992c Get the Z80 test suite up and running again.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
2017-10-28 13:06:10 +01:00
Adrian.Conlon
2c92e4d389 Updated for appveyor library location compatibility.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-09-12 13:30:56 +01:00
Adrian.Conlon
cae34d61d1 Ensure the Z80 unit tests run successfully to completion.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-09-07 01:04:09 +01:00
Adrian.Conlon
9b43b74c28 Rationalise some of the reset/initialise logic across pProcessor implementations.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-09-01 16:01:40 +01:00
Adrian.Conlon
1eb127ed72 Add power support to processor base class.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-08-31 12:13:00 +01:00
Adrian.Conlon
e70686c5de Some more rationalisation of processor execution/stepping strategies.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-08-30 23:17:34 +01:00
Adrian.Conlon
91c8855183 Share i8080 and Z80 I/O implementations.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-08-28 21:41:10 +01:00
Adrian.Conlon
329fd269ed Share some more code from the 6502 processor implementation.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-08-28 18:52:48 +01:00
Adrian.Conlon
19c0b93262 Changes to the "const"ness of peek necessitate some changes.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-08-24 11:06:23 +01:00
Adrian.Conlon
2c7e32aa78 First stab at implementing MBC1 support for LR35902. Not complete, but all old tests still work.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-08-23 23:17:45 +01:00
Adrian.Conlon
787d9dd799 Missed an easy "assume" entry
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-08-08 13:38:27 +01:00
Adrian.Conlon
ab20fc6107 Place Z80 documentation close to the Z80 emulator.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-08-07 09:30:04 +01:00
Adrian.Conlon
016b3bca59 Switch to a memory read/write event driven model. All tests passing.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-08-06 17:06:48 +01:00
Adrian.Conlon
b6dd48ca63 Some more small clarifications of shared processor implementation.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-07-25 18:56:43 +01:00
Adrian.Conlon
dfc02c7e54 Remove pointless comment.
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
2017-07-24 22:02:55 +01:00
Adrian.Conlon
19966f6ad8 Z80 eight bit increment/decrement can be simplified a little
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-07-22 10:05:35 +01:00
Adrian.Conlon
beca76d733 Share instruction decoding mechanism between Intel derived processors.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-07-21 13:33:17 +01:00
Adrian.Conlon
d0e98fa585 Fix a missing file issue in the fuse test project.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-07-20 12:17:37 +01:00
Adrian.Conlon
bbbde22322 Modify some of the Z80 daa code to better reflect bool/integer differences.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-07-20 12:17:03 +01:00
Adrian.Conlon
36fbee35fb Bring the various IntelProcessor derived processors a little closer together.
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
2017-07-19 13:59:28 +01:00
Adrian.Conlon
179ec7435f Whoops: adjustment of the block output flag handling was quite wrong! Thanks fuse test suite!
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-07-07 20:55:32 +01:00
Adrian.Conlon
3c0a1697fd Fetching bytes/words and stack access are more processor specific than I thought.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-07-07 09:27:06 +01:00
Adrian.Conlon
4cd2dc68e1 Correct some (but not all!) project configuration anomalies.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-07-05 19:36:25 +01:00
Adrian.Conlon
0e7ad4dd01 Correct a couple of inconsistencies in the test harness.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-07-05 17:40:16 +01:00
Adrian.Conlon
f52edaf8bc Tidy up 16-bit add/subtract to properly use MEMPTR.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-07-03 21:42:18 +01:00
Adrian.Conlon
6af1857cb0 A few minor consistency tweaks to the i8080 and z80 processors.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-07-02 17:38:19 +01:00
Adrian.Conlon
8f57fac3ee Use the same optimisation techniques on the Z80 header. Up to 233Mhz now.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-06-29 21:35:52 +01:00
Adrian.Conlon
3439523865 Some more optimisations, up to 225Mhz now.
Reordered if statements to give "then" case "expected"
Better use of "__assume" in switch statements

Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-06-29 21:25:58 +01:00
Adrian.Conlon
366c3fc601 Simplification of bitwise operators.
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
2017-06-29 12:19:22 +01:00
Adrian.Conlon
ea4588992d Whoops: missing switch/break was falling into an assume(0). Caused two fuse tests to fail...
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
2017-06-29 10:18:07 +01:00
Adrian.Conlon
954887217f Performance mods: probably about 30% speedup: the best yet.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-06-29 00:50:34 +01:00
Adrian.Conlon
7582d65ea3 Lots more method tidy ups in search of performance.
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
2017-06-28 15:39:31 +01:00
Adrian.Conlon
35efc86195 Simplify the use of the REFRESH register
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
2017-06-27 14:02:29 +01:00
Adrian.Conlon
c803387023 A few modifications:
1) Simplify REFRESH register handling via bit fields.
2) Use static methods in the Z80 emulator, if at all possible
3) Use a decoded opcode lookup, rather than decoding per instruction

Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-06-26 23:22:32 +01:00
Adrian.Conlon
a7d9cb0116 Fix an optimisation instruction ordering issue: fetchByte on both rhs/lhs.
This caused two failing tests in the debug build of the fuse test suite.

Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-06-24 21:38:42 +01:00
Adrian.Conlon
993fe5d2b4 Correct position of fuse test input.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-06-24 11:00:19 +01:00
Adrian.Conlon
af375ab10f Some more shared code.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-06-22 19:00:53 +01:00
Adrian.Conlon
f776379e96 Share flag adjustments across implementations using templated methods.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-06-22 16:57:38 +01:00
Adrian.Conlon
529aa1bd21 Tidy profile output
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-06-22 10:27:19 +01:00
Adrian.Conlon
8927f412d4 Use a shared test harness.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-06-21 23:55:25 +01:00
Adrian.Conlon
5a3713fc8a First stab at efficiency timing support for 8080 and z80 test runners.
Signed-off-by: Adrian.Conlon <adrian.conlon@gmail.com>
2017-06-21 21:05:07 +01:00
Adrian.Conlon
a4f8770eb0 Correct a couple of small compilation issues.
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
2017-06-19 18:08:13 +01:00
Adrian.Conlon
67fa2a7afe Incorporate disassembly into address profile output.
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
2017-06-19 17:37:41 +01:00
Adrian.Conlon
c7e65f5447 Consistency changes to the projects.
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
2017-06-19 13:53:37 +01:00
Adrian.Conlon
c9bf24d1fa Tidy up register and static method access.
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
2017-06-19 13:53:00 +01:00
Adrian.Conlon
23108a8536 Bring performance back to par by: inlining and static flag register access, where possible.
Signed-off-by: Adrian.Conlon <adrian.conlon@arup.com>
2017-06-18 18:14:39 +01:00