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  • b3faae34ae Correct a couple of problematic changes picked up by fuse test Adrian Conlon 2018-10-28 09:42:04 +0000
  • 99692ce6c7 Refactor MC6850 for C++14/17 updates Adrian Conlon 2018-10-27 21:58:23 +0100
  • 1a317c7907 C++14/17 refactoring for MC6809 Adrian Conlon 2018-10-27 21:55:54 +0100
  • 015071fcfb Tidy up GameBoy processor (LR35902) with respect to C++14/17 Adrian Conlon 2018-10-27 19:23:02 +0100
  • b9ca27feb3 Refactor the Intel 8080 core for C++17/14 Adrian Conlon 2018-10-27 18:51:30 +0100
  • fac2da9ac4 Start refactoring CPU cores to use C++17/14 features. (This commit covers the 6502 and Z80) Adrian Conlon 2018-10-27 18:41:55 +0100
  • 62f3cd717b First set of C++17/14 changes to the core library Adrian Conlon 2018-10-27 17:30:23 +0100
  • 8dbb3eafec Switch to C++17 standard in all EightBit projects. Adrian Conlon 2018-10-27 14:28:14 +0100
  • b50d21965d Addr support for the RTS/CTS and IRQ pins to the MC6850 chip emulation Adrian Conlon 2018-10-23 00:01:33 +0100
  • 4bfb264380 Simplify chip pin level matching a little. Adrian Conlon 2018-10-21 19:42:20 +0100
  • 3aa5b4bb91 Tidy the MC6850 transmit/receive sequence to be a little easier to read. Adrian Conlon 2018-10-21 18:09:23 +0100
  • 4840c238d6 Set configuration default to *not* exit early. Adrian Conlon 2018-10-21 18:07:42 +0100
  • 806251bf6f Whoops: Remove extra blank line. Adrian Conlon 2018-10-21 18:07:08 +0100
  • 54e0dcfe36 Move board termination and cycle count etc. into the configuration class. Adrian Conlon 2018-10-21 10:28:33 +0100
  • 4d09da1541 Reuse standard 6809/6850 chip/bus wiring Adrian Conlon 2018-10-20 22:54:10 +0100
  • 1b2ddd8843 Don't expose the bus via the CPU any more: if a component needs the bus, it should be prepared to hold a reference to it. Adrian Conlon 2018-10-20 20:52:41 +0100
  • 9b0cc4542f Tidy MC6809 test board/device access. Adrian Conlon 2018-10-20 16:57:32 +0100
  • dbc3e192d7 More sharing of common implementation on the MC6809. Adrian Conlon 2018-10-18 22:50:54 +0100
  • 83497b0b9e Share some implementation details on the MC6809, where possible. Somewhat closer to how I imagine the hardware is implemented... Adrian Conlon 2018-10-18 22:25:52 +0100
  • 966a07b018 Reuse pul/psh definition to simplify entire register set save/restore code. Adrian Conlon 2018-10-17 20:42:03 +0100
  • 4b2f8e3599 Correct "LE" definition to at least match the MC6809 documentation. Adrian Conlon 2018-10-17 20:39:58 +0100
  • 8c8438f819 Tidy the test code formatting a little Adrian Conlon 2018-10-14 23:39:37 +0100
  • 4e48f4a5a0 Slightly simplify half-carry evaluation. Adrian Conlon 2018-10-14 23:18:13 +0100
  • 140e87485c Whoops: Correct dodgy CMP test. That explains why I never understood why it was failing! Adrian Conlon 2018-10-14 21:26:33 +0100
  • 9d71c78338 DEC/INC don't adjust carry flags Adrian Conlon 2018-10-14 21:19:37 +0100
  • 0c07d39250 Share (hopefully!) correct overflow implementations Adrian Conlon 2018-10-14 21:19:03 +0100
  • 707a742899 Not complete, but this gets large chunks of the MC6809 addition and subtraction parts of the emulator working correctly Adrian Conlon 2018-10-14 20:40:20 +0100
  • 337e35ca1b Use the newly added CPU pokeWord method. Adrian Conlon 2018-10-14 20:39:09 +0100
  • 769c65394b The extra _getch isn't required as I fix the MC6809 CPU emulation. Adrian Conlon 2018-10-14 20:38:07 +0100
  • 12dc90c064 Add lots of tests, mainly covering addition and subtraction. Shows quite a few problems... Adrian Conlon 2018-10-14 10:06:47 +0100
  • 7e527ff093 Add Processor::pokeWord to define an endian specific 16-bit word write. Adrian Conlon 2018-10-14 10:05:43 +0100
  • 9445e7d1c4 Add test for CLRA implied Adrian Conlon 2018-10-07 11:04:22 +0100
  • 9296eaf954 Add test for BITA immediate. Adrian Conlon 2018-10-07 10:55:30 +0100
  • cf32f37fc3 Add test for ASRA inherent. And fix resulting bugs exposed! Adrian Conlon 2018-10-07 10:48:27 +0100
  • f2b9ab0814 Add test for ASLA inherent. Adrian Conlon 2018-10-07 10:32:26 +0100
  • 7719c8e875 Add test for ANDA immediate Adrian Conlon 2018-10-07 10:08:12 +0100
  • 1f4a84b803 Add test for ADDA immediate. Seems to be working. Adrian Conlon 2018-10-07 09:47:10 +0100
  • 5dc185866e Add a test for ADCA immediate. Half carry and overflow flags incorrect! Adrian Conlon 2018-10-07 09:14:30 +0100
  • 7e57efd4cd Modification of unit test comments: no functional modification. Adrian Conlon 2018-10-06 23:54:33 +0100
  • fe05d468d6 Start adding MC6809 unit tests for each instruction. Just ABX, so far Adrian Conlon 2018-10-06 23:52:39 +0100
  • 8048165aab Reorder the output of the M6850 status dump, so it more easily matches the bit order most -> least significant. Adrian Conlon 2018-10-03 20:16:59 +0100
  • 0c174afc02 More MC6809 disassembly corrections: tabs and pshu/s puls/u stack order. Adrian Conlon 2018-10-03 20:15:44 +0100
  • f6cd8a4277 Properly disassemble MC6809 PULS/PULU PSHS/PSHU instructions to show registers. Adrian Conlon 2018-10-02 22:35:31 +0100
  • f58e3ded83 Use corrected MC6850 in MC6809 test board. Working a little better now. Adrian Conlon 2018-09-30 23:10:03 +0100
  • 042e066a0c Correct status handling in the MC6850, and improve documentation. Adrian Conlon 2018-09-30 23:07:07 +0100
  • 8ea7bf5d68 Refactoring on the MC6850 and associated test board code. Adrian Conlon 2018-09-29 14:31:50 +0100
  • 8d3551e681 Refactor bit set/get routines from processor class to lower level chip class. Adrian Conlon 2018-09-29 14:08:44 +0100
  • de5a9963e0 More MC6850 updates Adrian Conlon 2018-09-29 10:06:02 +0100
  • f6bd871757 Whoops: correct 6809 stack pointer increment/decrement order Adrian Conlon 2018-09-29 10:02:53 +0100
  • 861fc28bba Wire up the MC6850 events to the board Adrian Conlon 2018-09-25 23:57:20 +0100
  • df7c7904f4 Whoops: correct a small layout (tabs) issue. Adrian Conlon 2018-09-25 23:56:28 +0100
  • 4f567c75f9 Probably doesn't work, but this is another style of MC6850 event handling Adrian Conlon 2018-09-25 23:55:14 +0100
  • 9ab075d0f6 Incorporate the concepts of transmission and receipt into the events for the MC6850 (TBC) Adrian Conlon 2018-09-24 08:29:11 +0100
  • d77c2a1e9d Add more of the MC6850 internals. Adrian Conlon 2018-09-23 20:31:55 +0100
  • b3faa0bb2e Wire the MC6850 chip into the MC6809 test code. Adrian Conlon 2018-09-23 13:14:10 +0100
  • 754fc8e6a3 Refactor the processor class to give us a "Chip" class that gives up pin levels and power. Adrian Conlon 2018-09-23 13:10:58 +0100
  • 91349eafa4 Updated MC6850 documentation. Bit more searchable... Adrian Conlon 2018-09-23 10:19:39 +0100
  • be2f5abdb5 Correct a couple of small layout issues in the MC6850 code Adrian Conlon 2018-09-23 00:08:16 +0100
  • e2f69b1dc8 Start adding support for the Motorola serial device, the MC6850 ACIA (most incomplete!) Adrian Conlon 2018-09-22 23:11:13 +0100
  • 30ac7dc268 Whoops: missed movement of stdafx.h for MC6809 Adrian Conlon 2018-09-22 23:09:10 +0100
  • d45401d9b1 Tidy a couple of MC6809 niggles: Adrian Conlon 2018-09-22 10:54:05 +0100
  • 7c03521025 Refactor plsu/s pshu/s to share code more easily Adrian Conlon 2018-09-21 00:28:08 +0100
  • 6bb8118c7f Add miscellaneous documentation and test gubbins Adrian Conlon 2018-09-21 00:17:25 +0100
  • 7adefd380a Sort a bunch of missing argument const specifications. Adrian Conlon 2018-09-21 00:16:00 +0100
  • 9e91d2adad Plug the 8K hole in the address space of the Grant Searle SBC with 0xff (held high) Adrian Conlon 2018-09-16 19:49:52 +0100
  • 54bb9743be Correct 10/11 opcode prefix disassembly on the 6809 processor. Adrian Conlon 2018-09-16 17:56:55 +0100
  • 2d93087e5f Correct the hex loader, using the new mapping mechanism. Adrian Conlon 2018-09-16 17:54:53 +0100
  • fe3794e011 Simplify register16_t usage a little. Adrian Conlon 2018-09-16 12:00:29 +0100
  • 6256d0bf8d Correct compilation warnings. Adrian Conlon 2018-09-15 18:33:33 +0100
  • 7d840f1a42 Modifying the manner in which memory is mapped, allows a fairly clean mechanism for loading Intel "hex" files. Adrian Conlon 2018-09-15 14:35:59 +0100
  • a9adde6ea5 Correct 6809 CLR flag handling. Adrian Conlon 2018-08-30 01:37:46 +0100
  • 8e0c1ebcde Modify the 6809 disassembler a little to give output more like xroar (for comparison purposes) Adrian Conlon 2018-08-30 01:37:09 +0100
  • c85176431b Refactor 6809 jsr/rts code a little. No functional changes. Adrian Conlon 2018-08-29 14:03:24 +0100
  • 97272d650d Simplify processor bus access a little by further allowing register16_t address access. Adrian Conlon 2018-08-29 13:52:25 +0100
  • 46b140dda1 Correct issues with the 6809 indirect indexed addressing mode. Adrian Conlon 2018-08-29 13:25:19 +0100
  • b0addc5100 Correct a couple of minor issues in the 6809 disassembler Adrian Conlon 2018-08-28 18:28:00 +0100
  • 52ad4e6996 Tidied the 6809 disassembler a little. Adrian Conlon 2018-08-28 16:46:15 +0100
  • 3dfea03b2e In theory, this finishes the 6809 disassembler. Adrian Conlon 2018-08-28 13:56:06 +0100
  • 67b5fe1658 Add two more pieces of 6809 documentation Adrian Conlon 2018-08-28 08:30:56 +0100
  • c22b3fca3b Correct 6809 disassembly prefix issue. Adrian Conlon 2018-08-28 08:18:00 +0100
  • 837ac495ab Couple more 6809 disassembly instructions added, up to the point of an instruction oddity... Adrian Conlon 2018-08-27 23:50:18 +0100
  • ce9738eb4b Fill out more 6809 disassembly + fix a bug in the TFR/EXG instructions: muddled up 8/16 bit transfers. Adrian Conlon 2018-08-27 22:48:08 +0100
  • fbc743a608 6809 Disassembly: Addressing mode: immediate byte added. More instructions decoded. Adrian Conlon 2018-08-27 13:11:43 +0100
  • dfc4c49454 Correct 5-bit sign extension on the 6809 processor. Allows CLR 5-bit offset indexed disassembly to work correctly. Adrian Conlon 2018-08-27 12:57:44 +0100
  • 2f632cdaf5 Another 6809 instruction and addressing mode disassembly added. Adrian Conlon 2018-08-27 11:29:15 +0100
  • a8cc289149 Whoops: The "Bus" class *really* isn't allowed to know the "endianness" of the attached processor! Adrian Conlon 2018-08-27 11:27:33 +0100
  • a5e51f7140 Simplify the 6809 disassembler usage a little. Adrian Conlon 2018-08-27 10:43:12 +0100
  • 974d5fbd14 Only show disassembled output, when there is actually something to show (fixes 6809 startup/interrupt sequence) Adrian Conlon 2018-08-27 10:25:15 +0100
  • 983e2a5eb2 Start fleshing out the 6809 disassembler. Adrian Conlon 2018-08-27 01:19:22 +0100
  • 87b7295fe8 Remove unused "Resource" folder from the 6809 test project Adrian Conlon 2018-08-27 01:18:49 +0100
  • 2d6b9d9ecf Add some more 6809 documentation. Adrian Conlon 2018-08-26 19:10:04 +0100
  • e88cbc269b Add a skeletal half way house between a 6809 tester and a CoCo 2 emulator. Adrian Conlon 2018-08-26 19:09:34 +0100
  • a22c5a5c78 Add skeletal disassembler to the 6809 processor. Adrian Conlon 2018-08-26 19:08:07 +0100
  • 735f70e717 Remove a couple of unused headers from the 6502 processor. Adrian Conlon 2018-08-26 19:06:00 +0100
  • 50826d36b6 Add a little pin documentation to the 6809 processor. Adrian Conlon 2018-08-26 19:02:41 +0100
  • dc6803a5b6 Whoops: powerOn should always be public (6809) Adrian Conlon 2018-08-26 17:27:50 +0100
  • ef5e325b6d Tidy 6809 header file usage a little. Adrian Conlon 2018-08-26 13:07:26 +0100
  • c03d8488b5 Allow memory peek as a const operation. Adrian Conlon 2018-08-26 13:06:05 +0100
  • 8823bb6610 Refactor the *EndianProcessor classes, such that their implementation is no longer in header files. Adrian Conlon 2018-08-25 22:51:56 +0100
  • 3a4235f651 Whoops: The NMI line needs to be powered on by individual processors now it's no longer part of the Processor base class. Adrian Conlon 2018-08-25 22:50:18 +0100