diff --git a/EightBit/Processor.cs b/EightBit/Processor.cs index 538fd15..bfdba75 100644 --- a/EightBit/Processor.cs +++ b/EightBit/Processor.cs @@ -220,10 +220,14 @@ namespace EightBit protected virtual byte BusRead() => this.Bus.Read(); // N.B. Should be the only real call into the "Bus.Read" code. + protected virtual void IncrementPC() => ++this.PC.Word; + + protected virtual void DecrementPC() => --this.PC.Word; + protected virtual byte FetchByte() { this.Bus.Address.Assign(this.PC); - this.PC.Word++; + IncrementPC(); return this.MemoryRead(); } diff --git a/Intel8080/Intel8080.cs b/Intel8080/Intel8080.cs index 73c8563..ec79ce9 100644 --- a/Intel8080/Intel8080.cs +++ b/Intel8080/Intel8080.cs @@ -13,8 +13,6 @@ namespace Intel8080 : base(bus) { this.ports = ports; - this.LoweredHALT += this.Intel8080_LoweredHALT; - this.RaisedHALT += this.Intel8080_RaisedHALT; } private readonly Register16 af = new(); @@ -91,16 +89,6 @@ namespace Intel8080 } } - private void Intel8080_RaisedHALT(object? sender, EventArgs e) - { - ++this.PC.Word; // Release the PC from HALT instruction - } - - private void Intel8080_LoweredHALT(object? sender, EventArgs e) - { - --this.PC.Word; // Keep the PC on the HALT instruction (i.e. executing NOP) - } - private int Sign() { diff --git a/LR35902/LR35902.cs b/LR35902/LR35902.cs index a30d6d1..8ea3ff9 100644 --- a/LR35902/LR35902.cs +++ b/LR35902/LR35902.cs @@ -669,7 +669,6 @@ namespace LR35902 { this.LowerHALT(); // Exception (replaces LD (HL), (HL)) this.TickMachine(2); - //this.PC.Word++; } else { diff --git a/M6502/Core.cs b/M6502/Core.cs index 5c96cf3..82370fb 100644 --- a/M6502/Core.cs +++ b/M6502/Core.cs @@ -664,7 +664,7 @@ namespace M6502 protected void ImmediateAddress() { this.Bus.Address.Assign(this.PC); - ++this.PC.Word; + this.IncrementPC(); } protected void AbsoluteAddress() => this.FetchWordAddress(); diff --git a/MC6809/MC6809.cs b/MC6809/MC6809.cs index ade14a2..344e223 100644 --- a/MC6809/MC6809.cs +++ b/MC6809/MC6809.cs @@ -161,13 +161,11 @@ namespace EightBit public void Halt() { - --this.PC.Word; this.LowerHALT(); } public void Proceed() { - ++this.PC.Word; this.RaiseHALT(); } diff --git a/Z80/Z80.cs b/Z80/Z80.cs index 1b380af..2184952 100644 --- a/Z80/Z80.cs +++ b/Z80/Z80.cs @@ -1021,9 +1021,9 @@ namespace Z80 case 6: // LDIR if (this.LDIR()) { - --this.PC.Word; + this.DecrementPC(); this.MEMPTR.Assign(this.PC); - --this.PC.Word; + this.DecrementPC(); } this.Tick(5); @@ -1031,9 +1031,9 @@ namespace Z80 case 7: // LDDR if (this.LDDR()) { - --this.PC.Word; + this.DecrementPC(); this.MEMPTR.Assign(this.PC); - --this.PC.Word; + this.DecrementPC(); } this.Tick(5); @@ -1055,9 +1055,9 @@ namespace Z80 case 6: // CPIR if (this.CPIR()) { - --this.PC.Word; + this.DecrementPC(); this.MEMPTR.Assign(this.PC); - --this.PC.Word; + this.DecrementPC(); this.Tick(5); } @@ -1065,9 +1065,9 @@ namespace Z80 case 7: // CPDR if (this.CPDR()) { - --this.PC.Word; + this.DecrementPC(); this.MEMPTR.Assign(this.PC); - --this.PC.Word; + this.DecrementPC(); this.Tick(3); } else @@ -1094,7 +1094,8 @@ namespace Z80 case 6: // INIR if (this.INIR()) { - this.PC.Word -= 2; + this.DecrementPC(); + this.DecrementPC(); this.Tick(5); } @@ -1102,7 +1103,8 @@ namespace Z80 case 7: // INDR if (this.INDR()) { - this.PC.Word -= 2; + this.DecrementPC(); + this.DecrementPC(); this.Tick(5); } @@ -1124,7 +1126,8 @@ namespace Z80 case 6: // OTIR if (this.OTIR()) { - this.PC.Word -= 2; + this.DecrementPC(); + this.DecrementPC(); this.Tick(5); } @@ -1132,7 +1135,8 @@ namespace Z80 case 7: // OTDR if (this.OTDR()) { - this.PC.Word -= 2; + this.DecrementPC(); + this.DecrementPC(); this.Tick(5); } @@ -1664,7 +1668,7 @@ namespace Z80 private byte FetchInitialOpCode() { var returned = this.ReadInitialOpCode(); - ++this.PC.Word; + this.IncrementPC(); return returned; }