mirror of
https://github.com/MoleskiCoder/EightBitNet.git
synced 2024-12-23 17:31:33 +00:00
482 lines
18 KiB
C#
482 lines
18 KiB
C#
// <copyright file="Disassembler.cs" company="Adrian Conlon">
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// Copyright (c) Adrian Conlon. All rights reserved.
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// </copyright>
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namespace EightBit
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{
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using System;
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public class Disassembler
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{
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public Disassembler(Bus bus) => this.Bus = bus;
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public Bus Bus { get; }
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public static string AsFlag(byte value, StatusBits flag, string represents, string off = "-") => (value & (byte)flag) != 0 ? represents : off;
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public static string AsFlags(byte value) =>
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AsFlag(value, StatusBits.SF, "S")
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+ AsFlag(value, StatusBits.ZF, "Z")
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+ AsFlag(value, (StatusBits)Bits.Bit5, "1", "0")
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+ AsFlag(value, StatusBits.AC, "A")
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+ AsFlag(value, (StatusBits)Bits.Bit3, "1", "0")
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+ AsFlag(value, StatusBits.PF, "P")
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+ AsFlag(value, (StatusBits)Bits.Bit1, "1", "0")
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+ AsFlag(value, StatusBits.CF, "C");
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public static string State(Intel8080 cpu)
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{
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var pc = cpu.PC;
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var sp = cpu.SP;
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var a = cpu.A;
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var f = cpu.F;
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var b = cpu.B;
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var c = cpu.C;
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var d = cpu.D;
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var e = cpu.E;
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var h = cpu.H;
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var l = cpu.L;
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return
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$"PC={pc.Word:x4} SP={sp.Word:x4} "
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+ $"A={a:x2} F={AsFlags(f)} "
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+ $"B={b:x2} C={c:x2} "
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+ $"D={d:x2} E={e:x2} "
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+ $"H={h:x2} L={l:x2}";
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}
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public string Disassemble(Intel8080 cpu) => this.Disassemble(cpu, cpu.PC.Word);
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private static string CC(int flag)
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{
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switch (flag)
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{
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case 0:
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return "NZ";
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case 1:
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return "Z";
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case 2:
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return "NC";
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case 3:
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return "C";
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case 4:
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return "PO";
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case 5:
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return "PE";
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case 6:
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return "P";
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case 7:
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return "M";
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}
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throw new System.ArgumentOutOfRangeException(nameof(flag));
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}
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private static string ALU(int which)
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{
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switch (which)
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{
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case 0: // ADD A,n
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return "ADD";
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case 1: // ADC
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return "ADC";
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case 2: // SUB n
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return "SUB";
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case 3: // SBC A,n
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return "SBB";
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case 4: // AND n
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return "ANA";
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case 5: // XOR n
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return "XRA";
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case 6: // OR n
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return "ORA";
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case 7: // CP n
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return "CMP";
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}
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throw new System.ArgumentOutOfRangeException(nameof(which));
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}
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private static string ALU2(int which)
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{
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switch (which)
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{
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case 0: // ADD A,n
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return "ADI";
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case 1: // ADC
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return "ACI";
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case 2: // SUB n
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return "SUI";
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case 3: // SBC A,n
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return "SBI";
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case 4: // AND n
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return "ANI";
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case 5: // XOR n
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return "XRI";
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case 6: // OR n
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return "ORI";
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case 7: // CP n
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return "CPI";
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}
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throw new System.ArgumentOutOfRangeException(nameof(which));
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}
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private static Tuple<string, int> Disassemble(int x, int y, int z, int p, int q)
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{
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var dumpCount = 0;
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var specification = string.Empty;
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switch (x)
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{
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case 0:
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switch (z)
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{
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case 0: // Relative jumps and assorted ops
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switch (y)
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{
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case 0: // NOP
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specification = "NOP";
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break;
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case 1: // EX AF AF'
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break;
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case 2: // DJNZ d
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break;
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case 3: // JR d
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break;
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default: // JR cc,d
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break;
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}
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break;
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case 1: // 16-bit load immediate/add
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switch (q)
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{
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case 0: // LD rp,nn
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specification = $"LXI {RP(p)}" + ",{1:X4}H";
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dumpCount += 2;
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break;
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case 1: // ADD HL,rp
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specification = $"DAD {RP(p)}";
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break;
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}
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break;
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case 2: // Indirect loading
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switch (q)
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{
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case 0:
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switch (p)
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{
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case 0: // LD (BC),A
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specification = "STAX B";
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break;
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case 1: // LD (DE),A
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specification = "STAX D";
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break;
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case 2: // LD (nn),HL
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specification = "SHLD {1:X4}H";
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dumpCount += 2;
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break;
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case 3: // LD (nn),A
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specification = "STA {1:X4}H";
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dumpCount += 2;
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break;
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}
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break;
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case 1:
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switch (p)
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{
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case 0: // LD A,(BC)
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specification = "LDAX B";
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break;
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case 1: // LD A,(DE)
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specification = "LDAX D";
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break;
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case 2: // LD HL,(nn)
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specification = "LHLD {1:X4}H";
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dumpCount += 2;
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break;
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case 3: // LD A,(nn)
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specification = "LDA {1:X4}H";
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dumpCount += 2;
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break;
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}
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break;
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}
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break;
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case 3: // 16-bit INC/DEC
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switch (q)
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{
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case 0: // INC rp
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specification = $"INX {RP(p)}";
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break;
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case 1: // DEC rp
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specification = $"DCX {RP(p)}";
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break;
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}
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break;
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case 4: // 8-bit INC
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specification = $"INR {R(y)}";
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break;
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case 5: // 8-bit DEC
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specification = $"DCR {R(y)}";
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break;
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case 6: // 8-bit load immediate
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specification = $"MVI {R(y)}" + ",{0:X2}H";
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dumpCount++;
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break;
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case 7: // Assorted operations on accumulator/flags
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switch (y)
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{
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case 0:
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specification = "RLC";
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break;
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case 1:
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specification = "RRC";
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break;
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case 2:
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specification = "RAL";
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break;
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case 3:
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specification = "RAR";
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break;
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case 4:
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specification = "DAA";
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break;
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case 5:
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specification = "CMA";
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break;
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case 6:
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specification = "STC";
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break;
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case 7:
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specification = "CMC";
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break;
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}
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break;
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}
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break;
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case 1: // 8-bit loading
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specification = z == 6 && y == 6 ? "HLT" : $"MOV {R(y)},{R(z)}";
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break;
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case 2: // Operate on accumulator and register/memory location
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specification = $"{ALU(y)} {R(z)}";
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break;
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case 3:
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switch (z)
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{
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case 0: // Conditional return
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specification = $"R{CC(y)}";
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break;
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case 1: // POP & various ops
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switch (q)
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{
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case 0: // POP rp2[p]
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specification = $"POP {RP2(p)}";
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break;
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case 1:
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switch (p)
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{
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case 0: // RET
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specification = "RET";
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break;
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case 1: // EXX
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break;
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case 2: // JP (HL)
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specification = "PCHL";
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break;
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case 3: // LD SP,HL
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specification = "SPHL";
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break;
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}
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break;
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}
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break;
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case 2: // Conditional jump
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specification = $"J{CC(y)}" + " {1:X4}H";
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dumpCount += 2;
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break;
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case 3: // Assorted operations
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switch (y)
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{
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case 0: // JP nn
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specification = "JMP {1:X4}H";
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dumpCount += 2;
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break;
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case 1: // CB prefix
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break;
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case 2: // OUT (n),A
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specification = "OUT {0:X2}H";
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dumpCount++;
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break;
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case 3: // IN A,(n)
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specification = "IN {0:X2}H";
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dumpCount++;
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break;
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case 4: // EX (SP),HL
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specification = "XHTL";
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break;
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case 5: // EX DE,HL
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specification = "XCHG";
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break;
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case 6: // DI
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specification = "DI";
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break;
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case 7: // EI
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specification = "EI";
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break;
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}
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break;
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case 4: // Conditional call: CALL cc[y], nn
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specification = $"C{CC(y)}" + " {1:X4}H";
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dumpCount += 2;
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break;
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case 5: // PUSH & various ops
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switch (q)
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{
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case 0: // PUSH rp2[p]
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specification = $"PUSH {RP2(p)}";
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break;
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case 1:
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switch (p)
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{
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case 0: // CALL nn
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specification = "CALL {1:X4}H";
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dumpCount += 2;
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break;
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case 1: // DD prefix
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break;
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case 2: // ED prefix
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break;
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case 3: // FD prefix
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break;
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}
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break;
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}
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break;
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case 6: // Operate on accumulator and immediate operand: alu[y] n
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specification = ALU2(y) + " {0:X2}H";
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dumpCount++;
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break;
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case 7: // Restart: RST y * 8
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specification = $"RST {y * 8:X2}";
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break;
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}
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break;
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}
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return new Tuple<string, int>(specification, dumpCount);
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}
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private static string RP(int rp)
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{
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switch (rp)
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{
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case 0:
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return "B";
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case 1:
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return "D";
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case 2:
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return "H";
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case 3:
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return "SP";
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}
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throw new System.ArgumentOutOfRangeException(nameof(rp));
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}
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private static string RP2(int rp)
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{
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switch (rp)
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{
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case 0:
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return "B";
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case 1:
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return "D";
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case 2:
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return "H";
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case 3:
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return "PSW";
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}
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throw new System.ArgumentOutOfRangeException(nameof(rp));
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}
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private static string R(int r)
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{
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switch (r)
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{
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case 0:
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return "B";
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case 1:
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return "C";
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case 2:
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return "D";
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case 3:
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return "E";
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case 4:
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return "H";
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case 5:
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return "L";
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case 6:
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return "M";
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case 7:
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return "A";
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}
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throw new System.ArgumentOutOfRangeException(nameof(r));
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}
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private string Disassemble(Intel8080 cpu, ushort pc)
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{
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var opCode = this.Bus.Peek(pc);
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var decoded = cpu.GetDecodedOpCode(opCode);
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var x = decoded.X;
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var y = decoded.Y;
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var z = decoded.Z;
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var p = decoded.P;
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var q = decoded.Q;
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var immediate = this.Bus.Peek((ushort)(pc + 1));
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var absolute = cpu.PeekWord((ushort)(pc + 1)).Word;
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var displacement = (sbyte)immediate;
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var relative = pc + displacement + 2;
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var indexedImmediate = this.Bus.Peek((ushort)(pc + 1));
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var disassembled = Disassemble(x, y, z, p, q);
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var specification = disassembled.Item1;
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var dumpCount = disassembled.Item2;
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var output = $"{opCode:x2}";
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for (var i = 0; i < dumpCount; ++i)
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{
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output += $"{this.Bus.Peek((ushort)(pc + i + 1)):x2}";
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}
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output += '\t';
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output += string.Format(specification, (int)immediate, (int)absolute, relative, (int)displacement, indexedImmediate);
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return output;
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}
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}
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}
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