mirror of
https://github.com/MoleskiCoder/EightBitNet.git
synced 2026-01-26 12:16:36 +00:00
668 lines
26 KiB
C#
668 lines
26 KiB
C#
// <copyright file="Disassembler.cs" company="Adrian Conlon">
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// Copyright (c) Adrian Conlon. All rights reserved.
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// </copyright>
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namespace LR35902
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{
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using EightBit;
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using System.Globalization;
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//public enum IoRegister
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//{
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// Abbreviated, // FF00 + dd
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// Absolute, // FFdd
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// Register, // C
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// Unused, // Unused!
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//}
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public sealed class Disassembler(Bus bus)
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{
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private bool prefixCB;
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public Bus Bus { get; } = bus;
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public static string AsFlag(byte value, byte flag, string represents) => (value & flag) != 0 ? represents : "-";
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public static string AsFlag(byte value, StatusBits flag, string represents) => AsFlag(value, (byte)flag, represents);
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public static string AsFlag(byte value, Interrupts flag, string represents) => AsFlag(value, (byte)flag, represents);
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public static string AsFlag(byte value, Bits flag, string represents) => AsFlag(value, (byte)flag, represents);
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public static string AsFlags(byte value) =>
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$"{AsFlag(value, StatusBits.ZF, "Z")}"
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+ $"{AsFlag(value, StatusBits.NF, "N")}"
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+ $"{AsFlag(value, StatusBits.HC, "H")}"
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+ $"{AsFlag(value, StatusBits.CF, "C")}"
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+ $"{AsFlag(value, Bits.Bit3, "+")}"
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+ $"{AsFlag(value, Bits.Bit2, "+")}"
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+ $"{AsFlag(value, Bits.Bit1, "+")}"
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+ $"{AsFlag(value, Bits.Bit0, "+")}";
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public static string AsInterrupt(byte value) =>
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$"{AsFlag(value, Interrupts.KeypadPressed, "K")}"
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+ $"{AsFlag(value, Interrupts.SerialTransfer, "S")}"
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+ $"{AsFlag(value, Interrupts.TimerOverflow, "T")}"
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+ $"{AsFlag(value, Interrupts.DisplayControlStatus, "D")}"
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+ $"{AsFlag(value, Interrupts.VerticalBlank, "V")}";
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public static string State(LR35902 cpu)
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{
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ArgumentNullException.ThrowIfNull(cpu);
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var pc = cpu.PC;
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var sp = cpu.SP;
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var a = cpu.A;
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var f = cpu.F;
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var b = cpu.B;
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var c = cpu.C;
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var d = cpu.D;
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var e = cpu.E;
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var h = cpu.H;
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var l = cpu.L;
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var ime = cpu.IME?1:0;
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var ie = cpu.IE;
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var i_f = cpu.IF;
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var masked = cpu.MaskedInterrupts;
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return
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$"PC={pc.Word:x4} SP={sp.Word:x4} "
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+ $"A={a:x2} F={AsFlags(f)} "
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+ $"B={b:x2} C={c:x2} "
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+ $"D={d:x2} E={e:x2} "
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+ $"H={h:x2} L={l:x2} "
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+ $"IME={ime} IE={AsInterrupt(ie)} IF={AsInterrupt(i_f)} Masked={AsInterrupt(masked)}";
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}
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public string Disassemble(LR35902 cpu)
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{
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ArgumentNullException.ThrowIfNull(cpu);
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this.prefixCB = false;
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return this.Disassemble(cpu, cpu.PC.Word);
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}
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private static string RP(int rp) => rp switch
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{
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0 => "BC",
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1 => "DE",
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2 => "HL",
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3 => "SP",
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_ => throw new ArgumentOutOfRangeException(nameof(rp)),
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};
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private static string RP2(int rp) => rp switch
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{
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0 => "BC",
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1 => "DE",
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2 => "HL",
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3 => "AF",
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_ => throw new ArgumentOutOfRangeException(nameof(rp)),
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};
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private static string R(int r) => r switch
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{
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0 => "B",
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1 => "C",
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2 => "D",
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3 => "E",
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4 => "H",
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5 => "L",
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6 => "(HL)",
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7 => "A",
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_ => throw new ArgumentOutOfRangeException(nameof(r)),
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};
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private static string IO(byte value) => value switch
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{
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// Port/Mode Registers
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IoRegisters.P1 => "IO:P1",
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IoRegisters.SB => "IO:SB",
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IoRegisters.SC => "IO:SC",
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IoRegisters.DIV => "IO:DIV",
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IoRegisters.TIMA => "IO:TIMA",
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IoRegisters.TMA => "IO:TMA",
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IoRegisters.TAC => "IO:TAC",
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// Interrupt Flags
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IoRegisters.IF => "IO:IF",
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IoRegisters.IE => "IO:IE",
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// LCD Display Registers
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IoRegisters.LCDC => "IO:LCDC",
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IoRegisters.STAT => "IO:STAT",
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IoRegisters.SCY => "IO:SCY",
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IoRegisters.SCX => "IO:SCX",
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IoRegisters.LY => "IO:LY",
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IoRegisters.LYC => "IO:LYC",
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IoRegisters.DMA => "IO:DMA",
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IoRegisters.BGP => "IO:BGP",
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IoRegisters.OBP0 => "IO:OBP0",
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IoRegisters.OBP1 => "IO:OBP1",
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IoRegisters.WY => "IO:WY",
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IoRegisters.WX => "IO:WX",
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// Sound Registers
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IoRegisters.NR10 => "IO:NR10",
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IoRegisters.NR11 => "IO:NR11",
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IoRegisters.NR12 => "IO:NR12",
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IoRegisters.NR13 => "IO:NR13",
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IoRegisters.NR14 => "IO:NR14",
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IoRegisters.NR21 => "IO:NR21",
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IoRegisters.NR22 => "IO:NR22",
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IoRegisters.NR23 => "IO:NR23",
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IoRegisters.NR24 => "IO:NR24",
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IoRegisters.NR30 => "IO:NR30",
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IoRegisters.NR31 => "IO:NR31",
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IoRegisters.NR32 => "IO:NR32",
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IoRegisters.NR33 => "IO:NR33",
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IoRegisters.NR34 => "IO:NR34",
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IoRegisters.NR41 => "IO:NR41",
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IoRegisters.NR42 => "IO:NR42",
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IoRegisters.NR43 => "IO:NR43",
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IoRegisters.NR44 => "IO:NR44",
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IoRegisters.NR50 => "IO:NR50",
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IoRegisters.NR51 => "IO:NR51",
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IoRegisters.NR52 => "IO:NR52",
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IoRegisters.WAVE_PATTERN_RAM_START => $"IO:WAVE_PATTERN_RAM+0",
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IoRegisters.WAVE_PATTERN_RAM_START + 1 => $"IO:WAVE_PATTERN_RAM+1",
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IoRegisters.WAVE_PATTERN_RAM_START + 2 => $"IO:WAVE_PATTERN_RAM+2",
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IoRegisters.WAVE_PATTERN_RAM_START + 3 => $"IO:WAVE_PATTERN_RAM+3",
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IoRegisters.WAVE_PATTERN_RAM_START + 4 => $"IO:WAVE_PATTERN_RAM+4",
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IoRegisters.WAVE_PATTERN_RAM_START + 5 => $"IO:WAVE_PATTERN_RAM+5",
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IoRegisters.WAVE_PATTERN_RAM_START + 6 => $"IO:WAVE_PATTERN_RAM+6",
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IoRegisters.WAVE_PATTERN_RAM_START + 7 => $"IO:WAVE_PATTERN_RAM+7",
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IoRegisters.WAVE_PATTERN_RAM_START + 8 => $"IO:WAVE_PATTERN_RAM+8",
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IoRegisters.WAVE_PATTERN_RAM_START + 9 => $"IO:WAVE_PATTERN_RAM+9",
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IoRegisters.WAVE_PATTERN_RAM_START + 10 => $"IO:WAVE_PATTERN_RAM+A",
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IoRegisters.WAVE_PATTERN_RAM_START + 11 => $"IO:WAVE_PATTERN_RAM+B",
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IoRegisters.WAVE_PATTERN_RAM_START + 12 => $"IO:WAVE_PATTERN_RAM+C",
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IoRegisters.WAVE_PATTERN_RAM_START + 13 => $"IO:WAVE_PATTERN_RAM+D",
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IoRegisters.WAVE_PATTERN_RAM_START + 14 => $"IO:WAVE_PATTERN_RAM+E",
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IoRegisters.WAVE_PATTERN_RAM_END => "IO:WAVE_PATTERN_RAM+F",
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// Boot rom control
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IoRegisters.BOOT_DISABLE => "IO:BOOT_DISABLE",
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_ => $"FF{value:x2}H",
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};
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private static string CC(int flag) => flag switch
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{
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0 => "NZ",
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1 => "Z",
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2 => "NC",
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3 => "C",
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4 => "PO",
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5 => "PE",
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6 => "P",
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7 => "M",
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_ => throw new ArgumentOutOfRangeException(nameof(flag)),
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};
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private static string ALU(int which) => which switch
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{
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0 => "ADD", // ADD A,n
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1 => "ADC", // ADC
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2 => "SUB", // SUB n
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3 => "SBC", // SBC A,n
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4 => "AND", // AND n
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5 => "XOR", // XOR n
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6 => "OR", // OR n
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7 => "CP", // CP n
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_ => throw new ArgumentOutOfRangeException(nameof(which)),
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};
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private static string DisassembleCB(ref string specification, int x, int y, int z)
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{
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var output = string.Empty;
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switch (x)
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{
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case 0: // rot[y] r[z]
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switch (y)
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{
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case 0:
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specification = $"RLC {R(z)}";
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break;
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case 1:
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specification = $"RRC {R(z)}";
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break;
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case 2:
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specification = $"RL {R(z)}";
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break;
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case 3:
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specification = $"RR {R(z)}";
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break;
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case 4:
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specification = $"SLA {R(z)}";
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break;
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case 5:
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specification = $"SRA {R(z)}";
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break;
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case 6:
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specification = $"SWAP {R(z)}";
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break;
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case 7:
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specification = $"SRL {R(z)}";
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break;
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default:
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break;
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}
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break;
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case 1: // BIT y, r[z]
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specification = $"BIT {y},{R(z)}";
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break;
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case 2: // RES y, r[z]
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specification = $"RES {y},{R(z)}";
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break;
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case 3: // SET y, r[z]
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specification = $"SET {y},{R(z)}";
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break;
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default:
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break;
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}
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return output;
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}
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public string Disassemble(LR35902 cpu, ushort pc)
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{
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var opCode = this.Bus.Peek(pc);
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var decoded = cpu.GetDecodedOpCode(opCode);
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var x = decoded.X;
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var y = decoded.Y;
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var z = decoded.Z;
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var p = decoded.P;
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var q = decoded.Q;
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var immediate = this.Bus.Peek((ushort)(pc + 1));
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var absolute = cpu.PeekWord((ushort)(pc + 1)).Word;
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var displacement = (sbyte)immediate;
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var relative = pc + displacement + 2;
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var indexedImmediate = this.Bus.Peek((ushort)(pc + 1));
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var dumpCount = 0;
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//var ioRegister = IoRegister.Unused;
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var output = $"{opCode:x2}";
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var specification = string.Empty;
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if (this.prefixCB)
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{
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output += DisassembleCB(ref specification, x, y, z);
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}
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else
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{
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output += this.DisassembleOther(cpu, pc, ref specification, ref dumpCount, /*ref ioRegister, */x, y, z, p, q);
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}
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for (var i = 0; i < dumpCount; ++i)
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{
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output += $"{this.Bus.Peek((ushort)(pc + i + 1)):x2}";
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}
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output += '\t';
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output += string.Format(CultureInfo.InvariantCulture, specification, (int)immediate, (int)absolute, relative, (int)displacement, indexedImmediate, IO(immediate));
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//switch (ioRegister)
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//{
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// case IoRegister.Abbreviated:
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// output += $"; register {IO(immediate)}";
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// break;
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// case IoRegister.Absolute:
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// output += "; register (Absolute)";
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// break;
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// case IoRegister.Register:
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// output += $"; register C:{IO(cpu.C)}";
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// break;
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// case IoRegister.Unused:
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// break;
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// default:
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// break;
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//}
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return output;
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}
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private string DisassembleOther(LR35902 cpu, ushort pc, ref string specification, ref int dumpCount, /*ref IoRegister ioRegister, */int x, int y, int z, int p, int q)
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{
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var output = string.Empty;
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switch (x)
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{
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case 0:
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switch (z)
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{
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case 0: // Relative jumps and assorted ops
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switch (y)
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{
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case 0: // NOP
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specification = "NOP";
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break;
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case 1: // GB: LD (nn),SP
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specification = "LD ({1:X4}H),SP";
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dumpCount += 2;
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break;
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case 2: // GB: STOP
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specification = "STOP";
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break;
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case 3: // JR d
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specification = "JR {2:X4}H";
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dumpCount++;
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break;
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default: // JR cc,d
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specification = $"JR {CC(y - 4)}" + ",{2:X4}H";
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dumpCount++;
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break;
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}
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break;
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case 1: // 16-bit load immediate/add
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switch (q)
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{
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case 0: // LD rp,nn
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specification = $"LD {RP(p)}," + "{1:X4}H";
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dumpCount += 2;
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break;
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case 1: // ADD HL,rp
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specification = $"ADD HL,{RP(p)}";
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break;
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default:
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break;
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}
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break;
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case 2: // Indirect loading
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switch (q)
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{
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case 0:
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switch (p)
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{
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case 0: // LD (BC),A
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specification = "LD (BC),A";
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break;
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case 1: // LD (DE),A
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specification = "LD (DE),A";
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break;
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case 2: // GB: LDI (HL),A
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specification = "LDI (HL),A";
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break;
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case 3: // GB: LDD (HL),A
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specification = "LDD (HL),A";
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break;
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default:
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break;
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}
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break;
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case 1:
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switch (p)
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{
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case 0: // LD A,(BC)
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specification = "LD A,(BC)";
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break;
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case 1: // LD A,(DE)
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specification = "LD A,(DE)";
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break;
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case 2: // GB: LDI A,(HL)
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specification = "LDI A,(HL)";
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break;
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case 3: // GB: LDD A,(HL)
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specification = "LDD A,(HL)";
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break;
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default:
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break;
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}
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break;
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default:
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break;
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}
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break;
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case 3: // 16-bit INC/DEC
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switch (q)
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{
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case 0: // INC rp
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specification = $"INC {RP(p)}";
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break;
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case 1: // DEC rp
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specification = $"DEC {RP(p)}";
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break;
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default:
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break;
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}
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break;
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case 4: // 8-bit INC
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specification = $"INC {R(y)}";
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break;
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case 5: // 8-bit DEC
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specification = $"DEC {R(y)}";
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break;
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case 6: // 8-bit load immediate
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specification = $"LD {R(y)}," + "{0:X2}H";
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dumpCount++;
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break;
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case 7: // Assorted operations on accumulator/flags
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switch (y)
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{
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case 0:
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specification = "RLCA";
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break;
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case 1:
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specification = "RRCA";
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break;
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case 2:
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specification = "RLA";
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break;
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case 3:
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specification = "RRA";
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break;
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case 4:
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specification = "DAA";
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break;
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case 5:
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specification = "CPL";
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break;
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case 6:
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specification = "SCF";
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break;
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case 7:
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specification = "CCF";
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break;
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default:
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break;
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}
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break;
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default:
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break;
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}
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break;
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case 1: // 8-bit loading
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if (z == 6 && y == 6)
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{
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specification = "HALT"; // Exception (replaces LD (HL), (HL))
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}
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else
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{
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specification = $"LD {R(y)},{R(z)}";
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}
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break;
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case 2: // Operate on accumulator and register/memory location
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specification = $"{ALU(y)} A,{R(z)}";
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break;
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case 3:
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switch (z)
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{
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case 0: // Conditional return
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switch (y)
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{
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case 0:
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case 1:
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case 2:
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case 3:
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specification = $"RET {CC(y)}";
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break;
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case 4:
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//specification = "LD (FF00H+{0:X2}H),A";
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specification = "LD ({5}),A";
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//ioRegister = IoRegister.Abbreviated;
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dumpCount++;
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break;
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case 5:
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specification = "ADD SP,{4:X4}H";
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dumpCount++;
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break;
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case 6:
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//specification = "LD A,(FF00H+{0:X2}H)";
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specification = "LD A,({5})";
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//ioRegister = IoRegister.Abbreviated;
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dumpCount++;
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break;
|
|
case 7:
|
|
specification = "LD HL,SP+{4}";
|
|
dumpCount++;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
break;
|
|
case 1: // POP & various ops
|
|
switch (q)
|
|
{
|
|
case 0: // POP rp2[p]
|
|
specification = $"POP {RP2(p)}";
|
|
break;
|
|
case 1:
|
|
switch (p)
|
|
{
|
|
case 0: // RET
|
|
specification = "RET";
|
|
break;
|
|
case 1: // GB: RETI
|
|
specification = "RETI";
|
|
break;
|
|
case 2: // JP (HL)
|
|
specification = "JP (HL)";
|
|
break;
|
|
case 3: // LD SP,HL
|
|
specification = "LD SP,HL";
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
break;
|
|
case 2: // Conditional jump
|
|
switch (y)
|
|
{
|
|
case 0:
|
|
case 1:
|
|
case 2:
|
|
case 3:
|
|
specification = $"JP {CC(y)}" + ",{1:X4}H";
|
|
dumpCount += 2;
|
|
break;
|
|
case 4:
|
|
specification = "LD (FF00H+C),A";
|
|
//ioRegister = IoRegister.Register;
|
|
break;
|
|
case 5:
|
|
specification = "LD ({1:X4}H),A";
|
|
dumpCount += 2;
|
|
break;
|
|
case 6:
|
|
specification = "LD A,(FF00H+C)";
|
|
//ioRegister = IoRegister.Register;
|
|
break;
|
|
case 7:
|
|
specification = "LD A,({1:X4}H)";
|
|
dumpCount += 2;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
break;
|
|
case 3: // Assorted operations
|
|
switch (y)
|
|
{
|
|
case 0: // JP nn
|
|
specification = "JP {1:X4}H";
|
|
dumpCount += 2;
|
|
break;
|
|
case 1: // CB prefix
|
|
this.prefixCB = true;
|
|
output += this.Disassemble(cpu, ++pc);
|
|
break;
|
|
case 6: // DI
|
|
specification = "DI";
|
|
break;
|
|
case 7: // EI
|
|
specification = "EI";
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
break;
|
|
case 4: // Conditional call: CALL cc[y], nn
|
|
specification = $"CALL {CC(y)}" + ",{1:X4}H";
|
|
dumpCount += 2;
|
|
break;
|
|
case 5: // PUSH & various ops
|
|
switch (q)
|
|
{
|
|
case 0: // PUSH rp2[p]
|
|
specification = $"PUSH {RP2(p)}";
|
|
break;
|
|
case 1:
|
|
switch (p)
|
|
{
|
|
case 0: // CALL nn
|
|
specification = "CALL {1:X4}H";
|
|
dumpCount += 2;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
break;
|
|
case 6: // Operate on accumulator and immediate operand: alu[y] n
|
|
specification = ALU(y) + " A,{0:X2}H";
|
|
dumpCount++;
|
|
break;
|
|
case 7: // Restart: RST y * 8
|
|
specification = $"RST {y * 8:X2}";
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return output;
|
|
}
|
|
}
|
|
}
|