From 5b792798ac30ca2fd1f9e8bb9555965ac2322594 Mon Sep 17 00:00:00 2001
From: David Schmenk <dschmenk@sbcglobal.net>
Date: Sat, 14 Sep 2024 10:50:58 -0700
Subject: [PATCH] Clipping optimizations

---
 src/libsrc/apple/dcgrlib.pla | 30 +++++++++++++++++-------------
 1 file changed, 17 insertions(+), 13 deletions(-)

diff --git a/src/libsrc/apple/dcgrlib.pla b/src/libsrc/apple/dcgrlib.pla
index 70f19c8..ae7bdb9 100644
--- a/src/libsrc/apple/dcgrlib.pla
+++ b/src/libsrc/apple/dcgrlib.pla
@@ -206,14 +206,16 @@ asm _clipX#0
         BCS     INVISX      ; YEP, X OFF RIGHT EDGE
         ;CLC
         ADC     ESTKL-3,X   ; X + WIDTH
-        CMP     TMPL        ; < DST_WIDTH?
-        BCC     VISX        ; YEP, FULLY VISIBLE
-        LDA     TMPL        ; CLIP WIDTH TO DST_WIDTH
+        CMP     TMPL        ; >= DST_WIDTH?
+        BCS     +
+        LDA     #$00        ; FULLY VISIBLE
+        RTS
++       LDA     TMPL        ; CLIP WIDTH TO DST_WIDTH
         ;SEC
         SBC     ESTKL-1,X
         STA     ESTKL-3,X   ; WIDTH = DST_WIDTH - X
-VISX    LDA     #$00        ; FULLY VISIBLE
         CLC
+        LDA     #$00        ; VISIBLE WITH WIDTH CLIP
         RTS
 ; X NEGATIVE, CHECK WITH W ADDED
 NEGX    LDA     ESTKL-1,X   ; X COORD
@@ -252,14 +254,16 @@ asm _clipY#0
         BCS     INVISY      ; YEP, Y OFF BOTTOM EDGE
         ;CLC
         ADC     ESTKL-4,X   ; Y + HEIGHT
-        CMP     TMPL        ; < DST_HEIGHT
-        BCC     VISY        ; YEP, FULLY VISIBLE
-        LDA     TMPL        ; CLIP HEIGHT TO DST_HEIGHT
+        CMP     TMPL        ; >= DST_HEIGHT
+        BCS     +
+        LDA     #$00        ; FULLY VISIBLE
+        RTS
++       LDA     TMPL        ; CLIP HEIGHT TO DST_HEIGHT
         ;SEC
         SBC     ESTKL-2,X
         STA     ESTKL-4,X   ; HEIGHT = DST_HEIGHT - Y
-VISY    LDA     #$00        ; FULLY VISIBLE
         CLC
+        LDA     #$00        ; VISIBLE WITH HEIGHT CLIP
         RTS
 ; Y NEGATIVE, CHECK WITH H ADDED
 NEGY    LDA     ESTKL-2,X   ; Y COORD
@@ -1547,15 +1551,15 @@ end
 export asm dcgrVLB#0
         PHP
         SEI
-        STA     $C079   ; Enable IOU access and reset VBL int on //c
-        STA     $C05B   ; Enable VBL int
+        STA     $C079       ; Enable IOU access and reset VBL int on //c
+        STA     $C05B       ; Enable VBL int
 -       LDA     $C019
-        STA     $C079   ; Reset VBL int on //c
+        STA     $C079       ; Reset VBL int on //c
         BMI     -
 -       LDA     $C019
         BPL     -
-        STA     $C05A   ; Disable VBL int on //c
-        STA     $C078   ; Disable IOU access on //c
+        STA     $C05A       ; Disable VBL int on //c
+        STA     $C078       ; Disable IOU access on //c
         PLP
         RTS
 end