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Compile the rest of the instructions.

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This commit is contained in:
Chris Pressey 2015-10-17 16:17:35 +01:00
parent e62fd85ccf
commit 479b484313
3 changed files with 120 additions and 13 deletions
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49
src/sixtypical/compiler.py
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@ -8,8 +8,11 @@ from sixtypical.model import (
from sixtypical.emitter import Label, Byte
from sixtypical.gen6502 import (
Immediate, Absolute,
LDA, LDX, LDY, STA, STX, STY, CLC, SEC, ADC, RTS, JSR,
LDA, LDX, LDY, STA, STX, STY,
CLC, SEC, ADC, SBC, ROL, ROR,
RTS, JSR,
INC, INX, INY, DEC, DEX, DEY,
CMP, CPX, CPY, AND, ORA, EOR,
)
@ -128,17 +131,39 @@ class Compiler(object):
else:
self.emitter.emit(DEC(Absolute(self.labels[dest.name])))
elif opcode == 'cmp':
raise NotImplementedError
elif opcode == 'and':
raise NotImplementedError
elif opcode == 'or':
raise NotImplementedError
elif opcode == 'xor':
raise NotImplementedError
elif opcode == 'shl':
raise NotImplementedError
elif opcode == 'shr':
raise NotImplementedError
cls = {
'a': CMP,
'x': CPX,
'y': CPY,
}.get(dest.name)
if cls is None:
raise UnsupportedOpcodeError(instr)
if isinstance(src, ConstantRef):
self.emitter.emit(cls(Immediate(Byte(src.value))))
else:
self.emitter.emit(cls(Absolute(self.labels[src.name])))
elif opcode in ('and', 'or', 'xor',):
cls = {
'and': AND,
'or': ORA,
'xor': EOR,
}[opcode]
if dest == REG_A:
if isinstance(src, ConstantRef):
self.emitter.emit(cls(Immediate(Byte(src.value))))
else:
self.emitter.emit(cls(Absolute(self.labels[src.name])))
else:
raise UnsupportedOpcodeError(instr)
elif opcode in ('shl', 'shr'):
cls = {
'shl': ROL,
'shr': ROR,
}[opcode]
if dest == REG_A:
self.emitter.emit(cls())
else:
raise UnsupportedOpcodeError(instr)
elif opcode == 'call':
label = self.labels[instr.name]
self.emitter.emit(JSR(Absolute(label)))

42
src/sixtypical/gen6502.py
View File

@ -74,7 +74,7 @@ class ADC(Opcode):
}
class ADD(Opcode):
class AND(Opcode):
opcodes = {
Immediate: 0x29,
Absolute: 0x2d,
@ -87,6 +87,27 @@ class CLC(Opcode):
}
class CMP(Opcode):
opcodes = {
Immediate: 0xc9,
Absolute: 0xcd,
}
class CPX(Opcode):
opcodes = {
Immediate: 0xe0,
Absolute: 0xec,
}
class CPY(Opcode):
opcodes = {
Immediate: 0xc0,
Absolute: 0xcc,
}
class DEC(Opcode):
opcodes = {
Absolute: 0xce,
@ -105,6 +126,13 @@ class DEY(Opcode):
}
class EOR(Opcode):
opcodes = {
Immediate: 0x49,
Absolute: 0x4d,
}
class INC(Opcode):
opcodes = {
Absolute: 0xee,
@ -157,6 +185,18 @@ class ORA(Opcode):
}
class ROL(Opcode):
opcodes = {
Implied: 0x2a, # Accumulator
}
class ROR(Opcode):
opcodes = {
Implied: 0x6a, # Accumulator
}
class RTS(Opcode):
opcodes = {
Implied: 0x60,

42
tests/SixtyPical Compilation.md
View File

@ -76,3 +76,45 @@ Access a defined memory location.
| ld a, foo
| }
= 00c0a0008c09c0ad09c060
Some instructions.
| byte foo
|
| routine main
| trashes a, x, y, z, n, c, v, foo
| {
| ld a, 0
| ld x, 0
| ld y, 0
| st a, foo
| st x, foo
| st y, foo
| st on, c
| st off, c
| add a, 1
| add a, foo
| sub a, 1
| sub a, foo
| inc foo
| inc x
| inc y
| dec foo
| dec x
| dec y
| and a, 255
| and a, foo
| or a, 255
| or a, foo
| xor a, 255
| xor a, foo
| cmp a, 1
| cmp a, foo
| cmp x, 1
| cmp x, foo
| cmp y, 1
| cmp y, foo
| shl a
| shr a
| }
= 00c0a900a200a0008d46c08e46c08c46c0381869016d46c0e901ed46c0ee46c0e8c8ce46c0ca8829ff2d46c009ff0d46c049ff4d46c0c901cd46c0e001ec46c0c001cc46c02a6a60