diff --git a/HISTORY.md b/HISTORY.md
index 3f6ebdb..caef163 100644
--- a/HISTORY.md
+++ b/HISTORY.md
@@ -1,6 +1,12 @@
 History of SixtyPical
 =====================
 
+0.16
+----
+
+*   `or a, z`, `and a, z`, and `eor a, z` compile to zero-page operations
+    if the address of z < 256.
+
 0.15
 ----
 
diff --git a/README.md b/README.md
index 1c25b7a..21afadd 100644
--- a/README.md
+++ b/README.md
@@ -89,6 +89,5 @@ are trashed inside the block.
 *   Automatic tail-call optimization (could be tricky, w/constraints?)
 *   Possibly `ld x, [ptr] + y`, possibly `st x, [ptr] + y`.
 *   Maybe even `copy [ptra] + y, [ptrb] + y`, which can be compiled to indirect LDA then indirect STA!
-*   Optimize `or|and|eor a, z` to zero-page operations if address of z < 256.
 
 [VICE]: http://vice-emu.sourceforge.net/
diff --git a/src/sixtypical/compiler.py b/src/sixtypical/compiler.py
index de01fba..ab38eda 100644
--- a/src/sixtypical/compiler.py
+++ b/src/sixtypical/compiler.py
@@ -332,7 +332,7 @@ class Compiler(object):
                 if isinstance(src, ConstantRef):
                     self.emitter.emit(cls(Immediate(Byte(src.value))))
                 else:
-                    self.emitter.emit(cls(Absolute(self.get_label(src.name))))
+                    self.emitter.emit(cls(self.absolute_or_zero_page(self.get_label(src.name))))
             else:
                 raise UnsupportedOpcodeError(instr)
         elif opcode in ('shl', 'shr'):
diff --git a/src/sixtypical/gen6502.py b/src/sixtypical/gen6502.py
index f166391..a2a0962 100644
--- a/src/sixtypical/gen6502.py
+++ b/src/sixtypical/gen6502.py
@@ -133,6 +133,7 @@ class AND(Instruction):
         Absolute:  0x2d,
         AbsoluteX: 0x3d,
         AbsoluteY: 0x39,
+        ZeroPage:  0x25,
     }
 
 
@@ -231,6 +232,7 @@ class EOR(Instruction):
         Absolute:  0x4d,
         AbsoluteX: 0x5d,
         AbsoluteY: 0x59,
+        ZeroPage:  0x45,
     }
 
 
@@ -299,6 +301,7 @@ class ORA(Instruction):
         Absolute:  0x0d,
         AbsoluteX: 0x1d,
         AbsoluteY: 0x19,
+        ZeroPage:  0x05,
     }
 
 
diff --git a/tests/SixtyPical Compilation.md b/tests/SixtyPical Compilation.md
index d6562d0..5e546e9 100644
--- a/tests/SixtyPical Compilation.md	
+++ b/tests/SixtyPical Compilation.md	
@@ -112,7 +112,8 @@ Memory location with explicit address.
     = $080F   STA $0400
     = $0812   RTS
 
-Accesses to memory locations in zero-page with `ld` and `st` use zero-page addressing.
+Accesses to memory locations in zero-page with `ld` and `st`
+and `and`, `or`, and `xor` use zero-page addressing.
 
     | byte zp @ $00
     | byte screen @ 100
@@ -126,12 +127,18 @@ Accesses to memory locations in zero-page with `ld` and `st` use zero-page addre
     |   st a, screen
     |   ld a, zp
     |   st a, zp
+    |   and a, zp
+    |   or a, zp
+    |   xor a, zp
     | }
     = $080D   LDA $64
     = $080F   STA $64
     = $0811   LDA $00
     = $0813   STA $00
-    = $0815   RTS
+    = $0815   AND $00
+    = $0817   ORA $00
+    = $0819   EOR $00
+    = $081B   RTS
 
 Memory location with initial value.