Indexed access, + x / + y, at least for LDA and STA.

--HG--
rename : eg/screen.60p => eg/screen1.60p

HISTORY.markdown

@@ -1,6 +1,11 @@
 History of SixtyPical
 =====================
 
+0.5-PRE
+-------
+
+*   Added `byte table` type locations and indexed addressing (`+ x`, `+ y`).
+
 0.4
 ---
 

README.markdown

@@ -33,23 +33,22 @@ TODO
 
 For 0.5:
 
-*   `table` type constructor and indirect addressing.
+*   hexadecimal literals.
+*   source code comments.
 
 For 0.6:
 
-*   hexadecimal literals.
+*   `interrupt` routines.
-*   source code comments.
+*   `vector` type.
 
 For 0.7:
 
 *   `word` type.
+*   `copy` instruction.
+*   `trash` instruction.
 
 For 0.8:
 
-*   `vector` type.
-
-For 0.9:
-
 *   add line number (or at least routine name) to error messages.
 *   6502-mnemonic aliases (`sec`, `clc`)
 *   other handy aliases (`eq` for `z`, etc.)

eg/screen1.60p

@@ -3,6 +3,6 @@ byte screen @ 1024
 routine main
   trashes a, z, n, screen
 {
-  ld a, 100
+  ld a, 83
   st a, screen
 }

eg/screen2.60p

@@ -0,0 +1,12 @@
+byte table screen @ 1024
+
+routine main
+  trashes a, x, z, n, screen
+{
+    ld x, 0
+    ld a, 83
+    repeat {
+        st a, screen + x
+        inc x
+    } until z
+}

src/sixtypical/compiler.py

@@ -8,7 +8,7 @@ from sixtypical.model import (
 )
 from sixtypical.emitter import Label, Byte
 from sixtypical.gen6502 import (
-    Immediate, Absolute, Relative,
+    Immediate, Absolute, AbsoluteX, AbsoluteY, Relative,
     LDA, LDX, LDY, STA, STX, STY,
     TAX, TAY, TXA, TYA,
     CLC, SEC, ADC, SBC, ROL, ROR,
@@ -81,6 +81,10 @@ class Compiler(object):
                     self.emitter.emit(TYA())
                 elif isinstance(src, ConstantRef):
                     self.emitter.emit(LDA(Immediate(Byte(src.value))))
+                elif instr.index == REG_X:
+                    self.emitter.emit(LDA(AbsoluteX(self.labels[src.name])))
+                elif instr.index == REG_Y:
+                    self.emitter.emit(LDA(AbsoluteY(self.labels[src.name])))
                 else:
                     self.emitter.emit(LDA(Absolute(self.labels[src.name])))
             elif dest == REG_X:
@@ -88,6 +92,8 @@ class Compiler(object):
                     self.emitter.emit(TAX())
                 elif isinstance(src, ConstantRef):
                     self.emitter.emit(LDX(Immediate(Byte(src.value))))
+                elif instr.index == REG_Y:
+                    self.emitter.emit(LDX(AbsoluteY(self.labels[src.name])))
                 else:
                     self.emitter.emit(LDX(Absolute(self.labels[src.name])))
             elif dest == REG_Y:
@@ -95,6 +101,8 @@ class Compiler(object):
                     self.emitter.emit(TAY())
                 elif isinstance(src, ConstantRef):
                     self.emitter.emit(LDY(Immediate(Byte(src.value))))
+                elif instr.index == REG_X:
+                    self.emitter.emit(LDY(AbsoluteX(self.labels[src.name])))
                 else:
                     self.emitter.emit(LDY(Absolute(self.labels[src.name])))
             else:
@@ -104,14 +112,20 @@ class Compiler(object):
                 self.emitter.emit(CLC())
             elif dest == FLAG_C and src == ConstantRef(TYPE_BIT, 1):
                 self.emitter.emit(SEC())
-            elif src == REG_A:
-                self.emitter.emit(STA(Absolute(self.labels[dest.name])))
-            elif src == REG_X:
-                self.emitter.emit(STX(Absolute(self.labels[dest.name])))
-            elif src == REG_Y:
-                self.emitter.emit(STY(Absolute(self.labels[dest.name])))
             else:
-                raise UnsupportedOpcodeError(instr)
+                op_cls = {
+                    REG_A: STA,
+                    REG_X: STX,
+                    REG_Y: STY
+                }.get(src, None)
+                mode_cls = {
+                    REG_X: AbsoluteX,
+                    REG_Y: AbsoluteY,
+                    None: Absolute
+                }.get(instr.index, None)
+                if op_cls is None or mode_cls is None:
+                    raise UnsupportedOpcodeError(instr)
+                self.emitter.emit(op_cls(mode_cls(self.labels[dest.name])))
         elif opcode == 'add':
             if dest == REG_A:
                 if isinstance(src, ConstantRef):

tests/SixtyPical Analysis.md

@@ -252,7 +252,6 @@ Storing to a table, you must use an index, and vice-versa.
 Reading from a table, you must use an index, and vice-versa.
 
     | byte one
-    | byte table many
     | 
     | routine main
     |   outputs one
@@ -265,7 +264,6 @@ Reading from a table, you must use an index, and vice-versa.
     = ok
 
     | byte one
-    | byte table many
     | 
     | routine main
     |   outputs one
@@ -277,7 +275,6 @@ Reading from a table, you must use an index, and vice-versa.
     | }
     ? TypeMismatchError
 
-    | byte one
     | byte table many
     | 
     | routine main
@@ -291,7 +288,6 @@ Reading from a table, you must use an index, and vice-versa.
     | }
     ? TypeMismatchError
 
-    | byte one
     | byte table many
     | 
     | routine main

tests/SixtyPical Compilation.md

@@ -208,3 +208,19 @@ Compiling `repeat forever`.
     |     } forever
     | }
     = 00c0a041c84c02c060
+
+Indexed access.
+
+    | byte one
+    | byte table many
+    | 
+    | routine main
+    |   outputs many
+    |   trashes a, x, n, z
+    | {
+    |     ld x, 0
+    |     ld a, 0
+    |     st a, many + x
+    |     ld a, many + x
+    | }
+    = 00c0a200a9009d0dc0bd0dc060