2019-03-18 21:56:19 +00:00
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65816 opcode table
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There are no more undocumented opcodes.
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All differences to the 65c02 are marked using a '+' sign, except
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for the #imm8 -> #imm change.
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00 brk 01 ora (dp, x) 02+ cop imm8 03+ ora offs8, s
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04 tsb dp 05 ora dp 06 asl dp 07+ ora [dp]
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08 php 09 ora #imm 0a asl 0b+ phd
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0c tsb abs16 0d ora abs16 0e asl abs16 0f+ ora abs24
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10 bpl rel8 11 ora (dp), y 12 ora (dp) 13+ ora (offs8, s), y
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14 trb dp 15 ora dp, x 16 asl dp, x 17+ ora [dp], y
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18 clc 19 ora abs16, y 1a inc 1b+ tcs
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1c trb abs16 1d ora abs16, x 1e asl abs16, x 1f+ ora abs24, x
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20 jsr abs16 21 and (dp, x) 22+ jsr abs24 23+ and offs8, s
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24 bit dp 25 and dp 26 rol dp 27+ and [dp]
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28 plp 29 and #imm 2a rol 2b+ pld
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2c bit abs16 2d and abs16 2e rol abs16 2f+ and abs24
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30 bmi rel8 31 and (dp), y 32 and (dp) 33+ and (offs8, s), y
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34 bit dp, x 35 and dp, x 36 rol dp, x 37+ and [dp], y
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38 sec 39 and abs16, y 3a dec 3b+ tsc
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3c bit abs16, x 3d and abs16, x 3e rol abs16, x 3f+ and abs24, x
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40 rti 41 eor (dp, x) 42+ wdm 43+ eor offs8, s
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44+ mvp src, dst 45 eor dp 46 lsr dp 47+ eor [dp]
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48 pha 49 eor #imm 4a lsr 4b+ phk
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4c jmp abs16 4d eor abs16 4e lsr abs16 4f+ eor abs24
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50 bvc rel8 51 eor (dp), y 52 eor (dp) 53+ eor (offs8, s), y
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54+ mvn src, dst 55 eor dp, x 56 lsr dp, x 57+ eor [dp], y
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58 cli 59 eor abs16, y 5a phy 5b+ tcd
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5c+ jmp abs24 5d eor abs16, x 5e lsr abs16, x 5f+ eor abs24, x
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60 rts 61 adc (dp, x) 62+ per rel16 63+ adc offs8, s
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64 stz dp 65 adc dp 66 ror dp 67+ adc [dp]
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68 pla 69 adc #imm 6a ror 6b+ rtl
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6c jmp (abs16) 6d adc abs16 6e ror abs16 6f+ adc abs24
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70 bvs rel8 71 adc (dp), y 72 adc (dp) 73+ adc (offs8, s), y
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74 stz dp, x 75 adc dp, x 76 ror dp, x 77+ adc [dp], y
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78 sei 79 adc abs16, y 7a ply 7b+ tdc
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7c jmp (abs16, x) 7d adc abs16, x 7e ror abs16, x 7f+ adc abs24, x
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80 bra rel8 81 sta (dp, x) 82+ brl rel16 83+ sta offs8, s
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84 sty dp 85 sta dp 86 stx dp 87+ sta [dp]
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88 dey 89 bit #imm 8a txa 8b+ phb
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8c sty abs16 8d sta abs16 8e stx abs16 8f+ sta abs24
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90 bcc rel8 91 sta (dp), y 92 sta (dp) 93+ sta (offs8, s), y
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94 sty dp, x 95 sta dp, x 96 stx dp, y 97+ sta [dp], y
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98 tya 99 sta abs16, y 9a txs 9b+ txy
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9c stz abs16 9d sta abs16, x 9e stz abs16, x 9f+ sta abs24, x
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a0 ldy #imm a1 lda (dp, x) a2 ldx #imm a3+ lda offs8, s
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a4 ldy dp a5 lda dp a6 ldx dp a7+ lda [dp]
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a8 tay a9 lda #imm aa tax ab+ plb
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ac ldy abs16 ad lda abs16 ae ldx abs16 af+ lda abs24
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b0 bcs rel8 b1 lda (dp), y b2 lda (dp) b3+ lda (offs8, s), y
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b4 ldy dp, x b5 lda dp, x b6 ldx dp, y b7+ lda [dp], y
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b8 clv b9 lda abs16, y ba tsx bb+ tyx
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bc ldy abs16, x bd lda abs16, x be ldx abs16, y bf+ lda abs24, x
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c0 cpy #imm c1 cmp (dp, x) c2+ rep #imm8 c3+ cmp offs8, s
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c4 cpy dp c5 cmp dp c6 dec dp c7+ cmp [dp]
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c8 iny c9 cmp #imm ca dex cb+ wai
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cc cpy abs16 cd cmp abs16 ce dec abs16 cf+ cmp abs24
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d0 bne rel8 d1 cmp (dp), y d2 cmp (dp) d3+ cmp (offs8, s), y
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d4+ pei (dp) d5 cmp dp, x d6 dec dp, x d7+ cmp [dp], y
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d8 cld d9 cmp abs16, y da phx db+ stp
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dc+ jmp [abs16] dd cmp abs16, x de dec abs16, x df+ cmp abs24, x
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e0 cpx #imm e1 sbc (dp, x) e2+ sep #imm8 e3+ sbc offs8, s
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e4 cpx dp e5 sbc dp e6 inc dp e7+ sbc [dp]
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e8 inx e9 sbc #imm ea nop eb+ xba
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ec cpx abs16 ed sbc abs16 ee inc abs16 ef+ sbc abs24
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f0 beq rel8 f1 sbc (dp), y f2 sbc (dp) f3+ sbc (offs8, s), y
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f4+ pea abs16 f5 sbc dp, x f6 inc dp, x f7+ sbc [dp], y
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f8 sed f9 sbc abs16, y fa plx fb+ xce
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fc+ jsr (abs16, x) fd sbc abs16, x fe inc abs16, x ff+ sbc abs24, x
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#imm: immediate value (8 or 16 bits, depends on processor status)
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#imm8: 8-bit immediate value
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dp: 8-bit direct page address
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offs8: 8-bit offset (for stack-relative addressing)
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abs16: 16-bit absolute address
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abs24: 24-bit absolute address
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rel8: 8-bit relative address offset
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rel16: 16-bit relative address offset
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src, dst: two 8-bit bank values
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(CAUTION: assembler expects "mnemonic src, dst" syntax,
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but machine language order is actually "opcode dst src")
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The instruction set of the 65816 is a much extended superset of that
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of the 65c02. Among the improvements are:
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- the register widths can be switched to 16 bits
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- addresses can now be 24 bits wide
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- zero page is now called direct page, with an arbitrary base address
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- lots of new addressing modes
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- block transfer instructions
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New mnemonics
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-------------
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2020-06-28 00:30:43 +00:00
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02 cop imm8 coprocessor operation
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6b rtl return long (fetches 24-bit address from stack)
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82 brl rel16 branch long (16-bit offset)
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0b phd push direct page register
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4b phk push program bank register
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8b phb push data bank register
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62 per rel16 push effective relative address
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d4 pei (dp) push effective indirect address
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f4 pea abs16 push effective absolute address
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2b pld pull direct page register
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ab plb pull data bank register
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1b tcs transfer C to stack pointer
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3b tsc transfer stack pointer to C
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5b tcd transfer C to direct page register
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7b tdc transfer direct page register to C
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('C' means the whole 16-bit accumulator, even in 8-bit mode)
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9b txy transfer X to Y
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bb tyx transfer Y to X
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eb xba exchange high and low bytes of accumulator
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fb xce exchange Carry and Emulation bits
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c2 rep #imm8 clear bits in status register
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e2 sep #imm8 set bits in status register
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cb wai wait for interrupt
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db stp wait for reset
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42 wdm (reserved for future expansion)
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block transfers:
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44 mvp src, dst move previous (decrementing addresses)
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54 mvn src, dst move next (incrementing addresses)
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the arguments are bank numbers. block size minus one must be in 16-bit
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accumulator. X holds source address, Y holds target address.
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after these instructions, data bank register is set to "dst".
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if blocks overlap:
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when moving a block to a higher address, use mvp and put the highest
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addresses in X/Y.
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when moving a block to a lower address, use mvn and put the lowest
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adresses in X/Y.
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2019-03-18 21:56:19 +00:00
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New addressing modes for existing mnemonics
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-------------------------------------------
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22 jsr abs24
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5c jmp abs24
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dc jmp [abs16]
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fc jsr (abs16, x)
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ora and eor adc sta lda cmp sbc
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-------------------------------
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03 23 43 63 83 a3 c3 e3 offs8, s
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07 27 47 67 87 a7 c7 e7 [dp]
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0f 2f 4f 6f 8f af cf ef abs24
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13 33 53 73 93 b3 d3 f3 (offs8, s), y
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17 37 57 77 97 b7 d7 f7 [dp], y
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1f 3f 5f 7f 9f bf df ff abs24, x
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