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added BITQ and ASRQ to m65 cpu.
git-svn-id: https://svn.code.sf.net/p/acme-crossass/code-0/trunk@283 4df02467-bbd4-4a76-a152-e7ce94205b78
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marcobaye
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@ -184,10 +184,15 @@ quad mode introduces several new mnemonics:
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ANDQ/EORQ/ORQ like AND/EOR/ORA
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ASLQ/LSRQ/ROLQ/RORQ like ASL/LSR/ROL/ROR
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INQ/DEQ like INC/DEC
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BITQ like BIT
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ASRQ like ASR
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The new mnemonics support all the addressing modes of the original
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mnemonics with two exceptions:
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- there are no 32-bit immediate arguments
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mnemonics with these exceptions:
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- there is no immediate addressing
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- indirect-Z-indexed addressing becomes indirect addressing
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- all other indexed addressing modes are only really useful
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with read-modify-write instructions or LDQ, because otherwise
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a part of the 'Q' value will be used as the index.
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CAUTION: The STQ instruction clobbers the N and Z flags!
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There is no "real" Q register, instead A/X/Y/Z are combined to form
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the Q register (A holds lsb, Z holds msb), except for read-modify-
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@ -217,4 +222,3 @@ quad and long modes combined result in another addressing mode for
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The NOP mnemonic is disabled for this instruction set because its
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opcode is re-used internally as a prefix byte.
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CAUTION: The !align pseudo opcode still inserts NOPs.
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@ -12,6 +12,8 @@ The mnemonics ldq/stq have nine addressing modes in quad mode, and a tenth
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when combined with long mode.
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The mnemonics cpq/adcq/sbcq/andq/eorq/orq have eight addressing modes in quad
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mode, and a ninth when combined with long mode.
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The mnemonic bitq has four addressing modes.
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The mnemonic asrq has three addressing modes.
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This mode is entered after a NEG:NEG (42 42) prefix, the following opcode is
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then taken from this table:
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@ -25,20 +27,20 @@ then taken from this table:
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1c 1d orq abs16, x 1e aslq abs16, x 1f
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20 21 andq (zp, x) 22 23
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24 25 andq zp 26 rolq zp 27
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24 bitq zp 25 andq zp 26 rolq zp 27
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28 29 2a rolq 2b
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2c 2d andq abs16 2e rolq abs16 2f
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2c bitq abs16 2d andq abs16 2e rolq abs16 2f
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30 31 andq (zp), y 32 andq (zp) 33
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34 35 andq zp, x 36 rolq zp, x 37
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34 bitq zp, x 35 andq zp, x 36 rolq zp, x 37
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38 39 andq abs16, y 3a deq 3b
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3c 3d andq abs16, x 3e rolq abs16, x 3f
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3c bitq abs16, x 3d andq abs16, x 3e rolq abs16, x 3f
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40 41 eorq (zp, x) 42 43
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44 45 eorq zp 46 lsrq zp 47
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40 41 eorq (zp, x) 42 43 asrq
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44 asrq zp 45 eorq zp 46 lsrq zp 47
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48 49 4a lsrq 4b
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4c 4d eorq abs16 4e lsrq abs16 4f
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50 51 eorq (zp), y 52 eorq (zp) 53
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54 55 eorq zp, x 56 lsrq zp, x 57
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54 asrq zp, x 55 eorq zp, x 56 lsrq zp, x 57
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58 59 eorq abs16, y 5a 5b
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5c 5d eorq abs16, x 5e lsrq abs16, x 5f
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20
src/mnemo.c
20
src/mnemo.c
@ -112,13 +112,13 @@ SCB accu_lindz8[] = { 0, 0, 0, 0, 0x12, 0, 0,
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// mnemotable), the assembler finds out the column to use here. The row
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// depends on the used addressing mode. A zero entry in these tables means
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// that the combination of mnemonic and addressing mode is illegal.
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// | 6502 | 6502/65c02/65ce02 | 65c02 | 65ce02 | 65816 | NMOS 6502 undocumented opcodes | C64DTV2 |
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enum { IDX_ASL,IDX_ROL,IDX_LSR,IDX_ROR,IDX_LDY,IDX_LDX,IDX_CPY,IDX_CPX,IDX_BIT,IDXcBIT,IDX_STX,IDXeSTX,IDX_STY,IDXeSTY,IDX_DEC,IDXcDEC,IDX_INC,IDXcINC,IDXcTSB,IDXcTRB,IDXcSTZ,IDXeASR,IDXeASW,IDXeCPZ,IDXeLDZ,IDXePHW,IDXeROW,IDXeRTN,IDX16COP,IDX16REP,IDX16SEP,IDX16PEA,IDXuANC,IDXuASR,IDXuARR,IDXuSBX,IDXuNOP,IDXuDOP,IDXuTOP,IDXuLXA,IDXuANE,IDXuLAS,IDXuTAS,IDXuSHX,IDXuSHY,IDX_SAC,IDX_SIR};
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SCB misc_impl[] = { 0x0a, 0x2a, 0x4a, 0x6a, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x3a, 0, 0x1a, 0, 0, 0, 0x43, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0xea, 0x80, 0x0c, 0, 0, 0, 0, 0, 0, 0, 0}; // implied/accu
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SCB misc_imm[] = { 0, 0, 0, 0, 0xa0, 0xa2, 0xc0, 0xe0, 0, 0x89, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0xc2, 0xa3, 0xf4, 0, 0x62, /*2?*/0, 0xc2, 0xe2, 0, 0x0b, 0x4b, 0x6b, 0xcb, 0x80, 0x80, 0, 0xab, 0x8b, 0, 0, 0, 0, 0x32, 0x42}; // #$ff #$ffff
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SCS misc_abs[] = { 0x0e06, 0x2e26, 0x4e46, 0x6e66, 0xaca4, 0xaea6, 0xccc4, 0xece4, 0x2c24, 0x2c24, 0x8e86, 0x8e86, 0x8c84, 0x8c84, 0xcec6, 0xcec6, 0xeee6, 0xeee6, 0x0c04, 0x1c14, 0x9c64, 0x44, 0xcb00, 0xdcd4, 0xab00, 0xfc00, 0xeb00, 0, 0x02, 0, 0, 0xf400, 0, 0, 0, 0, 0x0c04, 0x04, 0x0c00, 0, 0, 0, 0, 0, 0, 0, 0}; // $ff $ffff
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SCS misc_xabs[] = { 0x1e16, 0x3e36, 0x5e56, 0x7e76, 0xbcb4, 0, 0, 0, 0, 0x3c34, 0, 0, 0x94, 0x8b94, 0xded6, 0xded6, 0xfef6, 0xfef6, 0, 0, 0x9e74, 0x54, 0, 0, 0xbb00, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x1c14, 0x14, 0x1c00, 0, 0, 0, 0, 0, 0x9c00, 0, 0}; // $ff,x $ffff,x
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SCS misc_yabs[] = { 0, 0, 0, 0, 0, 0xbeb6, 0, 0, 0, 0, 0x96, 0x9b96, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0xbb00, 0x9b00, 0x9e00, 0, 0, 0}; // $ff,y $ffff,y
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// | 6502 | 6502/65c02/65ce02/m65 | 65c02 | 65ce02 | 65816 | NMOS 6502 undocumented opcodes | C64DTV2 |
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enum { IDX_ASL,IDX_ROL,IDX_LSR,IDX_ROR,IDX_LDY,IDX_LDX,IDX_CPY,IDX_CPX,IDX_BIT,IDXcBIT,IDXmBITQ,IDX_STX,IDXeSTX,IDX_STY,IDXeSTY,IDX_DEC,IDXcDEC,IDX_INC,IDXcINC,IDXcTSB,IDXcTRB,IDXcSTZ,IDXeASR,IDXeASW,IDXeCPZ,IDXeLDZ,IDXePHW,IDXeROW,IDXeRTN,IDX16COP,IDX16REP,IDX16SEP,IDX16PEA,IDXuANC,IDXuASR,IDXuARR,IDXuSBX,IDXuNOP,IDXuDOP,IDXuTOP,IDXuLXA,IDXuANE,IDXuLAS,IDXuTAS,IDXuSHX,IDXuSHY,IDX_SAC,IDX_SIR};
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SCB misc_impl[] = { 0x0a, 0x2a, 0x4a, 0x6a, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x3a, 0, 0x1a, 0, 0, 0, 0x43, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0xea, 0x80, 0x0c, 0, 0, 0, 0, 0, 0, 0, 0}; // implied/accu
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SCB misc_imm[] = { 0, 0, 0, 0, 0xa0, 0xa2, 0xc0, 0xe0, 0, 0x89, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0xc2, 0xa3, 0xf4, 0, 0x62, /*2?*/0, 0xc2, 0xe2, 0, 0x0b, 0x4b, 0x6b, 0xcb, 0x80, 0x80, 0, 0xab, 0x8b, 0, 0, 0, 0, 0x32, 0x42}; // #$ff #$ffff
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SCS misc_abs[] = { 0x0e06, 0x2e26, 0x4e46, 0x6e66, 0xaca4, 0xaea6, 0xccc4, 0xece4, 0x2c24, 0x2c24, 0x2c24, 0x8e86, 0x8e86, 0x8c84, 0x8c84, 0xcec6, 0xcec6, 0xeee6, 0xeee6, 0x0c04, 0x1c14, 0x9c64, 0x44, 0xcb00, 0xdcd4, 0xab00, 0xfc00, 0xeb00, 0, 0x02, 0, 0, 0xf400, 0, 0, 0, 0, 0x0c04, 0x04, 0x0c00, 0, 0, 0, 0, 0, 0, 0, 0}; // $ff $ffff
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SCS misc_xabs[] = { 0x1e16, 0x3e36, 0x5e56, 0x7e76, 0xbcb4, 0, 0, 0, 0, 0x3c34, 0x3c34, 0, 0, 0x94, 0x8b94, 0xded6, 0xded6, 0xfef6, 0xfef6, 0, 0, 0x9e74, 0x54, 0, 0, 0xbb00, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x1c14, 0x14, 0x1c00, 0, 0, 0, 0, 0, 0x9c00, 0, 0}; // $ff,x $ffff,x
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SCS misc_yabs[] = { 0, 0, 0, 0, 0, 0xbeb6, 0, 0, 0, 0, 0, 0x96, 0x9b96, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0xbb00, 0x9b00, 0x9e00, 0, 0, 0}; // $ff,y $ffff,y
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// Code tables for group GROUP_ALLJUMPS:
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// These tables are needed for finding out the correct code when the mnemonic
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@ -485,6 +485,10 @@ static struct ronode mnemos_m65[] = {
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// ...now ASLQ/LSRQ/ROLQ/RORQ
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// INC/DEC
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// ...now INQ/DEQ
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// BIT
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// ...now BITQ
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// ASR
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// ...now ASRQ
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// it works with all addressing modes (beware of index register usage!)
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// except for immediate addressing and "($ff),z", which becomes "($ff)"
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// extension 3:
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@ -513,6 +517,8 @@ static struct ronode mnemos_m65[] = {
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PREDEFNODE("rorq", MERGE(GROUP_MISC, IDX_ROR | PREFIX_NEGNEG)),
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PREDEFNODE("inq", MERGE(GROUP_MISC, IDXcINC | PREFIX_NEGNEG)),
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PREDEFNODE("deq", MERGE(GROUP_MISC, IDXcDEC | PREFIX_NEGNEG)),
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PREDEFNODE("bitq", MERGE(GROUP_MISC, IDXmBITQ | PREFIX_NEGNEG)),
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PREDEFNODE("asrq", MERGE(GROUP_MISC, IDXeASR | PREFIX_NEGNEG)),
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// because the NOP opcode is used as a prefix code, the mnemonic was disabled:
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PREDEFLAST("nop", MERGE(GROUP_PREFIX, 0xea)),
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// ^^^^ this marks the last element
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@ -9,7 +9,7 @@
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#define RELEASE "0.97" // update before release FIXME
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#define CODENAME "Zem" // update before release
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#define CHANGE_DATE "18 Jul" // update before release FIXME
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#define CHANGE_DATE "28 Jul" // update before release FIXME
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#define CHANGE_YEAR "2020" // update before release
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//#define HOME_PAGE "http://home.pages.de/~mac_bacon/smorbrod/acme/"
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#define HOME_PAGE "http://sourceforge.net/p/acme-crossass/" // FIXME
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Binary file not shown.
@ -28,20 +28,26 @@ M65 = 1 ; make next include skip the NOP mnemonic (re-used as prefix code by M65
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orq $1d1e, x ; 1d
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aslq $1d1e, x ; 1e
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andq ($01, x) ; 21
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bitq $05 ; 24
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andq $05 ; 25
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rolq $05 ; 26
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rolq ; 2a
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bitq $0d0e ; 2c
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andq $0d0e ; 2d
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rolq $0d0e ; 2e
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andq ($11), y ; 31
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andq ($12) ; 32
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bitq $15, x ; 34
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andq $15, x ; 35
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rolq $15, x ; 36
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andq $1919, y ; 39
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deq ; 3a
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bitq $1d1e, x ; 3c
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andq $1d1e, x ; 3d
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rolq $1d1e, x ; 3e
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eorq ($01, x) ; 41
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asrq ; 43
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asrq $05 ; 44
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eorq $05 ; 45
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lsrq $05 ; 46
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lsrq ; 4a
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@ -49,6 +55,7 @@ M65 = 1 ; make next include skip the NOP mnemonic (re-used as prefix code by M65
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lsrq $0d0e ; 4e
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eorq ($11), y ; 51
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eorq ($12) ; 52
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asrq $15, x ; 54
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eorq $15, x ; 55
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lsrq $15, x ; 56
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eorq $1919, y ; 59
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