From b03b2179795a5ad65b07db07b2c1928c5d82b64c Mon Sep 17 00:00:00 2001 From: marcobaye Date: Wed, 29 Jul 2020 23:30:33 +0000 Subject: [PATCH] disabled all indexed addressing for m65's "quad" mode, except for LDQ. git-svn-id: https://svn.code.sf.net/p/acme-crossass/code-0/trunk@287 4df02467-bbd4-4a76-a152-e7ce94205b78 --- docs/cputypes/all.txt | 8 ++-- docs/cputypes/cpu m65.txt | 82 ++++++++++++++++++------------------ src/mnemo.c | 16 ++++--- src/version.h | 2 +- testing/cpus/expected-m65.o | Bin 1060 -> 889 bytes testing/cpus/test-m65.a | 79 +++++++++++++++++----------------- 6 files changed, 95 insertions(+), 92 deletions(-) diff --git a/docs/cputypes/all.txt b/docs/cputypes/all.txt index 4f104e5..2c7864c 100644 --- a/docs/cputypes/all.txt +++ b/docs/cputypes/all.txt @@ -186,13 +186,13 @@ quad mode introduces several new mnemonics: INQ/DEQ like INC/DEC BITQ like BIT ASRQ like ASR - The new mnemonics support all the addressing modes of the original - mnemonics with these exceptions: + The new mnemonics support most of the addressing modes of the + original mnemonics with these exceptions: - there is no immediate addressing - indirect-Z-indexed addressing becomes indirect addressing - - all other indexed addressing modes are only really useful + - all other indexed addressing modes can only really be used with read-modify-write instructions or LDQ, because otherwise - a part of the 'Q' value will be used as the index. + a part of the 'Q' value would be used as the index. CAUTION: The STQ instruction clobbers the N and Z flags! There is no "real" Q register, instead A/X/Y/Z are combined to form the Q register (A holds lsb, Z holds msb), except for read-modify- diff --git a/docs/cputypes/cpu m65.txt b/docs/cputypes/cpu m65.txt index 6adb29e..23787d6 100644 --- a/docs/cputypes/cpu m65.txt +++ b/docs/cputypes/cpu m65.txt @@ -8,61 +8,61 @@ file), so this file only contains information about the extensions. "quad mode" allows 32-bit data operations using a virtual register called 'Q'. The mnemonics aslq/lsrq/rolq/rorq/inq/deq have five addressing modes. -The mnemonics ldq/stq have nine addressing modes in quad mode, and a tenth -when combined with long mode. -The mnemonics cpq/adcq/sbcq/andq/eorq/orq have eight addressing modes in quad -mode, and a ninth when combined with long mode. -The mnemonic bitq has four addressing modes. +The mnemonic ldq has eight addressing modes in quad mode, and a ninth when +combined with long mode. +The mnemonics stq/cpq/adcq/sbcq/andq/eorq/orq have three addressing modes in +quad mode, and a fourth when combined with long mode. +The mnemonic bitq has two addressing modes. The mnemonic asrq has three addressing modes. This mode is entered after a NEG:NEG (42 42) prefix, the following opcode is then taken from this table: -00 01 orq (zp, x) 02 03 +00 01 02 03 04 05 orq zp 06 aslq zp 07 08 09 0a aslq 0b 0c 0d orq abs16 0e aslq abs16 0f -10 11 orq (zp), y 12 orq (zp) 13 -14 15 orq zp, x 16 aslq zp, x 17 -18 19 orq abs16, y 1a inq 1b -1c 1d orq abs16, x 1e aslq abs16, x 1f +10 11 12 orq (zp) 13 +14 15 16 aslq zp, x 17 +18 19 1a inq 1b +1c 1d 1e aslq abs16, x 1f -20 21 andq (zp, x) 22 23 +20 21 22 23 24 bitq zp 25 andq zp 26 rolq zp 27 28 29 2a rolq 2b 2c bitq abs16 2d andq abs16 2e rolq abs16 2f -30 31 andq (zp), y 32 andq (zp) 33 -34 bitq zp, x 35 andq zp, x 36 rolq zp, x 37 -38 39 andq abs16, y 3a deq 3b -3c bitq abs16, x 3d andq abs16, x 3e rolq abs16, x 3f +30 31 32 andq (zp) 33 +34 35 36 rolq zp, x 37 +38 39 3a deq 3b +3c 3d 3e rolq abs16, x 3f -40 41 eorq (zp, x) 42 43 asrq +40 41 42 43 asrq 44 asrq zp 45 eorq zp 46 lsrq zp 47 48 49 4a lsrq 4b 4c 4d eorq abs16 4e lsrq abs16 4f -50 51 eorq (zp), y 52 eorq (zp) 53 -54 asrq zp, x 55 eorq zp, x 56 lsrq zp, x 57 -58 59 eorq abs16, y 5a 5b -5c 5d eorq abs16, x 5e lsrq abs16, x 5f +50 51 52 eorq (zp) 53 +54 asrq zp, x 55 56 lsrq zp, x 57 +58 59 5a 5b +5c 5d 5e lsrq abs16, x 5f -60 61 adcq (zp, x) 62 63 +60 61 62 63 64 65 adcq zp 66 rorq zp 67 68 69 6a rorq 6b 6c 6d adcq abs16 6e rorq abs16 6f -70 71 adcq (zp), y 72 adcq (zp) 73 -74 75 adcq zp, x 76 rorq zp, x 77 -78 79 adcq abs16, y 7a 7b -7c 7d adcq abs16, x 7e rorq abs16, x 7f +70 71 72 adcq (zp) 73 +74 75 76 rorq zp, x 77 +78 79 7a 7b +7c 7d 7e rorq abs16, x 7f -80 81 stq (zp, x) 82 stq (zp, s), y 83 +80 81 82 83 84 85 stq zp 86 87 88 89 8a 8b 8c 8d stq abs16 8e 8f -90 91 stq (zp), y 92 stq (zp) 93 -94 95 stq zp, x 96 97 -98 99 stq abs16, y 9a 9b -9c 9d stq abs16, x 9e 9f +90 91 92 stq (zp) 93 +94 95 96 97 +98 99 9a 9b +9c 9d 9e 9f -a0 a1 ldq (zp, x) a2 a3 +a0 a1 a2 a3 a4 a5 ldq zp a6 a7 a8 a9 aa ab ac ad ldq abs16 ae af @@ -71,23 +71,23 @@ b4 b5 ldq zp, x b6 b7 b8 b9 ldq abs16, y ba bb bc bd ldq abs16, x be bf -c0 c1 cpq (zp, x) c2 c3 +c0 c1 c2 c3 c4 c5 cpq zp c6 deq zp c7 c8 c9 ca cb cc cd cpq abs16 ce deq abs16 cf -d0 d1 cpq (zp), y d2 cpq (zp) d3 -d4 d5 cpq zp, x d6 deq zp, x d7 -d8 d9 cpq abs16, y da db -dc dd cpq abs16, x de deq abs16, x df +d0 d1 d2 cpq (zp) d3 +d4 d5 d6 deq zp, x d7 +d8 d9 da db +dc dd de deq abs16, x df -e0 e1 sbcq (zp, x) e2 ldq (zp, s), y e3 +e0 e1 e2 ldq (zp, s), y e3 e4 e5 sbcq zp e6 inq zp e7 e8 e9 ea eb ec ed sbcq abs16 ee inq abs16 ef -f0 f1 sbcq (zp), y f2 sbcq (zp) f3 -f4 f5 sbcq zp, x f6 inq zp, x f7 -f8 f9 sbcq abs16, y fa fb -fc fd sbcq abs16, x fe inq abs16, x ff +f0 f1 f2 sbcq (zp) f3 +f4 f5 f6 inq zp, x f7 +f8 f9 fa fb +fc fd fe inq abs16, x ff zp: 8-bit zeropage address abs16: 16-bit absolute address diff --git a/src/mnemo.c b/src/mnemo.c index 5ab67a4..ed20b98 100644 --- a/src/mnemo.c +++ b/src/mnemo.c @@ -78,6 +78,8 @@ enum mnemogroup { // TODO: make sure groups like IMPLIEDONLY and ZPONLY output // "Mnemonic does not support this addressing mode" instead of // "Garbage data at end of statement". +// TODO: maybe add GROUP_IMMEDIATEONLY? +// (for RTN, REP, SEP, ANC, ALR, ARR, SBX, LXA, ANE, SAC, SIR) // save some space #define SCB static const unsigned char @@ -94,13 +96,13 @@ enum mnemogroup { enum { IDX_ORA,IDXcORA,IDX16ORA,IDXeORA,IDXmORA,IDXmORQ,IDX_AND,IDXcAND,IDX16AND,IDXeAND,IDXmAND,IDXmANDQ,IDX_EOR,IDXcEOR,IDX16EOR,IDXeEOR,IDXmEOR,IDXmEORQ,IDX_ADC,IDXcADC,IDX16ADC,IDXeADC,IDXmADC,IDXmADCQ,IDX_STA,IDXcSTA,IDX16STA,IDXeSTA,IDXmSTA,IDXmSTQ,IDX_LDA,IDXcLDA,IDX16LDA,IDXeLDA,IDXmLDA,IDXmLDQ,IDX_CMP,IDXcCMP,IDX16CMP,IDXeCMP,IDXmCMP,IDXmCPQ,IDX_SBC,IDXcSBC,IDX16SBC,IDXeSBC,IDXmSBC,IDXmSBCQ,IDX16PEI,IDXuSLO,IDXuRLA,IDXuSRE,IDXuRRA,IDXuSAX,IDXuLAX,IDXuDCP,IDXuISC,IDXuSHA}; SCB accu_imm[] = { 0x09, 0x09, 0x09, 0x09, 0x09, 0, 0x29, 0x29, 0x29, 0x29, 0x29, 0, 0x49, 0x49, 0x49, 0x49, 0x49, 0, 0x69, 0x69, 0x69, 0x69, 0x69, 0, 0, 0, 0, 0, 0, 0, 0xa9, 0xa9, 0xa9, 0xa9, 0xa9, 0, 0xc9, 0xc9, 0xc9, 0xc9, 0xc9, 0, 0xe9, 0xe9, 0xe9, 0xe9, 0xe9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; // #$ff #$ffff SCL accu_abs[] = { 0x0d05, 0x0d05,0x0f0d05, 0x0d05, 0x0d05, 0x0d05, 0x2d25, 0x2d25,0x2f2d25, 0x2d25, 0x2d25, 0x2d25, 0x4d45, 0x4d45,0x4f4d45, 0x4d45, 0x4d45, 0x4d45, 0x6d65, 0x6d65,0x6f6d65, 0x6d65, 0x6d65, 0x6d65, 0x8d85, 0x8d85,0x8f8d85, 0x8d85, 0x8d85, 0x8d85, 0xada5, 0xada5,0xafada5, 0xada5, 0xada5, 0xada5, 0xcdc5, 0xcdc5,0xcfcdc5, 0xcdc5, 0xcdc5, 0xcdc5, 0xede5, 0xede5,0xefede5, 0xede5, 0xede5, 0xede5, 0, 0x0f07, 0x2f27, 0x4f47, 0x6f67, 0x8f87, 0xafa7, 0xcfc7, 0xefe7, 0}; // $ff $ffff $ffffff -SCL accu_xabs[] = { 0x1d15, 0x1d15,0x1f1d15, 0x1d15, 0x1d15, 0x1d15, 0x3d35, 0x3d35,0x3f3d35, 0x3d35, 0x3d35, 0x3d35, 0x5d55, 0x5d55,0x5f5d55, 0x5d55, 0x5d55, 0x5d55, 0x7d75, 0x7d75,0x7f7d75, 0x7d75, 0x7d75, 0x7d75, 0x9d95, 0x9d95,0x9f9d95, 0x9d95, 0x9d95, 0x9d95, 0xbdb5, 0xbdb5,0xbfbdb5, 0xbdb5, 0xbdb5, 0xbdb5, 0xddd5, 0xddd5,0xdfddd5, 0xddd5, 0xddd5, 0xddd5, 0xfdf5, 0xfdf5,0xfffdf5, 0xfdf5, 0xfdf5, 0xfdf5, 0, 0x1f17, 0x3f37, 0x5f57, 0x7f77, 0, 0, 0xdfd7, 0xfff7, 0}; // $ff,x $ffff,x $ffffff,x -SCS accu_yabs[] = { 0x1900, 0x1900, 0x1900, 0x1900, 0x1900, 0x1900, 0x3900, 0x3900, 0x3900, 0x3900, 0x3900, 0x3900, 0x5900, 0x5900, 0x5900, 0x5900, 0x5900, 0x5900, 0x7900, 0x7900, 0x7900, 0x7900, 0x7900, 0x7900, 0x9900, 0x9900, 0x9900, 0x9900, 0x9900, 0x9900, 0xb900, 0xb900, 0xb900, 0xb900, 0xb900, 0xb900, 0xd900, 0xd900, 0xd900, 0xd900, 0xd900, 0xd900, 0xf900, 0xf900, 0xf900, 0xf900, 0xf900, 0xf900, 0, 0x1b00, 0x3b00, 0x5b00, 0x7b00, 0x97, 0xbfb7, 0xdb00, 0xfb00, 0x9f00}; // $ff,y $ffff,y -SCB accu_xind8[] = { 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21, 0x41, 0x41, 0x41, 0x41, 0x41, 0x41, 0x61, 0x61, 0x61, 0x61, 0x61, 0x61, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0xa1, 0xa1, 0xa1, 0xa1, 0xa1, 0xa1, 0xc1, 0xc1, 0xc1, 0xc1, 0xc1, 0xc1, 0xe1, 0xe1, 0xe1, 0xe1, 0xe1, 0xe1, 0, 0x03, 0x23, 0x43, 0x63, 0x83, 0xa3, 0xc3, 0xe3, 0}; // ($ff,x) -SCB accu_indy8[] = { 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0xb1, 0xb1, 0xb1, 0xb1, 0xb1, 0xb1, 0xd1, 0xd1, 0xd1, 0xd1, 0xd1, 0xd1, 0xf1, 0xf1, 0xf1, 0xf1, 0xf1, 0xf1, 0, 0x13, 0x33, 0x53, 0x73, 0, 0xb3, 0xd3, 0xf3, 0x93}; // ($ff),y +SCL accu_xabs[] = { 0x1d15, 0x1d15,0x1f1d15, 0x1d15, 0x1d15, 0, 0x3d35, 0x3d35,0x3f3d35, 0x3d35, 0x3d35, 0, 0x5d55, 0x5d55,0x5f5d55, 0x5d55, 0x5d55, 0, 0x7d75, 0x7d75,0x7f7d75, 0x7d75, 0x7d75, 0, 0x9d95, 0x9d95,0x9f9d95, 0x9d95, 0x9d95, 0, 0xbdb5, 0xbdb5,0xbfbdb5, 0xbdb5, 0xbdb5, 0xbdb5, 0xddd5, 0xddd5,0xdfddd5, 0xddd5, 0xddd5, 0, 0xfdf5, 0xfdf5,0xfffdf5, 0xfdf5, 0xfdf5, 0, 0, 0x1f17, 0x3f37, 0x5f57, 0x7f77, 0, 0, 0xdfd7, 0xfff7, 0}; // $ff,x $ffff,x $ffffff,x +SCS accu_yabs[] = { 0x1900, 0x1900, 0x1900, 0x1900, 0x1900, 0, 0x3900, 0x3900, 0x3900, 0x3900, 0x3900, 0, 0x5900, 0x5900, 0x5900, 0x5900, 0x5900, 0, 0x7900, 0x7900, 0x7900, 0x7900, 0x7900, 0, 0x9900, 0x9900, 0x9900, 0x9900, 0x9900, 0, 0xb900, 0xb900, 0xb900, 0xb900, 0xb900, 0xb900, 0xd900, 0xd900, 0xd900, 0xd900, 0xd900, 0, 0xf900, 0xf900, 0xf900, 0xf900, 0xf900, 0, 0, 0x1b00, 0x3b00, 0x5b00, 0x7b00, 0x97, 0xbfb7, 0xdb00, 0xfb00, 0x9f00}; // $ff,y $ffff,y +SCB accu_xind8[] = { 0x01, 0x01, 0x01, 0x01, 0x01, 0, 0x21, 0x21, 0x21, 0x21, 0x21, 0, 0x41, 0x41, 0x41, 0x41, 0x41, 0, 0x61, 0x61, 0x61, 0x61, 0x61, 0, 0x81, 0x81, 0x81, 0x81, 0x81, 0, 0xa1, 0xa1, 0xa1, 0xa1, 0xa1, 0, 0xc1, 0xc1, 0xc1, 0xc1, 0xc1, 0, 0xe1, 0xe1, 0xe1, 0xe1, 0xe1, 0, 0, 0x03, 0x23, 0x43, 0x63, 0x83, 0xa3, 0xc3, 0xe3, 0}; // ($ff,x) +SCB accu_indy8[] = { 0x11, 0x11, 0x11, 0x11, 0x11, 0, 0x31, 0x31, 0x31, 0x31, 0x31, 0, 0x51, 0x51, 0x51, 0x51, 0x51, 0, 0x71, 0x71, 0x71, 0x71, 0x71, 0, 0x91, 0x91, 0x91, 0x91, 0x91, 0, 0xb1, 0xb1, 0xb1, 0xb1, 0xb1, 0xb1, 0xd1, 0xd1, 0xd1, 0xd1, 0xd1, 0, 0xf1, 0xf1, 0xf1, 0xf1, 0xf1, 0, 0, 0x13, 0x33, 0x53, 0x73, 0, 0xb3, 0xd3, 0xf3, 0x93}; // ($ff),y SCB accu_ind8[] = { 0, 0x12, 0x12, 0, 0, 0x12, 0, 0x32, 0x32, 0, 0, 0x32, 0, 0x52, 0x52, 0, 0, 0x52, 0, 0x72, 0x72, 0, 0, 0x72, 0, 0x92, 0x92, 0, 0, 0x92, 0, 0xb2, 0xb2, 0, 0, 0xb2, 0, 0xd2, 0xd2, 0, 0, 0xd2, 0, 0xf2, 0xf2, 0, 0, 0xf2, 0xd4, 0, 0, 0, 0, 0, 0, 0, 0, 0}; // ($ff) SCB accu_sabs8[] = { 0, 0, 0x03, 0, 0, 0, 0, 0, 0x23, 0, 0, 0, 0, 0, 0x43, 0, 0, 0, 0, 0, 0x63, 0, 0, 0, 0, 0, 0x83, 0, 0, 0, 0, 0, 0xa3, 0, 0, 0, 0, 0, 0xc3, 0, 0, 0, 0, 0, 0xe3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; // $ff,s -SCB accu_sindy8[] = { 0, 0, 0x13, 0, 0, 0, 0, 0, 0x33, 0, 0, 0, 0, 0, 0x53, 0, 0, 0, 0, 0, 0x73, 0, 0, 0, 0, 0, 0x93, 0x82, 0x82, 0x82, 0, 0, 0xb3, 0xe2, 0xe2, 0xe2, 0, 0, 0xd3, 0, 0, 0, 0, 0, 0xf3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; // ($ff,s),y +SCB accu_sindy8[] = { 0, 0, 0x13, 0, 0, 0, 0, 0, 0x33, 0, 0, 0, 0, 0, 0x53, 0, 0, 0, 0, 0, 0x73, 0, 0, 0, 0, 0, 0x93, 0x82, 0x82, 0, 0, 0, 0xb3, 0xe2, 0xe2, 0xe2, 0, 0, 0xd3, 0, 0, 0, 0, 0, 0xf3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; // ($ff,s),y SCB accu_lind8[] = { 0, 0, 0x07, 0, 0, 0x12, 0, 0, 0x27, 0, 0, 0x32, 0, 0, 0x47, 0, 0, 0x52, 0, 0, 0x67, 0, 0, 0x72, 0, 0, 0x87, 0, 0, 0x92, 0, 0, 0xa7, 0, 0, 0xb2, 0, 0, 0xc7, 0, 0, 0xd2, 0, 0, 0xe7, 0, 0, 0xf2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; // [$ff] SCB accu_lindy8[] = { 0, 0, 0x17, 0, 0, 0, 0, 0, 0x37, 0, 0, 0, 0, 0, 0x57, 0, 0, 0, 0, 0, 0x77, 0, 0, 0, 0, 0, 0x97, 0, 0, 0, 0, 0, 0xb7, 0, 0, 0, 0, 0, 0xd7, 0, 0, 0, 0, 0, 0xf7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; // [$ff],y SCB accu_indz8[] = { 0, 0, 0, 0x12, 0x12, 0, 0, 0, 0, 0x32, 0x32, 0, 0, 0, 0, 0x52, 0x52, 0, 0, 0, 0, 0x72, 0x72, 0, 0, 0, 0, 0x92, 0x92, 0, 0, 0, 0, 0xb2, 0xb2, 0, 0, 0, 0, 0xd2, 0xd2, 0, 0, 0, 0, 0xf2, 0xf2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; // ($ff),z @@ -117,7 +119,7 @@ enum { IDX_ASL,IDX_ROL,IDX_LSR,IDX_ROR,IDX_LDY,IDX_LDX,IDX_CPY,IDX_C SCB misc_impl[] = { 0x0a, 0x2a, 0x4a, 0x6a, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x3a, 0, 0x1a, 0, 0, 0, 0x43, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0xea, 0x80, 0x0c, 0, 0, 0, 0, 0, 0, 0, 0}; // implied/accu SCB misc_imm[] = { 0, 0, 0, 0, 0xa0, 0xa2, 0xc0, 0xe0, 0, 0x89, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0xc2, 0xa3, 0xf4, 0, 0x62, /*2?*/0, 0xc2, 0xe2, 0, 0x0b, 0x4b, 0x6b, 0xcb, 0x80, 0x80, 0, 0xab, 0x8b, 0, 0, 0, 0, 0x32, 0x42}; // #$ff #$ffff SCS misc_abs[] = { 0x0e06, 0x2e26, 0x4e46, 0x6e66, 0xaca4, 0xaea6, 0xccc4, 0xece4, 0x2c24, 0x2c24, 0x2c24, 0x8e86, 0x8e86, 0x8c84, 0x8c84, 0xcec6, 0xcec6, 0xeee6, 0xeee6, 0x0c04, 0x1c14, 0x9c64, 0x44, 0xcb00, 0xdcd4, 0xab00, 0xfc00, 0xeb00, 0, 0x02, 0, 0, 0xf400, 0, 0, 0, 0, 0x0c04, 0x04, 0x0c00, 0, 0, 0, 0, 0, 0, 0, 0}; // $ff $ffff -SCS misc_xabs[] = { 0x1e16, 0x3e36, 0x5e56, 0x7e76, 0xbcb4, 0, 0, 0, 0, 0x3c34, 0x3c34, 0, 0, 0x94, 0x8b94, 0xded6, 0xded6, 0xfef6, 0xfef6, 0, 0, 0x9e74, 0x54, 0, 0, 0xbb00, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x1c14, 0x14, 0x1c00, 0, 0, 0, 0, 0, 0x9c00, 0, 0}; // $ff,x $ffff,x +SCS misc_xabs[] = { 0x1e16, 0x3e36, 0x5e56, 0x7e76, 0xbcb4, 0, 0, 0, 0, 0x3c34, 0, 0, 0, 0x94, 0x8b94, 0xded6, 0xded6, 0xfef6, 0xfef6, 0, 0, 0x9e74, 0x54, 0, 0, 0xbb00, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x1c14, 0x14, 0x1c00, 0, 0, 0, 0, 0, 0x9c00, 0, 0}; // $ff,x $ffff,x SCS misc_yabs[] = { 0, 0, 0, 0, 0, 0xbeb6, 0, 0, 0, 0, 0, 0x96, 0x9b96, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0xbb00, 0x9b00, 0x9e00, 0, 0, 0}; // $ff,y $ffff,y // Code tables for group GROUP_ALLJUMPS: @@ -490,7 +492,7 @@ static struct ronode mnemos_m65[] = { // ...now BITQ // ASR // ...now ASRQ - // it works with all addressing modes (beware of index register usage!) + // it works with most addressing modes (beware of index register usage!) // except for immediate addressing and "($ff),z", which becomes "($ff)" // extension 3: // extensions 1 and 2 can be combined (NEG:NEG:NOP prefix), then diff --git a/src/version.h b/src/version.h index 00e7400..dbd9a1b 100644 --- a/src/version.h +++ b/src/version.h @@ -9,7 +9,7 @@ #define RELEASE "0.97" // update before release FIXME #define CODENAME "Zem" // update before release -#define CHANGE_DATE "29 Jul" // update before release FIXME +#define CHANGE_DATE "30 Jul" // update before release FIXME #define CHANGE_YEAR "2020" // update before release //#define HOME_PAGE "http://home.pages.de/~mac_bacon/smorbrod/acme/" #define HOME_PAGE "http://sourceforge.net/p/acme-crossass/" // FIXME diff --git a/testing/cpus/expected-m65.o b/testing/cpus/expected-m65.o index 5917e0c4c533a36997c5842119f2ef826b530569..9e4e715d49aff4db0780831a6257323b62e8e68f 100644 GIT binary patch delta 207 zcmZ3&@sn+XHq&H%CQ&{iAtxs>Q70!UCnq^M*~uA93iU=nAv2(mm6Ma5oUD_Rvy+nx ztCN!}5W4}fmy?q(AFq>>ABYG7stp0E4Flphkm6LJiZme3a&pQADaZp6ML<<$KoxZ$ z6|F$oUXbV{py*N{XDx`cQP9b06Hs8Q=;Rz`9@(Qn@nb-I79@8LL|g(&UIUtO59rGE R%o1#$fc$TwlkYRT0s#1uHWB~; delta 393 zcmWlTK`TU27=}AncaoZ^IW_94dopXy!h|BDyz5DsP!^O03q_ft6ed%a7UpJQVKL1_(nSMY@1=CJkgX*(_i!kjnwx zB#I)S2Z&t^I8ELp6G3mGpJI{X0Hr}PM201g0Hg9snla6|Nwxx4n`BX8F-3El%#c|X zbCTvY3w&#lFD;Q}U_~FTYS!3R*{-wMAe-v8mF#GC+12a79=m<{2lN~C59uDsJ$50z zrb!-xeC?e21=UM(CH-1+!{(OF9h-adsP0MUpEWOxS}ov}(HnVJ^P%}<_{H#>(GO`W a{8jVkVsEW4T3@lgYJJ1{GwYLbN8uluU25w9 diff --git a/testing/cpus/test-m65.a b/testing/cpus/test-m65.a index 6ea63a0..d49ef19 100644 --- a/testing/cpus/test-m65.a +++ b/testing/cpus/test-m65.a @@ -13,21 +13,22 @@ M65 = 1 ; make next include skip the NOP mnemonic (re-used as prefix code by M65 eom ; $ea, "end of mapping" ; "quad mode" m65 extension using NEG:NEG prefix: - orq ($01, x) ; 01 + ; (instructions that are commented out might be re-purposed later) + ;orq ($01, x) ; 01 orq $05 ; 05 aslq $05 ; 06 aslq ; 0a orq $0d0e ; 0d aslq $0d0e ; 0e - orq ($11), y ; 11 + ;orq ($11), y ; 11 orq ($12) ; 12 - orq $15, x ; 15 + ;orq $15, x ; 15 aslq $15, x ; 16 - orq $1919, y ; 19 + ;orq $1919, y ; 19 inq ; 1a - orq $1d1e, x ; 1d + ;orq $1d1e, x ; 1d aslq $1d1e, x ; 1e - andq ($01, x) ; 21 + ;andq ($01, x) ; 21 bitq $05 ; 24 andq $05 ; 25 rolq $05 ; 26 @@ -35,17 +36,17 @@ M65 = 1 ; make next include skip the NOP mnemonic (re-used as prefix code by M65 bitq $0d0e ; 2c andq $0d0e ; 2d rolq $0d0e ; 2e - andq ($11), y ; 31 + ;andq ($11), y ; 31 andq ($12) ; 32 - bitq $15, x ; 34 - andq $15, x ; 35 + ;bitq $15, x ; 34 + ;andq $15, x ; 35 rolq $15, x ; 36 - andq $1919, y ; 39 + ;andq $1919, y ; 39 deq ; 3a - bitq $1d1e, x ; 3c - andq $1d1e, x ; 3d + ;bitq $1d1e, x ; 3c + ;andq $1d1e, x ; 3d rolq $1d1e, x ; 3e - eorq ($01, x) ; 41 + ;eorq ($01, x) ; 41 asrq ; 43 asrq $05 ; 44 eorq $05 ; 45 @@ -53,37 +54,37 @@ M65 = 1 ; make next include skip the NOP mnemonic (re-used as prefix code by M65 lsrq ; 4a eorq $0d0e ; 4d lsrq $0d0e ; 4e - eorq ($11), y ; 51 + ;eorq ($11), y ; 51 eorq ($12) ; 52 asrq $15, x ; 54 - eorq $15, x ; 55 + ;eorq $15, x ; 55 lsrq $15, x ; 56 - eorq $1919, y ; 59 - eorq $1d1e, x ; 5d + ;eorq $1919, y ; 59 + ;eorq $1d1e, x ; 5d lsrq $1d1e, x ; 5e - adcq ($01, x) ; 61 + ;adcq ($01, x) ; 61 adcq $05 ; 65 rorq $05 ; 66 rorq ; 6a adcq $0d0e ; 6d rorq $0d0e ; 6e - adcq ($11), y ; 71 + ;adcq ($11), y ; 71 adcq ($12) ; 72 - adcq $15, x ; 75 + ;adcq $15, x ; 75 rorq $15, x ; 76 - adcq $1919, y ; 79 - adcq $1d1e, x ; 7d + ;adcq $1919, y ; 79 + ;adcq $1d1e, x ; 7d rorq $1d1e, x ; 7e - stq ($01, x) ; 81 - stq ($82, s), y ; 82 + ;stq ($01, x) ; 81 + ;stq ($82, s), y ; 82 stq $05 ; 85 stq $0d0e ; 8d - stq ($11), y ; 91 + ;stq ($11), y ; 91 stq ($12) ; 92 - stq $15, x ; 95 - stq $1919, y ; 99 - stq $1d1e, x ; 9d - ldq ($01, x) ; a1 + ;stq $15, x ; 95 + ;stq $1919, y ; 99 + ;stq $1d1e, x ; 9d + ;ldq ($01, x) ; a1 ldq $05 ; a5 ldq $0d0e ; ad ldq ($11), y ; b1 @@ -91,30 +92,30 @@ M65 = 1 ; make next include skip the NOP mnemonic (re-used as prefix code by M65 ldq $15, x ; b5 ldq $1919, y ; b9 ldq $1d1e, x ; bd - cpq ($01, x) ; c1 + ;cpq ($01, x) ; c1 cpq $05 ; c5 deq $05 ; c6 cpq $0d0e ; cd deq $0d0e ; ce - cpq ($11), y ; d1 + ;cpq ($11), y ; d1 cpq ($12) ; d2 - cpq $15, x ; d5 + ;cpq $15, x ; d5 deq $15, x ; d6 - cpq $1919, y ; d9 - cpq $1d1e, x ; dd + ;cpq $1919, y ; d9 + ;cpq $1d1e, x ; dd deq $1d1e, x ; de - sbcq ($01, x) ; e1 + ;sbcq ($01, x) ; e1 ldq ($e2, s), y ; e2 sbcq $05 ; e5 inq $05 ; e6 sbcq $0d0e ; ed inq $0d0e ; ee - sbcq ($11), y ; f1 + ;sbcq ($11), y ; f1 sbcq ($12) ; f2 - sbcq $15, x ; f5 + ;sbcq $15, x ; f5 inq $15, x ; f6 - sbcq $1919, y ; f9 - sbcq $1d1e, x ; fd + ;sbcq $1919, y ; f9 + ;sbcq $1d1e, x ; fd inq $1d1e, x ; fe ; "long mode" m65 extension using NOP prefix: ora [$12], z ; 12