mirror of
https://github.com/uffejakobsen/acme.git
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0e66c1fcb2
Added "c64dtv2" cpu type so you can use its SIR, SAC and BRA opcodes;
along with the undocumented ("illegal") opcodes of the 6510.
Added Martin Piper's "--msvc" patch so error output can be configured
to be in Visual Studio format. Thanks Martin!
Merged third-party patch of unknown origin to output label dump in VICE
format. Still needs work to be configurable about the types of
symbols actually output.
git-svn-id: https://svn.code.sf.net/p/acme-crossass/code-0/trunk@41 4df02467-bbd4-4a76-a152-e7ce94205b78
143 lines
6.2 KiB
Plaintext
143 lines
6.2 KiB
Plaintext
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ACME
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...the ACME Crossassembler for Multiple Environments
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--- Undocumented ("illegal") opcodes ---
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In release 0.87, support for some of the undocumented opcodes of the
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6502 processor was added.
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In release 0.89, some more were added.
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In release 0.94.8, another one was added (lxa).
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In release 0.95.3, C64DTV2 support was added, which includes these
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opcodes as well.
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Here are the mnemonics, addressing modes and generated opcodes:
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| addressing mode |
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Mnemo | 8 8,x 8,y 16 16,x 16,y (8,x) (8),y | performs:
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------+--------------------------------------------------+-----------
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slo | 07 17 -- 0f 1f 1b 03 13 | asl + ora
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rla | 27 37 -- 2f 3f 3b 23 33 | rol + and
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sre | 47 57 -- 4f 5f 5b 43 53 | lsr + eor
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rra | 67 77 -- 6f 7f 7b 63 73 | ror + adc
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sax | 87 -- 97 8f -- -- 83 -- | stx + sta
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lax | a7 -- b7 af -- bf a3 b3 | ldx + lda
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dcp | c7 d7 -- cf df db c3 d3 | dec + cmp
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isc | e7 f7 -- ef ff fb e3 f3 | inc + sbc
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| addressing mode |
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Mnemo | implied #8 8 8,x 16 16,x | performs:
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------+-------------------------------------+------------------------
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anc | -- 0b* -- -- -- -- | A = A & arg, then C=N
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asr | -- 4b -- -- -- -- | A = A & arg, then lsr
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arr | -- 6b -- -- -- -- | A = A & arg, then ror
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sbx | -- cb -- -- -- -- | X = (A & X) - arg
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dop | 80** 80 04 14 -- -- | skips next byte
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top | 0c** -- -- -- 0c 1c | skips next two bytes
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jam | 02 -- -- -- -- -- | crash (wait for reset)
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lxa | -- ab*** -- -- -- -- | A/X = (A | ??) & arg
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Example:
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!cpu 6510 ; activate additional mnemonics...
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lax (some_zp_label,x) ; ...and use them. No, this
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dcp (other_zp_label),y ; example does not make sense.
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*) Up until ACME version 0.95.1, anc#8 generated opcode 0x2b. Since
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ACME version 0.95.2, anc#8 generates opcode 0x0b. Both opcodes work
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the same way on a 6510. I am told 0x2b does not work on the C64DTV2.
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**) Note that "dop" and "top" can be used with implied addressing, but
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the generated opcodes are those for immediate and 16-bit absolute
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addressing, respectively. Using dop/top with x-indexed addressing
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might have its uses when timing is critical (crossing a page border
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adds a penalty cycle).
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***) This opcode is said to first perform an ORA with an arbitrary(!)
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value, then do an AND with the given argument, then do a TAX.
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This means it is unstable and therefore useless - unless the given
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argument is zero, in which case it reliably clears both A and X.
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There is no guarantee that these opcodes actually work on a given 6502
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(or 6510, or 8500, or 8502) CPU. But as far as I know, nobody ever
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found an unmodified C64/C128 where these illegals didn't work. That's
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why I used "6510" as the CPU keyword instead of "6502illegal" or
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something like that.
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These illegals will definitely *not* work on 65c02 and 65816 CPUs. But
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I really should not have to tell you that ;)
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Because there are no official mnemonics for these opcodes, different
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people use different names for them. I hope my choices are not too
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exotic for your taste.
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Just for the sake of completeness: Here are all the remaining opcodes
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(the ones ACME won't generate even with "6510" cpu):
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Opcode| Description C64DTV2
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------+--------------------------------------------------------------
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12 | same as 02 and others jam CRASH bra rel
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1a | same as (*legal*) ea nop
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22 | same as 02 and others jam CRASH
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2b | same as 0b anc #8 dop
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32 | same as 02 and others jam CRASH sac #8
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34 | same as 14 and others dop 8,x
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3a | same as (*legal*) ea nop
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3c | same as 1c and others top 16,x
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42 | same as 02 and others jam CRASH sir #8
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44 | same as 04 dop 8
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52 | same as 02 and others jam CRASH
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54 | same as 14 and others dop 8,x
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5a | same as (*legal*) ea nop
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5c | same as 1c and others top 16,x
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62 | same as 02 and others jam CRASH
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64 | same as 04 dop 8
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72 | same as 02 and others jam CRASH
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74 | same as 14 and others dop 8,x
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7a | same as (*legal*) ea nop
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7c | same as 1c and others top 16,x
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82 | same as c2/e2 dop #8, but said to CRASH sometimes
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89 | same as 80 dop #8
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8b | see notes below
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92 | same as 02 and others jam CRASH
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93 | see notes below
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9b | see notes below
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9c | see notes below
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9e | see notes below
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9f | see notes below
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b2 | same as 02 and others jam CRASH
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bb | see notes below
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c2 | same as 82/e2 dop #8, but said to CRASH sometimes
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d2 | same as 02 and others jam CRASH
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d4 | same as 14 and others dop 8,x
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da | same as (*legal*) ea nop
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dc | same as 1c and others top 16,x
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e2 | same as 82/c2 dop #8, but said to CRASH sometimes
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eb | same as (*legal*) e9 sbc #8
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f2 | same as 02 and others jam CRASH
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f4 | same as 14 and others dop 8,x
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fa | same as (*legal*) ea nop
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fc | same as 1c and others top 16,x
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Concerning opcodes 8b, 93, 9b, 9c, 9e, 9f, bb:
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These opcodes are said to be unstable. For more information about what
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they do, see these documents:
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John West, Marko Mäkelä. '64doc' file, 1994/06/03.
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Extra Instructions Of The 65XX Series CPU, Adam Vardy, 27 Sept. 1996
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6502 Undocumented Opcodes, by Freddy Offenga, 5/17/1997
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AAY64 (All About Your 64)
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I did not see much point in assigning mnemonics for these opcodes. The
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reference documents above call them:
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8b: ane, xaa
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93: sha, axa, ahx
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9b: shs, tas, xas
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9c: shy, say, sya
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9e: shx, xas, sxa
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9f: sha, axa, ahx
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bb: las, lar, lae
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