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42d71284a8
git-svn-id: https://svn.code.sf.net/p/acme-crossass/code-0/trunk@377 4df02467-bbd4-4a76-a152-e7ce94205b78
119 lines
5.9 KiB
Plaintext
119 lines
5.9 KiB
Plaintext
;ACME 0.95
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!ifdef lib_cbm_c64_reu_a !eof
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lib_cbm_c64_reu_a = 1
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; This file contains definitions for accessing a RAM Expansion Unit (REU) of
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; type 1700, 1764, 1750 and compatible. These units contain a chip called REC
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; (RAM Expansion Controller) capable of direct memory access (DMA).
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; Standard base address of control registers is $df00 in i/o space.
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!address {
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; status register
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rec_status = $df00 ; reading will clear IRQ, END and ERROR bits
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}
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rec_STATUS_IRQ = %#.......
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rec_STATUS_END = %.#......
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rec_STATUS_ERROR = %..#..... ; for verify command
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rec_STATUS_TYPE = %...#.... ; chip type (do not use to determine unit size!)
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rec_STATUS_VERSION = %....#### ; always zero
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!address {
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; command register
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rec_command = $df01
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}
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rec_COMMAND_EXECUTE = %#....... ; setting this starts the operation
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;reserved = %.#...... ; register bit exists, but does nothing
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rec_COMMAND_RELOAD = %..#..... ; reload address registers when done (do not use in verify mode, because you want the address in case of an error!)
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rec_COMMAND_IMMEDIATELY = %...#.... ; do not wait for $ff00 write
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;reserved = %....##.. ; register bits exist, but do nothing
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rec_COMMAND_MODE_MASK = %......## ; bit mask for the four modes
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rec_COMMAND_MODE_STASH = %........ ; computer-to-REU
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rec_COMMAND_MODE_FETCH = %.......# ; REU-to-computer
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rec_COMMAND_MODE_SWAP = %......#. ; exchange
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rec_COMMAND_MODE_VERIFY = %......## ; compare
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rec_COMMAND_STASH = %#.#..... ; these wait for $ff00 before
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rec_COMMAND_FETCH = %#.#....# ; starting and then reload values.
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!address {
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; internal address (computer RAM)
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rec_int_low = $df02
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rec_int_high = $df03
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; external address (expansion RAM)
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rec_ext_low = $df04
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rec_ext_high = $df05
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rec_ext_bank = $df06 ; upper five bits always read as 1
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; A stock 1700 unit has two banks (128 KiB).
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; A stock 1764 unit has four banks (256 KiB).
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; A stock 1750 unit has eight banks (512 KiB).
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; Upgraded units and clones may have more, but the REC chip will always
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; "wrap around" after eight banks if crossing bank borders!
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; amount of bytes to process
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rec_amount_low = $df07 ; using $0000 results in
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rec_amount_high = $df08 ; 64 KiB being transferred
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; when to request interrupts
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rec_irqctrl = $df09 ; lower five bits always read as 1
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}
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rec_IRQCTRL_ENABLE = %#.......
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rec_IRQCTRL_ON_END = %.#......
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rec_IRQCTRL_ON_ERROR = %..#..... ; for verify errors
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!address {
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; address control (set to zero for normal operation)
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rec_addrctrl = $df0a ; lower six bits always read as 1
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}
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rec_ADDRCTRL_FIX_INT = %#.......
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rec_ADDRCTRL_FIX_EXT = %.#......
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; $df0b..$df1f always read as $ff,
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; at $df20 the registers repeat.
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; these "32 registers" are visible 8 times in the $df00 page.
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; The REC is labeled "MOS 8726R1" and was available as a giant (64-pin) DIP
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; version and as a 68-pin quad-pack version. Both packages seem to contain the
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; same die, but because of the different number of pins, they are bonded
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; slightly differently.
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; Pinouts:
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;
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; DIP version
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; ____ ____ /reset 1
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; | V | /irq 2 | 68 n.c.
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; /reset | 1 64 | vcc dotclk 3 \ | / 67 vcc
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; /irq | 2 63 | bs r/w 4 \ \ | / / 66 bs
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; dotclk | 3 62 | /cas1 1 MHz 5 \ \ \ | / / / 65 /cas1
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; r/w | 4 61 | /cas0 /cs 6 \ \ \ \ | / / / / 64 /cas0
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; 1 MHz | 5 60 | /ras1 /ba 7 \ \ \ \ \ | / / / / / 63 /ras1
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; /cs | 6 59 | /ras0 /dma 8 \ \ \ \ \ \ | / / / / / / 62 /ras0
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; /ba | 7 58 | /dwe d7 9 \ \ \ \ \ \ \ | / / / / / / / 61 /dwe
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; /dma | 8 57 | dd0 \_\_\_\_\_\_\_\_|_/_/_/_/_/_/_/_/
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; d7 | 9 56 | dd1 d6 10| o |60 dd0
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; d6 | 10 55 | dd2 d5 11| |59 dd1
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; d5 | 11 54 | dd3 d4 12| |58 dd2
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; d4 | 12 53 | dd4 d3 13| |57 dd3
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; d3 | 13 52 | dd5 d2 14| |56 dd4
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; d2 | 14 51 | dd6 d1 15| |55 dd5
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; d1 | 15 50 | dd7 d0 16| |54 dd6
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; d0 | 16 49 | vss n.c. 17| quad pack |53 dd7
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; vss | 17 48 | ma8 vss 18| |52 vss
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; a15 | 18 47 | ma7 a15 19| version |51 n.c.
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; a14 | 19 46 | ma6 a14 20| |50 ma8
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; a13 | 20 45 | ma5 a13 21| |49 ma7
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; a12 | 21 44 | ma4 a12 22| |48 ma6
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; a11 | 22 43 | ma3 a11 23| |47 ma5
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; a10 | 23 42 | ma2 a10 24| |46 ma4
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; a9 | 24 41 | ma1 a9 25| |45 ma3
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; a8 | 25 40 | ma0 a8 26|_________________________________|44 ma2
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; a7 | 26 39 | test / / / / / / / / | \ \ \ \ \ \ \ \
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; a6 | 27 38 | vss a7 27 / / / / / / / | \ \ \ \ \ \ \ 43 ma1
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; a5 | 28 37 | vcc a6 28 / / / / / / | \ \ \ \ \ \ 42 ma0
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; a4 | 29 36 | /romsel a5 29 / / / / / | \ \ \ \ \ 41 n.c.
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; a3 | 30 35 | /roml a4 30 / / / / | \ \ \ \ 40 test
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; a2 | 31 34 | /romh a3 31 / / / | \ \ \ 39 vss
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; a1 | 32 33 | a0 a2 32 / / | \ \ 38 vcc
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; |_________| a1 33 / | \ 37 /romsel
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; a0 34 | 36 /roml
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; 35 /romh
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;
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; Basically, half of the pins (the low numbers) are for talking to the c64/c128
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; and the other half (the high numbers) are for talking to the REU's own RAM.
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; "/romh", "/roml" and "/romsel" are just the inputs and the output of a simple
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; AND gate, the result is used to select the EPROM socket.
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