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cefa89c138
git-svn-id: https://svn.code.sf.net/p/acme-crossass/code-0/trunk@110 4df02467-bbd4-4a76-a152-e7ce94205b78
163 lines
6.8 KiB
Plaintext
163 lines
6.8 KiB
Plaintext
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65ce02 opcode table
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There are no more undocumented opcodes.
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All differences to the r65c02 are marked using '+' or '!' signs:
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'!' marks (backward-compatible) changes to existing instructions.
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'+' marks new instructions.
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00 brk 01 ora (zp, x) 02+ cle 03+ see
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04 tsb zp 05 ora zp 06 asl zp 07 rmb0 zp
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08 php 09 ora #imm8 0a asl 0b+ tsy
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0c tsb abs16 0d ora abs16 0e asl abs16 0f bbr0 zp, rel8
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10 bpl rel8 11 ora (zp), y 12! ora (zp), z 13+ bpl rel16
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14 trb zp 15 ora zp, x 16 asl zp, x 17 rmb1 zp
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18 clc 19 ora abs16, y 1a inc 1b+ inz
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1c trb abs16 1d ora abs16, x 1e asl abs16, x 1f bbr1 zp, rel8
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20 jsr abs16 21 and (zp, x) 22+ jsr (abs16) 23+ jsr (abs16, x)
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24 bit zp 25 and zp 26 rol zp 27 rmb2 zp
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28 plp 29 and #imm8 2a rol 2b+ tys
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2c bit abs16 2d and abs16 2e rol abs16 2f bbr2 zp, rel8
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30 bmi rel8 31 and (zp), y 32! and (zp), z 33+ bmi rel16
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34 bit zp, x 35 and zp, x 36 rol zp, x 37 rmb3 zp
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38 sec 39 and abs16, y 3a dec 3b+ dez
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3c bit abs16, x 3d and abs16, x 3e rol abs16, x 3f bbr3 zp, rel8
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40 rti 41 eor (zp, x) 42+ neg 43+ asr
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44+ asr zp 45 eor zp 46 lsr zp 47 rmb4 zp
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48 pha 49 eor #imm8 4a lsr 4b+ taz
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4c jmp abs16 4d eor abs16 4e lsr abs16 4f bbr4 zp, rel8
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50 bvc rel8 51 eor (zp), y 52! eor (zp), z 53+ bvc rel16
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54+ asr zp, x 55 eor zp, x 56 lsr zp, x 57 rmb5 zp
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58 cli 59 eor abs16, y 5a phy 5b+ tab
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5c+ aug 5d eor abs16, x 5e lsr abs16, x 5f bbr5 zp, rel8
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60 rts 61 adc (zp, x) 62+ rtn #imm8 63+ bsr rel16
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64! stz zp 65 adc zp 66 ror zp 67 rmb6 zp
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68 pla 69 adc #imm8 6a ror 6b+ tza
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6c jmp (abs16) 6d adc abs16 6e ror abs16 6f bbr6 zp, rel8
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70 bvs rel8 71 adc (zp), y 72! adc (zp), z 73+ bvs rel16
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74! stz zp, x 75 adc zp, x 76 ror zp, x 77 rmb7 zp
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78 sei 79 adc abs16, y 7a ply 7b+ tba
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7c jmp (abs16, x) 7d adc abs16, x 7e ror abs16, x 7f bbr7 zp, rel8
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80 bra rel8 81 sta (zp, x) 82+ sta (o8, s), y 83+ bra rel16
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84 sty zp 85 sta zp 86 stx zp 87 smb0 zp
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88 dey 89 bit #imm8 8a txa 8b+ sty abs16, x
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8c sty abs16 8d sta abs16 8e stx abs16 8f bbs0 zp, rel8
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90 bcc rel8 91 sta (zp), y 92! sta (zp), z 93+ bcc rel16
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94 sty zp, x 95 sta zp, x 96 stx zp, y 97 smb1 zp
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98 tya 99 sta abs16, y 9a txs 9b+ stx abs16, y
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9c! stz abs16 9d sta abs16, x 9e! stz abs16, x 9f bbs1 zp, rel8
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a0 ldy #imm8 a1 lda (zp, x) a2 ldx #imm8 a3+ ldz #imm8
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a4 ldy zp a5 lda zp a6 ldx zp a7 smb2 zp
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a8 tay a9 lda #imm8 aa tax ab+ ldz abs16
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ac ldy abs16 ad lda abs16 ae ldx abs16 af bbs2 zp, rel8
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b0 bcs rel8 b1 lda (zp), y b2! lda (zp), z b3+ bcs rel16
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b4 ldy zp, x b5 lda zp, x b6 ldx zp, y b7 smb3 zp
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b8 clv b9 lda abs16, y ba tsx bb+ ldz abs16, x
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bc ldy abs16, x bd lda abs16, x be ldx abs16, y bf bbs3 zp, rel8
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c0 cpy #imm8 c1 cmp (zp, x) c2+ cpz #imm8 c3+ dew zp
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c4 cpy zp c5 cmp zp c6 dec zp c7 smb4 zp
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c8 iny c9 cmp #imm8 ca dex cb+ asw abs16
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cc cpy abs16 cd cmp abs16 ce dec abs16 cf bbs4 zp, rel8
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d0 bne rel8 d1 cmp (zp), y d2! cmp (zp), z d3+ bne rel16
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d4+ cpz zp d5 cmp zp, x d6 dec zp, x d7 smb5 zp
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d8 cld d9 cmp abs16, y da phx db+ phz
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dc+ cpz abs16 dd cmp abs16, x de dec abs16, x df bbs5 zp, rel8
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e0 cpx #imm8 e1 sbc (zp, x) e2+ lda (o8, s), y e3+ inw zp
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e4 cpx zp e5 sbc zp e6 inc zp e7 smb6 zp
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e8 inx e9 sbc #imm8 ea nop eb+ row abs16
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ec cpx abs16 ed sbc abs16 ee inc abs16 ef bbs6 zp, rel8
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f0 beq rel8 f1 sbc (zp), y f2! sbc (zp), z f3+ beq rel16
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f4+ phw #imm16 f5 sbc zp, x f6 inc zp, x f7 smb7 zp
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f8 sed f9 sbc abs16, y fa plx fb+ plz
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fc+ phw abs16 fd sbc abs16, x fe inc abs16, x ff bbs7 zp, rel8
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#imm8: 8-bit immediate value
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#imm16: 16-bit immediate value (only for opcode f4)
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zp: 8-bit zeropage address
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abs16: 16-bit absolute address
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rel8: 8-bit relative address offset
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rel16: 16-bit relative address offset
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o8: 8-bit offset (for stack-relative addressing, see opcodes 82 and e2)
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The 65ce02 is a superset of the r65c02. It has several improvements:
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new Z register
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--------------
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The "stz" mnemonic no longer means "store zero", but "store Z register"
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(see opcodes 64, 74, 9c, 9e)
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The "(zp)" addressing mode now becomes "(zp), z"
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(see opcodes 12, 32, 52, 72, 92, b2, d2, f2)
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Z defaults to zero after reset, so these changes are backward compatible
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until Z is loaded with a non-zero value.
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New instructions for this register:
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1b inz increment Z
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3b dez decrement Z
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4b taz transfer A to Z
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6b tza transfer Z to A
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a3 ldz #imm8
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ab ldz abs16
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bb ldz abs16, x
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c2 cpz #imm8
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d4 cpz zp
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db phz push Z
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dc cpz abs16
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fb plz pull Z
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16-bit stack pointer
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--------------------
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02 cle clear stack extend disable
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03 see set stack extend disable
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0b tsy transfer stack_ptr_high to Y
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2b tys transfer Y to stack_ptr_high
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16-bit branches
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---------------
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13 bpl rel16
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33 bmi rel16
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53 bvc rel16
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63 bsr rel16 relative jsr, "branch to subroutine"
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73 bvs rel16
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83 bra rel16 relative jmp
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93 bcc rel16
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b3 bcs rel16
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d3 bne rel16
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f3 beq rel16
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To use these in ACME, use the mnemonics lbpl, lbmi, lbvc, ...
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(except for "bsr", because there is no 8-bit version of it anyway)
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new addressing modes for existing instructions
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----------------------------------------------
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22 jsr (abs16)
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23 jsr (abs16, x)
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82 sta (offset8, s), y
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8b sty abs16, x
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9b stx abs16, y
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e2 lda (offset8, s), y
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new instructions
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----------------
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42 neg negate A
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43 asr
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44 asr zp
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54 asr zp, x
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5b tab
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5c aug "4-byte NOP reserved for future expansion"
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62 rtn #imm8
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7b tba
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c3 dew zp
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cb asw abs16
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e3 inw zp
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eb row abs16
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f4 phw #imm16
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fc phw abs16
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