From 66c5faeb9a5ddef4b1622679a971e8f7a0ee1090 Mon Sep 17 00:00:00 2001 From: acqn Date: Tue, 8 Sep 2020 23:40:58 +0800 Subject: [PATCH] Added processor flags usage tracking. Added ZNRegs for tracking what register(s) Z/N flags currently reflect. Added utility functions to check if the specified processor state is known to be a certain value. --- src/cc65/codeent.c | 698 ++++++++++++++++++++++++++++++++++++++------ src/cc65/codeent.h | 4 +- src/cc65/codeinfo.c | 532 ++++++++++++++++----------------- src/cc65/codeinfo.h | 27 +- src/cc65/codeseg.c | 6 + src/cc65/coptsize.c | 584 ++++++++++++++++++------------------ src/cc65/coptstop.c | 8 +- src/cc65/reginfo.c | 50 ++++ src/cc65/reginfo.h | 118 ++++++++ 9 files changed, 1371 insertions(+), 656 deletions(-) diff --git a/src/cc65/codeent.c b/src/cc65/codeent.c index 0e3094962..085130001 100644 --- a/src/cc65/codeent.c +++ b/src/cc65/codeent.c @@ -498,6 +498,228 @@ void CE_FreeRegInfo (CodeEntry* E) +static void DeduceZ (RegContents* C, short Val) +/* Auto-set Z flag */ +{ + if (RegValIsUnknown (Val)) { + C->PFlags |= UNKNOWN_PFVAL_Z; + } else { + C->PFlags &= ~UNKNOWN_PFVAL_Z; + if (Val == 0) { + C->PFlags |= PFVAL_Z; + } + } +} + + + +static void DeduceZN (RegContents* C, short Val) +/* Auto-set Z/N flags */ +{ + if (RegValIsUnknown (Val)) { + C->PFlags |= UNKNOWN_PFVAL_ZN; + } else { + C->PFlags &= ~UNKNOWN_PFVAL_ZN; + if (Val == 0) { + C->PFlags |= PFVAL_Z; + } else if (Val & PFVAL_N) { + C->PFlags |= PFVAL_N; + } + } +} + + + +static short KnownOpADCDeduceCZVN (RegContents* Out, RegContents* In, short Rhs) +/* Do the ADC and auto-set C/Z/V/N flags. +** Both operands and the C flag must be known. +*/ +{ + short SVal, UVal; + SVal = (signed char)(In->RegA & 0xFF) + (signed char)(Rhs & 0xFF); + UVal = (In->RegA & 0xFF) + (Rhs & 0xFF); + if (In->PFlags & PFVAL_C) { + ++SVal; + ++UVal; + } + + Out->PFlags &= ~UNKNOWN_PFVAL_CZVN; + if (UVal > 0xFF) { + Out->PFlags |= PFVAL_C; + } + + if (SVal < -128 || SVal > 127) { + Out->PFlags |= PFVAL_V; + } + + DeduceZN (Out, UVal); + + return UVal; +} + + + +static short KnownOpSBCDeduceCZVN (RegContents* Out, RegContents* In, short Rhs) +/* Do the SBC and auto-set C/Z/V/N flags. +** Both operands and the C flag must be known. +*/ +{ + short SVal, UVal; + SVal = (signed char)(In->RegA & 0xFF) - (signed char)(Rhs & 0xFF); + UVal = (In->RegA & 0xFF) - (Rhs & 0xFF); + if ((In->PFlags & PFVAL_C) == 0) { + --SVal; + --UVal; + } + + Out->PFlags &= ~UNKNOWN_PFVAL_CZVN; + if (UVal >= 0) { + Out->PFlags |= PFVAL_C; + } + + if (SVal < -128 || SVal > 127) { + Out->PFlags |= PFVAL_V; + } + + DeduceZN (Out, UVal); + + return UVal; +} + + + +static short KnownOpCmpDeduceCZN (RegContents* C, short Lhs, short Rhs) +/* Do the CMP and auto-set C/Z/N flags. +** Both operands must be known. + */ +{ + short Val = (Lhs & 0xFF) - (Rhs & 0xFF); + + C->PFlags &= ~UNKNOWN_PFVAL_C; + if (Val >= 0) { + C->PFlags |= PFVAL_C; + } + DeduceZN (C, Val); + + return Val; +} + + + +static short AnyOpASLDeduceCZN (RegContents* C, short Shiftee) +/* Do the ASL and auto-set C/Z/N flags */ +{ + if (RegValIsKnown (Shiftee)) { + C->PFlags &= ~UNKNOWN_PFVAL_C; + if (Shiftee & 0x80U) { + C->PFlags |= PFVAL_C; + } + Shiftee = (Shiftee << 1) & 0xFF; + } + DeduceZN (C, Shiftee); + + return Shiftee; +} + + + +static short AnyOpLSRDeduceCZN (RegContents* C, short Shiftee) +/* Do the LSR and auto-set C/Z/N flags */ +{ + if (RegValIsKnown (Shiftee)) { + C->PFlags &= ~UNKNOWN_PFVAL_C; + if (Shiftee & 0x01U) { + C->PFlags |= PFVAL_C; + } + Shiftee = (Shiftee >> 1) & 0xFF; + } + DeduceZN (C, Shiftee); + + return Shiftee; +} + + + +static short AnyOpROLDeduceCZN (RegContents* C, short PFlags, short Shiftee) +/* Do the ROL and auto-set C/Z/N flags */ +{ + if (RegValIsKnown (Shiftee) && PStatesAreKnown (PFlags, PSTATE_C)) { + C->PFlags &= ~UNKNOWN_PFVAL_C; + if (Shiftee & 0x80U) { + C->PFlags |= PFVAL_C; + } + Shiftee = (Shiftee << 1) & 0xFF; + if (PFlags & PFVAL_C) { + Shiftee |= 0x01U; + } + } else { + Shiftee = UNKNOWN_REGVAL; + } + DeduceZN (C, Shiftee); + + return Shiftee; +} + + + +static short AnyOpRORDeduceCZN (RegContents* C, short PFlags, short Shiftee) +/* Do the ROR and auto-set C/Z/N flags */ +{ + if (RegValIsKnown (Shiftee) && PStatesAreKnown (PFlags, PSTATE_C)) { + C->PFlags &= ~UNKNOWN_PFVAL_C; + if (Shiftee & 0x01U) { + C->PFlags |= PFVAL_C; + } + Shiftee = (Shiftee >> 1) & 0xFF; + if (PFlags & PFVAL_C) { + Shiftee |= 0x80U; + } + } else { + Shiftee = UNKNOWN_REGVAL; + } + DeduceZN (C, Shiftee); + + return Shiftee; +} + + + +static void BranchDeduceOnProcessorFlag (RegContents* True, RegContents* False, unsigned short PTrueFlag) +/* Auto-set the corresponding C/Z/V/N flag output for both True/Flase code flows */ +{ + PTrueFlag &= 0xFF; + unsigned short Mask = ~(PTrueFlag * 0x0101U) & 0xFFFFU; + True->PFlags &= Mask; + True->PFlags |= PTrueFlag; + False->PFlags &= Mask; +} + + + +static int MightAffectKnownZP (CodeEntry* E, RegContents* In) +/* TODO: This is supposed to check if any builtin ZP could be affected. +** It simply returns TRUE in most cases for now. +*/ +{ + unsigned Index = 0; + + if (E->AM == AM65_ZP || + E->AM == AM65_ABS || + (E->AM == AM65_ZPX && RegValIsKnown (In->RegX) && (Index = In->RegX & 0xFF)) || + (E->AM == AM65_ZPY && RegValIsKnown (In->RegY) && (Index = In->RegY & 0xFF)) || + (E->AM == AM65_ABSX && RegValIsKnown (In->RegX) && (Index = In->RegX & 0xFF)) || + (E->AM == AM65_ABSY && RegValIsKnown (In->RegY) && (Index = In->RegY & 0xFF))) { + return 1; + } else if ((E->AM == AM65_ZP_IND) || + (E->AM == AM65_ZPX_IND && RegValIsKnown (In->RegX) && (Index = In->RegX & 0xFF)) || + (E->AM == AM65_ZP_INDY && RegValIsKnown (In->RegY) && (Index = In->RegY & 0xFF))) { + return 1; + } + return 1; +} + + + void CE_GenRegInfo (CodeEntry* E, RegContents* InputRegs) /* Generate register info for this instruction. If an old info exists, it is ** overwritten. @@ -506,9 +728,13 @@ void CE_GenRegInfo (CodeEntry* E, RegContents* InputRegs) /* Pointers to the register contents */ RegContents* In; RegContents* Out; + RegContents* BranchOut; /* Function register usage */ - unsigned short Use, Chg; + unsigned Use, Chg; + + /* Value in question */ + short Val = UNKNOWN_REGVAL; /* If we don't have a register info struct, allocate one. */ if (E->RI == 0) { @@ -525,18 +751,46 @@ void CE_GenRegInfo (CodeEntry* E, RegContents* InputRegs) /* Get pointers to the register contents */ In = &E->RI->In; Out = &E->RI->Out; + BranchOut = &E->RI->Out2; /* Handle the different instructions */ switch (E->OPC) { case OP65_ADC: - /* We don't know the value of the carry, so the result is - ** always unknown. - */ Out->RegA = UNKNOWN_REGVAL; + Out->PFlags |= UNKNOWN_PFVAL_CZVN; + Out->ZNRegs = ZNREG_A; + if (PStatesAreKnown (In->PFlags, PSTATE_C) && + RegValIsKnown (In->RegA)) { + if (CE_IsConstImm (E)) { + Out->RegA = KnownOpADCDeduceCZVN (Out, In, (short) E->Num); + } else if (E->AM == AM65_ZP) { + switch (GetKnownReg (E->Use & REG_ZP, In)) { + case REG_TMP1: + Out->RegA = KnownOpADCDeduceCZVN (Out, In, In->Tmp1); + break; + case REG_PTR1_LO: + Out->RegA = KnownOpADCDeduceCZVN (Out, In, In->Ptr1Lo); + break; + case REG_PTR1_HI: + Out->RegA = KnownOpADCDeduceCZVN (Out, In, In->Ptr1Hi); + break; + case REG_SREG_LO: + Out->RegA = KnownOpADCDeduceCZVN (Out, In, In->SRegLo); + break; + case REG_SREG_HI: + Out->RegA = KnownOpADCDeduceCZVN (Out, In, In->SRegHi); + break; + default: + break; + } + } + } break; case OP65_AND: + Out->RegA = UNKNOWN_REGVAL; + Out->ZNRegs = ZNREG_A; if (RegValIsKnown (In->RegA)) { if (CE_IsConstImm (E)) { Out->RegA = In->RegA & (short) E->Num; @@ -558,145 +812,289 @@ void CE_GenRegInfo (CodeEntry* E, RegContents* InputRegs) Out->RegA = In->RegA & In->SRegHi; break; default: - Out->RegA = UNKNOWN_REGVAL; break; } - } else { - Out->RegA = UNKNOWN_REGVAL; } } else if (CE_IsKnownImm (E, 0)) { /* A and $00 does always give zero */ Out->RegA = 0; } + DeduceZN (Out, Out->RegA); break; case OP65_ASL: - if (E->AM == AM65_ACC && RegValIsKnown (In->RegA)) { - Out->RegA = (In->RegA << 1) & 0xFF; + Out->PFlags |= UNKNOWN_PFVAL_CZN; + Out->ZNRegs = ZNREG_NONE; + if (E->AM == AM65_ACC) { + Out->RegA = AnyOpASLDeduceCZN (Out, In->RegA); + Out->ZNRegs = ZNREG_A; } else if (E->AM == AM65_ZP) { switch (GetKnownReg (E->Chg & REG_ZP, In)) { case REG_TMP1: - Out->Tmp1 = (In->Tmp1 << 1) & 0xFF; + Out->Tmp1 = AnyOpASLDeduceCZN (Out, In->Tmp1); + Out->ZNRegs = ZNREG_TMP1; break; case REG_PTR1_LO: - Out->Ptr1Lo = (In->Ptr1Lo << 1) & 0xFF; + Out->Ptr1Lo = AnyOpASLDeduceCZN (Out, In->Ptr1Lo); + Out->ZNRegs = ZNREG_PTR1_LO; break; case REG_PTR1_HI: - Out->Ptr1Hi = (In->Ptr1Hi << 1) & 0xFF; + Out->Ptr1Hi = AnyOpASLDeduceCZN (Out, In->Ptr1Hi); + Out->ZNRegs = ZNREG_PTR1_HI; break; case REG_SREG_LO: - Out->SRegLo = (In->SRegLo << 1) & 0xFF; + Out->SRegLo = AnyOpASLDeduceCZN (Out, In->SRegLo); + Out->ZNRegs = ZNREG_SREG_LO; break; case REG_SREG_HI: - Out->SRegHi = (In->SRegHi << 1) & 0xFF; + Out->SRegHi = AnyOpASLDeduceCZN (Out, In->SRegHi); + Out->ZNRegs = ZNREG_SREG_HI; break; } - } else if (E->AM == AM65_ZPX) { + } else if (MightAffectKnownZP (E, In)) { /* Invalidates all ZP registers */ RC_InvalidateZP (Out); } break; case OP65_BCC: + BranchDeduceOnProcessorFlag (Out, BranchOut, PFVAL_C); break; case OP65_BCS: + BranchDeduceOnProcessorFlag (BranchOut, Out, PFVAL_C); break; case OP65_BEQ: + BranchDeduceOnProcessorFlag (BranchOut, Out, PFVAL_Z); break; case OP65_BIT: + Out->ZNRegs = ZNREG_NONE; + if (E->AM == AM65_ZP) { + switch (GetKnownReg (E->Chg & REG_ZP, In)) { + case REG_TMP1: + Val = In->Tmp1; + break; + case REG_PTR1_LO: + Val = In->Ptr1Lo; + break; + case REG_PTR1_HI: + Val = In->Ptr1Hi; + break; + case REG_SREG_LO: + Val = In->SRegLo; + break; + case REG_SREG_HI: + Val = In->SRegHi; + break; + } + } + Out->PFlags &= ~UNKNOWN_PFVAL_V; + if (Val & PFVAL_V) { + Out->PFlags |= PFVAL_V; + } + DeduceZN (Out, Val); break; case OP65_BMI: + BranchDeduceOnProcessorFlag (BranchOut, Out, PFVAL_N); break; case OP65_BNE: + BranchDeduceOnProcessorFlag (Out, BranchOut, PFVAL_Z); break; case OP65_BPL: + BranchDeduceOnProcessorFlag (Out, BranchOut, PFVAL_N); break; case OP65_BRA: break; case OP65_BRK: + Out->PFlags &= ~UNKNOWN_PFVAL_B; + Out->PFlags |= PFVAL_B; break; case OP65_BVC: + BranchDeduceOnProcessorFlag (Out, BranchOut, PFVAL_V); break; case OP65_BVS: + BranchDeduceOnProcessorFlag (BranchOut, Out, PFVAL_V); break; case OP65_CLC: + Out->PFlags &= ~UNKNOWN_PFVAL_C; break; case OP65_CLD: + Out->PFlags &= ~UNKNOWN_PFVAL_D; break; case OP65_CLI: + Out->PFlags &= ~UNKNOWN_PFVAL_I; break; case OP65_CLV: + Out->PFlags &= ~UNKNOWN_PFVAL_V; break; case OP65_CMP: + Out->PFlags |= UNKNOWN_PFVAL_CZN; + Out->ZNRegs = ZNREG_NONE; + if (RegValIsKnown (In->RegA)) { + if (CE_IsConstImm (E)) { + KnownOpCmpDeduceCZN (Out, In->RegA, (short)E->Num); + } else if (E->AM == AM65_ZP) { + switch (GetKnownReg (E->Use & REG_ZP, In)) { + case REG_TMP1: + KnownOpCmpDeduceCZN (Out, In->RegA, In->Tmp1); + break; + case REG_PTR1_LO: + KnownOpCmpDeduceCZN (Out, In->RegA, In->Ptr1Lo); + break; + case REG_PTR1_HI: + KnownOpCmpDeduceCZN (Out, In->RegA, In->Ptr1Hi); + break; + case REG_SREG_LO: + KnownOpCmpDeduceCZN (Out, In->RegA, In->SRegLo); + break; + case REG_SREG_HI: + KnownOpCmpDeduceCZN (Out, In->RegA, In->SRegHi); + break; + default: + break; + } + } + } break; case OP65_CPX: + Out->PFlags |= UNKNOWN_PFVAL_CZN; + Out->ZNRegs = ZNREG_NONE; + if (RegValIsKnown (In->RegX)) { + if (CE_IsConstImm (E)) { + KnownOpCmpDeduceCZN (Out, In->RegX, (short)E->Num); + } else if (E->AM == AM65_ZP) { + switch (GetKnownReg (E->Use & REG_ZP, In)) { + case REG_TMP1: + KnownOpCmpDeduceCZN (Out, In->RegX, In->Tmp1); + break; + case REG_PTR1_LO: + KnownOpCmpDeduceCZN (Out, In->RegX, In->Ptr1Lo); + break; + case REG_PTR1_HI: + KnownOpCmpDeduceCZN (Out, In->RegX, In->Ptr1Hi); + break; + case REG_SREG_LO: + KnownOpCmpDeduceCZN (Out, In->RegX, In->SRegLo); + break; + case REG_SREG_HI: + KnownOpCmpDeduceCZN (Out, In->RegX, In->SRegHi); + break; + default: + break; + } + } + } break; case OP65_CPY: + Out->PFlags |= UNKNOWN_PFVAL_CZN; + Out->ZNRegs = ZNREG_NONE; + if (RegValIsKnown (In->RegY)) { + if (CE_IsConstImm (E)) { + KnownOpCmpDeduceCZN (Out, In->RegY, (short)E->Num); + } else if (E->AM == AM65_ZP) { + switch (GetKnownReg (E->Use & REG_ZP, In)) { + case REG_TMP1: + KnownOpCmpDeduceCZN (Out, In->RegY, In->Tmp1); + break; + case REG_PTR1_LO: + KnownOpCmpDeduceCZN (Out, In->RegY, In->Ptr1Lo); + break; + case REG_PTR1_HI: + KnownOpCmpDeduceCZN (Out, In->RegY, In->Ptr1Hi); + break; + case REG_SREG_LO: + KnownOpCmpDeduceCZN (Out, In->RegY, In->SRegLo); + break; + case REG_SREG_HI: + KnownOpCmpDeduceCZN (Out, In->RegY, In->SRegHi); + break; + default: + break; + } + } + } break; case OP65_DEA: + Out->ZNRegs = ZNREG_A; if (RegValIsKnown (In->RegA)) { Out->RegA = (In->RegA - 1) & 0xFF; } + DeduceZN (Out, Out->RegA); break; case OP65_DEC: - if (E->AM == AM65_ACC && RegValIsKnown (In->RegA)) { - Out->RegA = (In->RegA - 1) & 0xFF; + Out->ZNRegs = ZNREG_NONE; + if (E->AM == AM65_ACC) { + if (RegValIsKnown (In->RegA)) { + Val = Out->RegA = (In->RegA - 1) & 0xFF; + } + Out->ZNRegs = ZNREG_A; } else if (E->AM == AM65_ZP) { switch (GetKnownReg (E->Chg & REG_ZP, In)) { case REG_TMP1: - Out->Tmp1 = (In->Tmp1 - 1) & 0xFF; + Val = Out->Tmp1 = (In->Tmp1 - 1) & 0xFF; + Out->ZNRegs = ZNREG_TMP1; break; case REG_PTR1_LO: - Out->Ptr1Lo = (In->Ptr1Lo - 1) & 0xFF; + Val = Out->Ptr1Lo = (In->Ptr1Lo - 1) & 0xFF; + Out->ZNRegs = ZNREG_PTR1_LO; break; case REG_PTR1_HI: - Out->Ptr1Hi = (In->Ptr1Hi - 1) & 0xFF; + Val = Out->Ptr1Hi = (In->Ptr1Hi - 1) & 0xFF; + Out->ZNRegs = ZNREG_PTR1_HI; break; case REG_SREG_LO: - Out->SRegLo = (In->SRegLo - 1) & 0xFF; + Val = Out->SRegLo = (In->SRegLo - 1) & 0xFF; + Out->ZNRegs = ZNREG_SREG_LO; break; case REG_SREG_HI: - Out->SRegHi = (In->SRegHi - 1) & 0xFF; + Val = Out->SRegHi = (In->SRegHi - 1) & 0xFF; + Out->ZNRegs = ZNREG_SREG_HI; break; } - } else if (E->AM == AM65_ZPX) { + } else if (MightAffectKnownZP (E, In)) { /* Invalidates all ZP registers */ RC_InvalidateZP (Out); } + DeduceZN (Out, Val); break; case OP65_DEX: + Out->ZNRegs = ZNREG_X; if (RegValIsKnown (In->RegX)) { Out->RegX = (In->RegX - 1) & 0xFF; } + DeduceZN (Out, Out->RegX); break; case OP65_DEY: + Out->ZNRegs = ZNREG_Y; if (RegValIsKnown (In->RegY)) { Out->RegY = (In->RegY - 1) & 0xFF; } + DeduceZN (Out, Out->RegY); break; case OP65_EOR: + Out->RegA = UNKNOWN_REGVAL; + Out->ZNRegs = ZNREG_A; if (RegValIsKnown (In->RegA)) { if (CE_IsConstImm (E)) { Out->RegA = In->RegA ^ (short) E->Num; @@ -718,82 +1116,104 @@ void CE_GenRegInfo (CodeEntry* E, RegContents* InputRegs) Out->RegA = In->RegA ^ In->SRegHi; break; default: - Out->RegA = UNKNOWN_REGVAL; break; } - } else { - Out->RegA = UNKNOWN_REGVAL; } } + DeduceZN (Out, Out->RegA); break; case OP65_INA: + Out->ZNRegs = ZNREG_A; if (RegValIsKnown (In->RegA)) { Out->RegA = (In->RegA + 1) & 0xFF; } + DeduceZN (Out, Out->RegA); break; case OP65_INC: - if (E->AM == AM65_ACC && RegValIsKnown (In->RegA)) { - Out->RegA = (In->RegA + 1) & 0xFF; + Out->ZNRegs = ZNREG_NONE; + if (E->AM == AM65_ACC) { + if (RegValIsKnown (In->RegA)) { + Val = Out->RegA = (In->RegA + 1) & 0xFF; + } + Out->ZNRegs = ZNREG_A; } else if (E->AM == AM65_ZP) { - switch (GetKnownReg (E->Chg & REG_ZP, In)) { + switch (GetKnownReg (E->Chg & REG_ZP, 0)) { case REG_TMP1: - Out->Tmp1 = (In->Tmp1 + 1) & 0xFF; + Val = Out->Tmp1 = (In->Tmp1 + 1) & 0xFF; + Out->ZNRegs = ZNREG_TMP1; break; case REG_PTR1_LO: - Out->Ptr1Lo = (In->Ptr1Lo + 1) & 0xFF; + Val = Out->Ptr1Lo = (In->Ptr1Lo + 1) & 0xFF; + Out->ZNRegs = ZNREG_PTR1_LO; break; case REG_PTR1_HI: - Out->Ptr1Hi = (In->Ptr1Hi + 1) & 0xFF; + Val = Out->Ptr1Hi = (In->Ptr1Hi + 1) & 0xFF; + Out->ZNRegs = ZNREG_PTR1_HI; break; case REG_SREG_LO: - Out->SRegLo = (In->SRegLo + 1) & 0xFF; + Val = Out->SRegLo = (In->SRegLo + 1) & 0xFF; + Out->ZNRegs = ZNREG_SREG_LO; break; case REG_SREG_HI: - Out->SRegHi = (In->SRegHi + 1) & 0xFF; + Val = Out->SRegHi = (In->SRegHi + 1) & 0xFF; + Out->ZNRegs = ZNREG_SREG_HI; break; } - } else if (E->AM == AM65_ZPX) { + } else if (MightAffectKnownZP (E, In)) { /* Invalidates all ZP registers */ RC_InvalidateZP (Out); } + DeduceZN (Out, Val); break; case OP65_INX: + Out->ZNRegs = ZNREG_X; if (RegValIsKnown (In->RegX)) { Out->RegX = (In->RegX + 1) & 0xFF; } + DeduceZN (Out, Out->RegX); break; case OP65_INY: + Out->ZNRegs = ZNREG_Y; if (RegValIsKnown (In->RegY)) { Out->RegY = (In->RegY + 1) & 0xFF; } + DeduceZN (Out, Out->RegY); break; case OP65_JCC: + BranchDeduceOnProcessorFlag (Out, BranchOut, PFVAL_C); break; case OP65_JCS: + BranchDeduceOnProcessorFlag (BranchOut, Out, PFVAL_C); break; case OP65_JEQ: + BranchDeduceOnProcessorFlag (BranchOut, Out, PFVAL_Z); break; case OP65_JMI: + BranchDeduceOnProcessorFlag (BranchOut, Out, PFVAL_N); break; case OP65_JMP: break; case OP65_JNE: + BranchDeduceOnProcessorFlag (Out, BranchOut, PFVAL_Z); break; case OP65_JPL: + BranchDeduceOnProcessorFlag (Out, BranchOut, PFVAL_N); break; case OP65_JSR: + Out->ZNRegs = ZNREG_NONE; + /* Get the code info for the function */ GetFuncInfo (E->Arg, &Use, &Chg); if (Chg & REG_A) { @@ -820,6 +1240,9 @@ void CE_GenRegInfo (CodeEntry* E, RegContents* InputRegs) if (Chg & REG_SREG_HI) { Out->SRegHi = UNKNOWN_REGVAL; } + /* FIXME: Quick hack to set flags on process status: */ + Out->PFlags |= ((Chg & PSTATE_ALL) >> PSTATE_BITS_SHIFT) * 0x0101U; + /* ## FIXME: Quick hack for some known functions: */ if (strcmp (E->Arg, "complax") == 0) { if (RegValIsKnown (In->RegA)) { @@ -861,12 +1284,16 @@ void CE_GenRegInfo (CodeEntry* E, RegContents* InputRegs) break; case OP65_JVC: + BranchDeduceOnProcessorFlag (Out, BranchOut, PFVAL_V); break; case OP65_JVS: + BranchDeduceOnProcessorFlag (BranchOut, Out, PFVAL_V); break; case OP65_LDA: + Out->RegA = UNKNOWN_REGVAL; + Out->ZNRegs = ZNREG_A; if (CE_IsConstImm (E)) { Out->RegA = (unsigned char) E->Num; } else if (E->AM == AM65_ZP) { @@ -887,16 +1314,15 @@ void CE_GenRegInfo (CodeEntry* E, RegContents* InputRegs) Out->RegA = In->SRegHi; break; default: - Out->RegA = UNKNOWN_REGVAL; break; } - } else { - /* A is now unknown */ - Out->RegA = UNKNOWN_REGVAL; } + DeduceZN (Out, Out->RegA); break; case OP65_LDX: + Out->RegX = UNKNOWN_REGVAL; + Out->ZNRegs = ZNREG_X; if (CE_IsConstImm (E)) { Out->RegX = (unsigned char) E->Num; } else if (E->AM == AM65_ZP) { @@ -917,16 +1343,15 @@ void CE_GenRegInfo (CodeEntry* E, RegContents* InputRegs) Out->RegX = In->SRegHi; break; default: - Out->RegX = UNKNOWN_REGVAL; break; } - } else { - /* X is now unknown */ - Out->RegX = UNKNOWN_REGVAL; } + DeduceZN (Out, Out->RegX); break; case OP65_LDY: + Out->RegY = UNKNOWN_REGVAL; + Out->ZNRegs = ZNREG_Y; if (CE_IsConstImm (E)) { Out->RegY = (unsigned char) E->Num; } else if (E->AM == AM65_ZP) { @@ -947,37 +1372,42 @@ void CE_GenRegInfo (CodeEntry* E, RegContents* InputRegs) Out->RegY = In->SRegHi; break; default: - Out->RegY = UNKNOWN_REGVAL; break; } - } else { - /* Y is now unknown */ - Out->RegY = UNKNOWN_REGVAL; } + DeduceZN (Out, Out->RegY); break; case OP65_LSR: - if (E->AM == AM65_ACC && RegValIsKnown (In->RegA)) { - Out->RegA = (In->RegA >> 1) & 0xFF; + Out->PFlags |= UNKNOWN_PFVAL_CZN; + Out->ZNRegs = ZNREG_NONE; + if (E->AM == AM65_ACC) { + Out->RegA = AnyOpLSRDeduceCZN (Out, In->RegA); + Out->ZNRegs = ZNREG_A; } else if (E->AM == AM65_ZP) { - switch (GetKnownReg (E->Chg & REG_ZP, In)) { + switch (GetKnownReg (E->Chg & REG_ZP, 0)) { case REG_TMP1: - Out->Tmp1 = (In->Tmp1 >> 1) & 0xFF; + Out->Tmp1 = AnyOpLSRDeduceCZN (Out, In->Tmp1); + Out->ZNRegs = ZNREG_TMP1; break; case REG_PTR1_LO: - Out->Ptr1Lo = (In->Ptr1Lo >> 1) & 0xFF; + Out->Ptr1Lo = AnyOpLSRDeduceCZN (Out, In->Ptr1Lo); + Out->ZNRegs = ZNREG_PTR1_LO; break; case REG_PTR1_HI: - Out->Ptr1Hi = (In->Ptr1Hi >> 1) & 0xFF; + Out->Ptr1Hi = AnyOpLSRDeduceCZN (Out, In->Ptr1Hi); + Out->ZNRegs = ZNREG_PTR1_HI; break; case REG_SREG_LO: - Out->SRegLo = (In->SRegLo >> 1) & 0xFF; + Out->SRegLo = AnyOpLSRDeduceCZN (Out, In->SRegLo); + Out->ZNRegs = ZNREG_SREG_LO; break; case REG_SREG_HI: - Out->SRegHi = (In->SRegHi >> 1) & 0xFF; + Out->SRegHi = AnyOpLSRDeduceCZN (Out, In->SRegHi); + Out->ZNRegs = ZNREG_SREG_HI; break; } - } else if (E->AM == AM65_ZPX) { + } else if (MightAffectKnownZP (E, In)) { /* Invalidates all ZP registers */ RC_InvalidateZP (Out); } @@ -987,6 +1417,8 @@ void CE_GenRegInfo (CodeEntry* E, RegContents* InputRegs) break; case OP65_ORA: + Out->RegA = UNKNOWN_REGVAL; + Out->ZNRegs = ZNREG_A; if (RegValIsKnown (In->RegA)) { if (CE_IsConstImm (E)) { Out->RegA = In->RegA | (short) E->Num; @@ -1008,17 +1440,14 @@ void CE_GenRegInfo (CodeEntry* E, RegContents* InputRegs) Out->RegA = In->RegA | In->SRegHi; break; default: - Out->RegA = UNKNOWN_REGVAL; break; } - } else { - /* A is now unknown */ - Out->RegA = UNKNOWN_REGVAL; } } else if (CE_IsKnownImm (E, 0xFF)) { /* ORA with 0xFF does always give 0xFF */ Out->RegA = 0xFF; } + DeduceZN (Out, Out->RegA); break; case OP65_PHA: @@ -1035,93 +1464,150 @@ void CE_GenRegInfo (CodeEntry* E, RegContents* InputRegs) case OP65_PLA: Out->RegA = UNKNOWN_REGVAL; + Out->PFlags |= UNKNOWN_PFVAL_ZN; + Out->ZNRegs = ZNREG_A; break; case OP65_PLP: + Out->PFlags = UNKNOWN_PFVAL_ALL; + Out->ZNRegs = ZNREG_NONE; break; case OP65_PLX: Out->RegX = UNKNOWN_REGVAL; + Out->PFlags |= UNKNOWN_PFVAL_ZN; + Out->ZNRegs = ZNREG_X; break; case OP65_PLY: Out->RegY = UNKNOWN_REGVAL; + Out->PFlags |= UNKNOWN_PFVAL_ZN; + Out->ZNRegs = ZNREG_Y; break; case OP65_ROL: - /* We don't know the value of the carry bit */ + Out->PFlags |= UNKNOWN_PFVAL_CZN; + Out->ZNRegs = ZNREG_NONE; if (E->AM == AM65_ACC) { - Out->RegA = UNKNOWN_REGVAL; + Out->RegA = AnyOpROLDeduceCZN (Out, In->PFlags, In->RegA); + Out->ZNRegs = ZNREG_A; } else if (E->AM == AM65_ZP) { - switch (GetKnownReg (E->Chg & REG_ZP, In)) { + switch (GetKnownReg (E->Chg & REG_ZP, 0)) { case REG_TMP1: - Out->Tmp1 = UNKNOWN_REGVAL; + Out->Tmp1 = AnyOpROLDeduceCZN (Out, In->PFlags, In->Tmp1); + Out->ZNRegs = ZNREG_TMP1; break; case REG_PTR1_LO: - Out->Ptr1Lo = UNKNOWN_REGVAL; + Out->Ptr1Lo = AnyOpROLDeduceCZN (Out, In->PFlags, In->Ptr1Lo); + Out->ZNRegs = ZNREG_PTR1_LO; break; case REG_PTR1_HI: - Out->Ptr1Hi = UNKNOWN_REGVAL; + Out->Ptr1Hi = AnyOpROLDeduceCZN (Out, In->PFlags, In->Ptr1Hi); + Out->ZNRegs = ZNREG_PTR1_HI; break; case REG_SREG_LO: - Out->SRegLo = UNKNOWN_REGVAL; + Out->SRegLo = AnyOpROLDeduceCZN (Out, In->PFlags, In->SRegLo); + Out->ZNRegs = ZNREG_SREG_LO; break; case REG_SREG_HI: - Out->SRegHi = UNKNOWN_REGVAL; + Out->SRegHi = AnyOpROLDeduceCZN (Out, In->PFlags, In->SRegHi); + Out->ZNRegs = ZNREG_SREG_HI; break; } - } else if (E->AM == AM65_ZPX) { + } else if (MightAffectKnownZP (E, In)) { /* Invalidates all ZP registers */ RC_InvalidateZP (Out); } break; case OP65_ROR: - /* We don't know the value of the carry bit */ + Out->PFlags |= UNKNOWN_PFVAL_CZN; + Out->ZNRegs = ZNREG_NONE; if (E->AM == AM65_ACC) { - Out->RegA = UNKNOWN_REGVAL; + Out->RegA = AnyOpRORDeduceCZN (Out, In->PFlags, In->RegA); + Out->ZNRegs = ZNREG_A; } else if (E->AM == AM65_ZP) { - switch (GetKnownReg (E->Chg & REG_ZP, In)) { + switch (GetKnownReg (E->Chg & REG_ZP, 0)) { case REG_TMP1: - Out->Tmp1 = UNKNOWN_REGVAL; + Out->Tmp1 = AnyOpRORDeduceCZN (Out, In->PFlags, In->Tmp1); + Out->ZNRegs = ZNREG_TMP1; break; case REG_PTR1_LO: - Out->Ptr1Lo = UNKNOWN_REGVAL; + Out->Ptr1Lo = AnyOpRORDeduceCZN (Out, In->PFlags, In->Ptr1Lo); + Out->ZNRegs = ZNREG_PTR1_LO; break; case REG_PTR1_HI: - Out->Ptr1Hi = UNKNOWN_REGVAL; + Out->Ptr1Hi = AnyOpRORDeduceCZN (Out, In->PFlags, In->Ptr1Hi); + Out->ZNRegs = ZNREG_PTR1_HI; break; case REG_SREG_LO: - Out->SRegLo = UNKNOWN_REGVAL; + Out->SRegLo = AnyOpRORDeduceCZN (Out, In->PFlags, In->SRegLo); + Out->ZNRegs = ZNREG_SREG_LO; break; case REG_SREG_HI: - Out->SRegHi = UNKNOWN_REGVAL; + Out->SRegHi = AnyOpRORDeduceCZN (Out, In->PFlags, In->SRegHi); + Out->ZNRegs = ZNREG_SREG_HI; break; } - } else if (E->AM == AM65_ZPX) { + } else if (MightAffectKnownZP (E, In)) { /* Invalidates all ZP registers */ RC_InvalidateZP (Out); } break; case OP65_RTI: + Out->PFlags |= UNKNOWN_PFVAL_ALL; break; case OP65_RTS: break; case OP65_SBC: - /* We don't know the value of the carry bit */ Out->RegA = UNKNOWN_REGVAL; + Out->PFlags |= UNKNOWN_PFVAL_CZVN; + Out->ZNRegs = ZNREG_A; + if (PStatesAreKnown (In->PFlags, PSTATE_C) && + RegValIsKnown (In->RegA)) { + if (CE_IsConstImm (E)) { + Out->RegA = KnownOpSBCDeduceCZVN (Out, In, (short) E->Num); + } + else if (E->AM == AM65_ZP) { + switch (GetKnownReg(E->Use & REG_ZP, In)) { + case REG_TMP1: + Out->RegA = KnownOpSBCDeduceCZVN (Out, In, In->Tmp1); + break; + case REG_PTR1_LO: + Out->RegA = KnownOpSBCDeduceCZVN (Out, In, In->Ptr1Lo); + break; + case REG_PTR1_HI: + Out->RegA = KnownOpSBCDeduceCZVN (Out, In, In->Ptr1Hi); + break; + case REG_SREG_LO: + Out->RegA = KnownOpSBCDeduceCZVN (Out, In, In->SRegLo); + break; + case REG_SREG_HI: + Out->RegA = KnownOpSBCDeduceCZVN (Out, In, In->SRegHi); + break; + default: + break; + } + } + } break; case OP65_SEC: + Out->PFlags &= ~UNKNOWN_PFVAL_C; + Out->PFlags |= PFVAL_C; break; case OP65_SED: + Out->PFlags &= ~UNKNOWN_PFVAL_D; + Out->PFlags |= PFVAL_D; break; case OP65_SEI: + Out->PFlags &= ~UNKNOWN_PFVAL_I; + Out->PFlags |= PFVAL_I; break; case OP65_STA: @@ -1143,7 +1629,7 @@ void CE_GenRegInfo (CodeEntry* E, RegContents* InputRegs) Out->SRegHi = In->RegA; break; } - } else if (E->AM == AM65_ZPX) { + } else if (MightAffectKnownZP (E, In)) { /* Invalidates all ZP registers */ RC_InvalidateZP (Out); } @@ -1171,7 +1657,7 @@ void CE_GenRegInfo (CodeEntry* E, RegContents* InputRegs) Out->SRegHi = In->RegX; break; } - } else if (E->AM == AM65_ZPX) { + } else if (MightAffectKnownZP (E, In)) { /* Invalidates all ZP registers */ RC_InvalidateZP (Out); } @@ -1196,7 +1682,7 @@ void CE_GenRegInfo (CodeEntry* E, RegContents* InputRegs) Out->SRegHi = In->RegY; break; } - } else if (E->AM == AM65_ZPX) { + } else if (MightAffectKnownZP (E, In)) { /* Invalidates all ZP registers */ RC_InvalidateZP (Out); } @@ -1221,7 +1707,7 @@ void CE_GenRegInfo (CodeEntry* E, RegContents* InputRegs) Out->SRegHi = 0; break; } - } else if (E->AM == AM65_ZPX) { + } else if (MightAffectKnownZP (E, In)) { /* Invalidates all ZP registers */ RC_InvalidateZP (Out); } @@ -1229,37 +1715,44 @@ void CE_GenRegInfo (CodeEntry* E, RegContents* InputRegs) case OP65_TAX: Out->RegX = In->RegA; + Out->ZNRegs = ZNREG_AX; + DeduceZN (Out, Out->RegX); break; case OP65_TAY: Out->RegY = In->RegA; + Out->ZNRegs = ZNREG_AY; + DeduceZN (Out, Out->RegY); break; case OP65_TRB: - if (E->AM == AM65_ZPX) { - /* Invalidates all ZP registers */ - RC_InvalidateZP (Out); - } else if (E->AM == AM65_ZP) { + Out->ZNRegs = ZNREG_NONE; + if (E->AM == AM65_ZP) { if (RegValIsKnown (In->RegA)) { switch (GetKnownReg (E->Chg & REG_ZP, In)) { case REG_TMP1: + Val = Out->Tmp1 & In->RegA; Out->Tmp1 &= ~In->RegA; break; case REG_PTR1_LO: + Val = Out->Ptr1Lo & In->RegA; Out->Ptr1Lo &= ~In->RegA; break; case REG_PTR1_HI: + Val = Out->Ptr1Hi & In->RegA; Out->Ptr1Hi &= ~In->RegA; break; case REG_SREG_LO: + Val = Out->SRegLo & In->RegA; Out->SRegLo &= ~In->RegA; break; case REG_SREG_HI: + Val = Out->SRegHi & In->RegA; Out->SRegHi &= ~In->RegA; break; } } else { - switch (GetKnownReg (E->Chg & REG_ZP, In)) { + switch (GetKnownReg (E->Chg & REG_ZP, 0)) { case REG_TMP1: Out->Tmp1 = UNKNOWN_REGVAL; break; @@ -1277,34 +1770,41 @@ void CE_GenRegInfo (CodeEntry* E, RegContents* InputRegs) break; } } + } else if (MightAffectKnownZP (E, In)) { + /* Invalidates all ZP registers */ + RC_InvalidateZP (Out); } + DeduceZ (Out, Val); break; case OP65_TSB: - if (E->AM == AM65_ZPX) { - /* Invalidates all ZP registers */ - RC_InvalidateZP (Out); - } else if (E->AM == AM65_ZP) { + Out->ZNRegs = ZNREG_NONE; + if (E->AM == AM65_ZP) { if (RegValIsKnown (In->RegA)) { switch (GetKnownReg (E->Chg & REG_ZP, In)) { case REG_TMP1: + Val = Out->Tmp1 & In->RegA; Out->Tmp1 |= In->RegA; break; case REG_PTR1_LO: + Val = Out->Ptr1Lo & In->RegA; Out->Ptr1Lo |= In->RegA; break; case REG_PTR1_HI: + Val = Out->Ptr1Hi & In->RegA; Out->Ptr1Hi |= In->RegA; break; case REG_SREG_LO: + Val = Out->SRegLo & In->RegA; Out->SRegLo |= In->RegA; break; case REG_SREG_HI: + Val = Out->SRegHi & In->RegA; Out->SRegHi |= In->RegA; break; } } else { - switch (GetKnownReg (E->Chg & REG_ZP, In)) { + switch (GetKnownReg (E->Chg & REG_ZP, 0)) { case REG_TMP1: Out->Tmp1 = UNKNOWN_REGVAL; break; @@ -1322,22 +1822,34 @@ void CE_GenRegInfo (CodeEntry* E, RegContents* InputRegs) break; } } + } else if (MightAffectKnownZP (E, In)) { + /* Invalidates all ZP registers */ + RC_InvalidateZP (Out); } + DeduceZ (Out, Val); break; case OP65_TSX: Out->RegX = UNKNOWN_REGVAL; + Out->PFlags |= UNKNOWN_PFVAL_ZN; + Out->ZNRegs = ZNREG_X; break; case OP65_TXA: Out->RegA = In->RegX; + Out->ZNRegs = ZNREG_AX; + DeduceZN (Out, Out->RegA); break; case OP65_TXS: + Out->ZNRegs = ZNREG_X; + DeduceZN (Out, In->RegX); break; case OP65_TYA: Out->RegA = In->RegY; + Out->ZNRegs = ZNREG_AY; + DeduceZN (Out, Out->RegA); break; default: diff --git a/src/cc65/codeent.h b/src/cc65/codeent.h index 96373a8f9..3d07670d7 100644 --- a/src/cc65/codeent.h +++ b/src/cc65/codeent.h @@ -73,8 +73,8 @@ struct CodeEntry { char* Arg; /* Argument as string */ unsigned long Num; /* Numeric argument */ unsigned short Info; /* Additional code info */ - unsigned short Use; /* Registers used */ - unsigned short Chg; /* Registers changed/destroyed */ + unsigned int Use; /* Registers used */ + unsigned int Chg; /* Registers changed/destroyed */ CodeLabel* JumpTo; /* Jump label */ Collection Labels; /* Labels for this instruction */ LineInfo* LI; /* Source line info for this insn */ diff --git a/src/cc65/codeinfo.c b/src/cc65/codeinfo.c index f51189293..892f4cd5f 100644 --- a/src/cc65/codeinfo.c +++ b/src/cc65/codeinfo.c @@ -77,8 +77,8 @@ static const char BoolTransformerTab [][8] = { typedef struct FuncInfo FuncInfo; struct FuncInfo { const char* Name; /* Function name */ - unsigned short Use; /* Register usage */ - unsigned short Chg; /* Changed/destroyed registers */ + unsigned Use; /* Register usage */ + unsigned Chg; /* Changed/destroyed registers */ }; /* Note for the shift functions: Shifts are done modulo 32, so all shift @@ -86,264 +86,264 @@ struct FuncInfo { ** anyway. */ static const FuncInfo FuncInfoTable[] = { - { "addeq0sp", REG_AX, REG_AXY }, - { "addeqysp", REG_AXY, REG_AXY }, - { "addysp", REG_Y, REG_NONE }, - { "aslax1", REG_AX, REG_AX | REG_TMP1 }, - { "aslax2", REG_AX, REG_AX | REG_TMP1 }, - { "aslax3", REG_AX, REG_AX | REG_TMP1 }, - { "aslax4", REG_AX, REG_AX | REG_TMP1 }, - { "aslaxy", REG_AXY, REG_AXY | REG_TMP1 }, - { "asleax1", REG_EAX, REG_EAX | REG_TMP1 }, - { "asleax2", REG_EAX, REG_EAX | REG_TMP1 }, - { "asleax3", REG_EAX, REG_EAX | REG_TMP1 }, - { "asleax4", REG_EAX, REG_EAXY | REG_TMP1 }, - { "asrax1", REG_AX, REG_AX | REG_TMP1 }, - { "asrax2", REG_AX, REG_AX | REG_TMP1 }, - { "asrax3", REG_AX, REG_AX | REG_TMP1 }, - { "asrax4", REG_AX, REG_AX | REG_TMP1 }, - { "asraxy", REG_AXY, REG_AXY | REG_TMP1 }, - { "asreax1", REG_EAX, REG_EAX | REG_TMP1 }, - { "asreax2", REG_EAX, REG_EAX | REG_TMP1 }, - { "asreax3", REG_EAX, REG_EAX | REG_TMP1 }, - { "asreax4", REG_EAX, REG_EAXY | REG_TMP1 }, - { "bcasta", REG_A, REG_AX }, - { "bcastax", REG_AX, REG_AX }, - { "bcasteax", REG_EAX, REG_EAX | REG_TMP1 }, - { "bnega", REG_A, REG_AX }, - { "bnegax", REG_AX, REG_AX }, - { "bnegeax", REG_EAX, REG_EAX | REG_TMP1 }, - { "booleq", REG_NONE, REG_AX }, - { "boolge", REG_NONE, REG_AX }, - { "boolgt", REG_NONE, REG_AX }, - { "boolle", REG_NONE, REG_AX }, - { "boollt", REG_NONE, REG_AX }, - { "boolne", REG_NONE, REG_AX }, - { "booluge", REG_NONE, REG_AX }, - { "boolugt", REG_NONE, REG_AX }, - { "boolule", REG_NONE, REG_AX }, - { "boolult", REG_NONE, REG_AX }, - { "callax", REG_AX, REG_ALL }, - { "complax", REG_AX, REG_AX }, - { "decax1", REG_AX, REG_AX }, - { "decax2", REG_AX, REG_AX }, - { "decax3", REG_AX, REG_AX }, - { "decax4", REG_AX, REG_AX }, - { "decax5", REG_AX, REG_AX }, - { "decax6", REG_AX, REG_AX }, - { "decax7", REG_AX, REG_AX }, - { "decax8", REG_AX, REG_AX }, - { "decaxy", REG_AXY, REG_AX | REG_TMP1 }, - { "deceaxy", REG_EAXY, REG_EAX }, - { "decsp1", REG_NONE, REG_Y }, - { "decsp2", REG_NONE, REG_A }, - { "decsp3", REG_NONE, REG_A }, - { "decsp4", REG_NONE, REG_A }, - { "decsp5", REG_NONE, REG_A }, - { "decsp6", REG_NONE, REG_A }, - { "decsp7", REG_NONE, REG_A }, - { "decsp8", REG_NONE, REG_A }, - { "incax1", REG_AX, REG_AX }, - { "incax2", REG_AX, REG_AX }, - { "incax3", REG_AX, REG_AXY | REG_TMP1 }, - { "incax4", REG_AX, REG_AXY | REG_TMP1 }, - { "incax5", REG_AX, REG_AXY | REG_TMP1 }, - { "incax6", REG_AX, REG_AXY | REG_TMP1 }, - { "incax7", REG_AX, REG_AXY | REG_TMP1 }, - { "incax8", REG_AX, REG_AXY | REG_TMP1 }, - { "incaxy", REG_AXY, REG_AXY | REG_TMP1 }, - { "incsp1", REG_NONE, REG_NONE }, - { "incsp2", REG_NONE, REG_Y }, - { "incsp3", REG_NONE, REG_Y }, - { "incsp4", REG_NONE, REG_Y }, - { "incsp5", REG_NONE, REG_Y }, - { "incsp6", REG_NONE, REG_Y }, - { "incsp7", REG_NONE, REG_Y }, - { "incsp8", REG_NONE, REG_Y }, - { "laddeq", REG_EAXY|REG_PTR1_LO, REG_EAXY | REG_PTR1_HI }, - { "laddeq0sp", REG_EAX, REG_EAXY }, - { "laddeq1", REG_Y | REG_PTR1_LO, REG_EAXY | REG_PTR1_HI }, - { "laddeqa", REG_AY | REG_PTR1_LO, REG_EAXY | REG_PTR1_HI }, - { "laddeqysp", REG_EAXY, REG_EAXY }, - { "ldaidx", REG_AXY, REG_AX | REG_PTR1 }, - { "ldauidx", REG_AXY, REG_AX | REG_PTR1 }, - { "ldax0sp", REG_NONE, REG_AXY }, - { "ldaxi", REG_AX, REG_AXY | REG_PTR1 }, - { "ldaxidx", REG_AXY, REG_AXY | REG_PTR1 }, - { "ldaxysp", REG_Y, REG_AXY }, - { "ldeax0sp", REG_NONE, REG_EAXY }, - { "ldeaxi", REG_AX, REG_EAXY | REG_PTR1 }, - { "ldeaxidx", REG_AXY, REG_EAXY | REG_PTR1 }, - { "ldeaxysp", REG_Y, REG_EAXY }, - { "leaa0sp", REG_A, REG_AX }, - { "leaaxsp", REG_AX, REG_AX }, - { "lsubeq", REG_EAXY|REG_PTR1_LO, REG_EAXY | REG_PTR1_HI }, - { "lsubeq0sp", REG_EAX, REG_EAXY }, - { "lsubeq1", REG_Y | REG_PTR1_LO, REG_EAXY | REG_PTR1_HI }, - { "lsubeqa", REG_AY | REG_PTR1_LO, REG_EAXY | REG_PTR1_HI }, - { "lsubeqysp", REG_EAXY, REG_EAXY }, - { "mulax10", REG_AX, REG_AX | REG_PTR1 }, - { "mulax3", REG_AX, REG_AX | REG_PTR1 }, - { "mulax5", REG_AX, REG_AX | REG_PTR1 }, - { "mulax6", REG_AX, REG_AX | REG_PTR1 }, - { "mulax7", REG_AX, REG_AX | REG_PTR1 }, - { "mulax9", REG_AX, REG_AX | REG_PTR1 }, - { "negax", REG_AX, REG_AX }, - { "push0", REG_NONE, REG_AXY }, - { "push0ax", REG_AX, REG_Y | REG_SREG }, - { "push1", REG_NONE, REG_AXY }, - { "push2", REG_NONE, REG_AXY }, - { "push3", REG_NONE, REG_AXY }, - { "push4", REG_NONE, REG_AXY }, - { "push5", REG_NONE, REG_AXY }, - { "push6", REG_NONE, REG_AXY }, - { "push7", REG_NONE, REG_AXY }, - { "pusha", REG_A, REG_Y }, - { "pusha0", REG_A, REG_XY }, - { "pusha0sp", REG_NONE, REG_AY }, - { "pushaFF", REG_A, REG_Y }, - { "pushax", REG_AX, REG_Y }, - { "pushaysp", REG_Y, REG_AY }, - { "pushc0", REG_NONE, REG_A | REG_Y }, - { "pushc1", REG_NONE, REG_A | REG_Y }, - { "pushc2", REG_NONE, REG_A | REG_Y }, - { "pusheax", REG_EAX, REG_Y }, - { "pushl0", REG_NONE, REG_AXY }, - { "pushw", REG_AX, REG_AXY | REG_PTR1 }, - { "pushw0sp", REG_NONE, REG_AXY }, - { "pushwidx", REG_AXY, REG_AXY | REG_PTR1 }, - { "pushwysp", REG_Y, REG_AXY }, - { "regswap", REG_AXY, REG_AXY | REG_TMP1 }, - { "regswap1", REG_XY, REG_A }, - { "regswap2", REG_XY, REG_A | REG_Y }, - { "return0", REG_NONE, REG_AX }, - { "return1", REG_NONE, REG_AX }, - { "shlax1", REG_AX, REG_AX | REG_TMP1 }, - { "shlax2", REG_AX, REG_AX | REG_TMP1 }, - { "shlax3", REG_AX, REG_AX | REG_TMP1 }, - { "shlax4", REG_AX, REG_AX | REG_TMP1 }, - { "shlaxy", REG_AXY, REG_AXY | REG_TMP1 }, - { "shleax1", REG_EAX, REG_EAX | REG_TMP1 }, - { "shleax2", REG_EAX, REG_EAX | REG_TMP1 }, - { "shleax3", REG_EAX, REG_EAX | REG_TMP1 }, - { "shleax4", REG_EAX, REG_EAXY | REG_TMP1 }, - { "shrax1", REG_AX, REG_AX | REG_TMP1 }, - { "shrax2", REG_AX, REG_AX | REG_TMP1 }, - { "shrax3", REG_AX, REG_AX | REG_TMP1 }, - { "shrax4", REG_AX, REG_AX | REG_TMP1 }, - { "shraxy", REG_AXY, REG_AXY | REG_TMP1 }, - { "shreax1", REG_EAX, REG_EAX | REG_TMP1 }, - { "shreax2", REG_EAX, REG_EAX | REG_TMP1 }, - { "shreax3", REG_EAX, REG_EAX | REG_TMP1 }, - { "shreax4", REG_EAX, REG_EAXY | REG_TMP1 }, - { "staspidx", REG_A | REG_Y, REG_Y | REG_TMP1 | REG_PTR1 }, - { "stax0sp", REG_AX, REG_Y }, - { "staxspidx", REG_AXY, REG_TMP1 | REG_PTR1 }, - { "staxysp", REG_AXY, REG_Y }, - { "steax0sp", REG_EAX, REG_Y }, - { "steaxysp", REG_EAXY, REG_Y }, - { "subeq0sp", REG_AX, REG_AXY }, - { "subeqysp", REG_AXY, REG_AXY }, - { "subysp", REG_Y, REG_AY }, - { "tosadd0ax", REG_AX, REG_EAXY | REG_TMP1 }, - { "tosadda0", REG_A, REG_AXY }, - { "tosaddax", REG_AX, REG_AXY }, - { "tosaddeax", REG_EAX, REG_EAXY | REG_TMP1 }, - { "tosand0ax", REG_AX, REG_EAXY | REG_TMP1 }, - { "tosanda0", REG_A, REG_AXY }, - { "tosandax", REG_AX, REG_AXY }, - { "tosandeax", REG_EAX, REG_EAXY | REG_TMP1 }, - { "tosaslax", REG_A, REG_AXY | REG_TMP1 }, - { "tosasleax", REG_A, REG_EAXY | REG_TMP1 }, - { "tosasrax", REG_A, REG_AXY | REG_TMP1 }, - { "tosasreax", REG_A, REG_EAXY | REG_TMP1 }, - { "tosdiv0ax", REG_AX, REG_ALL }, - { "tosdiva0", REG_A, REG_ALL }, - { "tosdivax", REG_AX, REG_ALL }, - { "tosdiveax", REG_EAX, REG_ALL }, - { "toseq00", REG_NONE, REG_AXY | REG_SREG }, - { "toseqa0", REG_A, REG_AXY | REG_SREG }, - { "toseqax", REG_AX, REG_AXY | REG_SREG }, - { "toseqeax", REG_EAX, REG_AXY | REG_PTR1 }, - { "tosge00", REG_NONE, REG_AXY | REG_SREG }, - { "tosgea0", REG_A, REG_AXY | REG_SREG }, - { "tosgeax", REG_AX, REG_AXY | REG_SREG }, - { "tosgeeax", REG_EAX, REG_AXY | REG_PTR1 }, - { "tosgt00", REG_NONE, REG_AXY | REG_SREG }, - { "tosgta0", REG_A, REG_AXY | REG_SREG }, - { "tosgtax", REG_AX, REG_AXY | REG_SREG }, - { "tosgteax", REG_EAX, REG_AXY | REG_PTR1 }, - { "tosicmp", REG_AX, REG_AXY | REG_SREG }, - { "tosicmp0", REG_A, REG_AXY | REG_SREG }, - { "toslcmp", REG_EAX, REG_A | REG_Y | REG_PTR1 }, - { "tosle00", REG_NONE, REG_AXY | REG_SREG }, - { "toslea0", REG_A, REG_AXY | REG_SREG }, - { "tosleax", REG_AX, REG_AXY | REG_SREG }, - { "tosleeax", REG_EAX, REG_AXY | REG_PTR1 }, - { "toslt00", REG_NONE, REG_AXY | REG_SREG }, - { "toslta0", REG_A, REG_AXY | REG_SREG }, - { "tosltax", REG_AX, REG_AXY | REG_SREG }, - { "toslteax", REG_EAX, REG_AXY | REG_PTR1 }, - { "tosmod0ax", REG_AX, REG_ALL }, - { "tosmodeax", REG_EAX, REG_ALL }, - { "tosmul0ax", REG_AX, REG_ALL }, - { "tosmula0", REG_A, REG_ALL }, - { "tosmulax", REG_AX, REG_ALL }, - { "tosmuleax", REG_EAX, REG_ALL }, - { "tosne00", REG_NONE, REG_AXY | REG_SREG }, - { "tosnea0", REG_A, REG_AXY | REG_SREG }, - { "tosneax", REG_AX, REG_AXY | REG_SREG }, - { "tosneeax", REG_EAX, REG_AXY | REG_PTR1 }, - { "tosor0ax", REG_AX, REG_EAXY | REG_TMP1 }, - { "tosora0", REG_A, REG_AXY | REG_TMP1 }, - { "tosorax", REG_AX, REG_AXY | REG_TMP1 }, - { "tosoreax", REG_EAX, REG_EAXY | REG_TMP1 }, - { "tosrsub0ax", REG_AX, REG_EAXY | REG_TMP1 }, - { "tosrsuba0", REG_A, REG_AXY | REG_TMP1 }, - { "tosrsubax", REG_AX, REG_AXY | REG_TMP1 }, - { "tosrsubeax", REG_EAX, REG_EAXY | REG_TMP1 }, - { "tosshlax", REG_A, REG_AXY | REG_TMP1 }, - { "tosshleax", REG_A, REG_EAXY | REG_TMP1 }, - { "tosshrax", REG_A, REG_AXY | REG_TMP1 }, - { "tosshreax", REG_A, REG_EAXY | REG_TMP1 }, - { "tossub0ax", REG_AX, REG_EAXY }, - { "tossuba0", REG_A, REG_AXY }, - { "tossubax", REG_AX, REG_AXY }, - { "tossubeax", REG_EAX, REG_EAXY }, - { "tosudiv0ax", REG_AX, REG_ALL & ~REG_SAVE }, - { "tosudiva0", REG_A, REG_EAXY | REG_PTR1 }, /* also ptr4 */ - { "tosudivax", REG_AX, REG_EAXY | REG_PTR1 }, /* also ptr4 */ - { "tosudiveax", REG_EAX, REG_ALL & ~REG_SAVE }, - { "tosuge00", REG_NONE, REG_AXY | REG_SREG }, - { "tosugea0", REG_A, REG_AXY | REG_SREG }, - { "tosugeax", REG_AX, REG_AXY | REG_SREG }, - { "tosugeeax", REG_EAX, REG_AXY | REG_PTR1 }, - { "tosugt00", REG_NONE, REG_AXY | REG_SREG }, - { "tosugta0", REG_A, REG_AXY | REG_SREG }, - { "tosugtax", REG_AX, REG_AXY | REG_SREG }, - { "tosugteax", REG_EAX, REG_AXY | REG_PTR1 }, - { "tosule00", REG_NONE, REG_AXY | REG_SREG }, - { "tosulea0", REG_A, REG_AXY | REG_SREG }, - { "tosuleax", REG_AX, REG_AXY | REG_SREG }, - { "tosuleeax", REG_EAX, REG_AXY | REG_PTR1 }, - { "tosult00", REG_NONE, REG_AXY | REG_SREG }, - { "tosulta0", REG_A, REG_AXY | REG_SREG }, - { "tosultax", REG_AX, REG_AXY | REG_SREG }, - { "tosulteax", REG_EAX, REG_AXY | REG_PTR1 }, - { "tosumod0ax", REG_AX, REG_ALL & ~REG_SAVE }, - { "tosumoda0", REG_A, REG_EAXY | REG_PTR1 }, /* also ptr4 */ - { "tosumodax", REG_AX, REG_EAXY | REG_PTR1 }, /* also ptr4 */ - { "tosumodeax", REG_EAX, REG_ALL & ~REG_SAVE }, - { "tosumul0ax", REG_AX, REG_ALL }, - { "tosumula0", REG_A, REG_ALL }, - { "tosumulax", REG_AX, REG_ALL }, - { "tosumuleax", REG_EAX, REG_ALL }, - { "tosxor0ax", REG_AX, REG_EAXY | REG_TMP1 }, - { "tosxora0", REG_A, REG_AXY | REG_TMP1 }, - { "tosxorax", REG_AX, REG_AXY | REG_TMP1 }, - { "tosxoreax", REG_EAX, REG_EAXY | REG_TMP1 }, - { "tsteax", REG_EAX, REG_Y }, - { "utsteax", REG_EAX, REG_Y }, + { "addeq0sp", REG_AX, PSTATE_ALL | REG_AXY }, + { "addeqysp", REG_AXY, PSTATE_ALL | REG_AXY }, + { "addysp", REG_Y, PSTATE_ALL | REG_NONE }, + { "aslax1", REG_AX, PSTATE_ALL | REG_AX | REG_TMP1 }, + { "aslax2", REG_AX, PSTATE_ALL | REG_AX | REG_TMP1 }, + { "aslax3", REG_AX, PSTATE_ALL | REG_AX | REG_TMP1 }, + { "aslax4", REG_AX, PSTATE_ALL | REG_AX | REG_TMP1 }, + { "aslaxy", REG_AXY, PSTATE_ALL | REG_AXY | REG_TMP1 }, + { "asleax1", REG_EAX, PSTATE_ALL | REG_EAX | REG_TMP1 }, + { "asleax2", REG_EAX, PSTATE_ALL | REG_EAX | REG_TMP1 }, + { "asleax3", REG_EAX, PSTATE_ALL | REG_EAX | REG_TMP1 }, + { "asleax4", REG_EAX, PSTATE_ALL | REG_EAXY | REG_TMP1 }, + { "asrax1", REG_AX, PSTATE_ALL | REG_AX | REG_TMP1 }, + { "asrax2", REG_AX, PSTATE_ALL | REG_AX | REG_TMP1 }, + { "asrax3", REG_AX, PSTATE_ALL | REG_AX | REG_TMP1 }, + { "asrax4", REG_AX, PSTATE_ALL | REG_AX | REG_TMP1 }, + { "asraxy", REG_AXY, PSTATE_ALL | REG_AXY | REG_TMP1 }, + { "asreax1", REG_EAX, PSTATE_ALL | REG_EAX | REG_TMP1 }, + { "asreax2", REG_EAX, PSTATE_ALL | REG_EAX | REG_TMP1 }, + { "asreax3", REG_EAX, PSTATE_ALL | REG_EAX | REG_TMP1 }, + { "asreax4", REG_EAX, PSTATE_ALL | REG_EAXY | REG_TMP1 }, + { "bcasta", REG_A, PSTATE_ALL | REG_AX }, + { "bcastax", REG_AX, PSTATE_ALL | REG_AX }, + { "bcasteax", REG_EAX, PSTATE_ALL | REG_EAX | REG_TMP1 }, + { "bnega", REG_A, PSTATE_ALL | REG_AX }, + { "bnegax", REG_AX, PSTATE_ALL | REG_AX }, + { "bnegeax", REG_EAX, PSTATE_ALL | REG_EAX | REG_TMP1 }, + { "booleq", PSTATE_Z, PSTATE_ALL | REG_AX }, + { "boolge", PSTATE_N, PSTATE_ALL | REG_AX }, + { "boolgt", PSTATE_ZN, PSTATE_ALL | REG_AX }, + { "boolle", PSTATE_ZN, PSTATE_ALL | REG_AX }, + { "boollt", PSTATE_N, PSTATE_ALL | REG_AX }, + { "boolne", PSTATE_Z, PSTATE_ALL | REG_AX }, + { "booluge", PSTATE_C, PSTATE_ALL | REG_AX }, + { "boolugt", PSTATE_CZ, PSTATE_ALL | REG_AX }, + { "boolule", PSTATE_CZ, PSTATE_ALL | REG_AX }, + { "boolult", PSTATE_C, PSTATE_ALL | REG_AX }, + { "callax", REG_AX, PSTATE_ALL | REG_ALL }, + { "complax", REG_AX, PSTATE_ALL | REG_AX }, + { "decax1", REG_AX, PSTATE_ALL | REG_AX }, + { "decax2", REG_AX, PSTATE_ALL | REG_AX }, + { "decax3", REG_AX, PSTATE_ALL | REG_AX }, + { "decax4", REG_AX, PSTATE_ALL | REG_AX }, + { "decax5", REG_AX, PSTATE_ALL | REG_AX }, + { "decax6", REG_AX, PSTATE_ALL | REG_AX }, + { "decax7", REG_AX, PSTATE_ALL | REG_AX }, + { "decax8", REG_AX, PSTATE_ALL | REG_AX }, + { "decaxy", REG_AXY, PSTATE_ALL | REG_AX | REG_TMP1 }, + { "deceaxy", REG_EAXY, PSTATE_ALL | REG_EAX }, + { "decsp1", REG_NONE, PSTATE_ALL | REG_Y }, + { "decsp2", REG_NONE, PSTATE_ALL | REG_A }, + { "decsp3", REG_NONE, PSTATE_ALL | REG_A }, + { "decsp4", REG_NONE, PSTATE_ALL | REG_A }, + { "decsp5", REG_NONE, PSTATE_ALL | REG_A }, + { "decsp6", REG_NONE, PSTATE_ALL | REG_A }, + { "decsp7", REG_NONE, PSTATE_ALL | REG_A }, + { "decsp8", REG_NONE, PSTATE_ALL | REG_A }, + { "incax1", REG_AX, PSTATE_ALL | REG_AX }, + { "incax2", REG_AX, PSTATE_ALL | REG_AX }, + { "incax3", REG_AX, PSTATE_ALL | REG_AXY | REG_TMP1 }, + { "incax4", REG_AX, PSTATE_ALL | REG_AXY | REG_TMP1 }, + { "incax5", REG_AX, PSTATE_ALL | REG_AXY | REG_TMP1 }, + { "incax6", REG_AX, PSTATE_ALL | REG_AXY | REG_TMP1 }, + { "incax7", REG_AX, PSTATE_ALL | REG_AXY | REG_TMP1 }, + { "incax8", REG_AX, PSTATE_ALL | REG_AXY | REG_TMP1 }, + { "incaxy", REG_AXY, PSTATE_ALL | REG_AXY | REG_TMP1 }, + { "incsp1", REG_NONE, PSTATE_ALL | REG_NONE }, + { "incsp2", REG_NONE, PSTATE_ALL | REG_Y }, + { "incsp3", REG_NONE, PSTATE_ALL | REG_Y }, + { "incsp4", REG_NONE, PSTATE_ALL | REG_Y }, + { "incsp5", REG_NONE, PSTATE_ALL | REG_Y }, + { "incsp6", REG_NONE, PSTATE_ALL | REG_Y }, + { "incsp7", REG_NONE, PSTATE_ALL | REG_Y }, + { "incsp8", REG_NONE, PSTATE_ALL | REG_Y }, + { "laddeq", REG_EAXY|REG_PTR1_LO, PSTATE_ALL | REG_EAXY | REG_PTR1_HI }, + { "laddeq0sp", REG_EAX, PSTATE_ALL | REG_EAXY }, + { "laddeq1", REG_Y | REG_PTR1_LO, PSTATE_ALL | REG_EAXY | REG_PTR1_HI }, + { "laddeqa", REG_AY | REG_PTR1_LO, PSTATE_ALL | REG_EAXY | REG_PTR1_HI }, + { "laddeqysp", REG_EAXY, PSTATE_ALL | REG_EAXY }, + { "ldaidx", REG_AXY, PSTATE_ALL | REG_AX | REG_PTR1 }, + { "ldauidx", REG_AXY, PSTATE_ALL | REG_AX | REG_PTR1 }, + { "ldax0sp", REG_NONE, PSTATE_ALL | REG_AXY }, + { "ldaxi", REG_AX, PSTATE_ALL | REG_AXY | REG_PTR1 }, + { "ldaxidx", REG_AXY, PSTATE_ALL | REG_AXY | REG_PTR1 }, + { "ldaxysp", REG_Y, PSTATE_ALL | REG_AXY }, + { "ldeax0sp", REG_NONE, PSTATE_ALL | REG_EAXY }, + { "ldeaxi", REG_AX, PSTATE_ALL | REG_EAXY | REG_PTR1 }, + { "ldeaxidx", REG_AXY, PSTATE_ALL | REG_EAXY | REG_PTR1 }, + { "ldeaxysp", REG_Y, PSTATE_ALL | REG_EAXY }, + { "leaa0sp", REG_A, PSTATE_ALL | REG_AX }, + { "leaaxsp", REG_AX, PSTATE_ALL | REG_AX }, + { "lsubeq", REG_EAXY|REG_PTR1_LO, PSTATE_ALL | REG_EAXY | REG_PTR1_HI }, + { "lsubeq0sp", REG_EAX, PSTATE_ALL | REG_EAXY }, + { "lsubeq1", REG_Y | REG_PTR1_LO, PSTATE_ALL | REG_EAXY | REG_PTR1_HI }, + { "lsubeqa", REG_AY | REG_PTR1_LO, PSTATE_ALL | REG_EAXY | REG_PTR1_HI }, + { "lsubeqysp", REG_EAXY, PSTATE_ALL | REG_EAXY }, + { "mulax10", REG_AX, PSTATE_ALL | REG_AX | REG_PTR1 }, + { "mulax3", REG_AX, PSTATE_ALL | REG_AX | REG_PTR1 }, + { "mulax5", REG_AX, PSTATE_ALL | REG_AX | REG_PTR1 }, + { "mulax6", REG_AX, PSTATE_ALL | REG_AX | REG_PTR1 }, + { "mulax7", REG_AX, PSTATE_ALL | REG_AX | REG_PTR1 }, + { "mulax9", REG_AX, PSTATE_ALL | REG_AX | REG_PTR1 }, + { "negax", REG_AX, PSTATE_ALL | REG_AX }, + { "push0", REG_NONE, PSTATE_ALL | REG_AXY }, + { "push0ax", REG_AX, PSTATE_ALL | REG_Y | REG_SREG }, + { "push1", REG_NONE, PSTATE_ALL | REG_AXY }, + { "push2", REG_NONE, PSTATE_ALL | REG_AXY }, + { "push3", REG_NONE, PSTATE_ALL | REG_AXY }, + { "push4", REG_NONE, PSTATE_ALL | REG_AXY }, + { "push5", REG_NONE, PSTATE_ALL | REG_AXY }, + { "push6", REG_NONE, PSTATE_ALL | REG_AXY }, + { "push7", REG_NONE, PSTATE_ALL | REG_AXY }, + { "pusha", REG_A, PSTATE_ALL | REG_Y }, + { "pusha0", REG_A, PSTATE_ALL | REG_XY }, + { "pusha0sp", REG_NONE, PSTATE_ALL | REG_AY }, + { "pushaFF", REG_A, PSTATE_ALL | REG_Y }, + { "pushax", REG_AX, PSTATE_ALL | REG_Y }, + { "pushaysp", REG_Y, PSTATE_ALL | REG_AY }, + { "pushc0", REG_NONE, PSTATE_ALL | REG_A | REG_Y }, + { "pushc1", REG_NONE, PSTATE_ALL | REG_A | REG_Y }, + { "pushc2", REG_NONE, PSTATE_ALL | REG_A | REG_Y }, + { "pusheax", REG_EAX, PSTATE_ALL | REG_Y }, + { "pushl0", REG_NONE, PSTATE_ALL | REG_AXY }, + { "pushw", REG_AX, PSTATE_ALL | REG_AXY | REG_PTR1 }, + { "pushw0sp", REG_NONE, PSTATE_ALL | REG_AXY }, + { "pushwidx", REG_AXY, PSTATE_ALL | REG_AXY | REG_PTR1 }, + { "pushwysp", REG_Y, PSTATE_ALL | REG_AXY }, + { "regswap", REG_AXY, PSTATE_ALL | REG_AXY | REG_TMP1 }, + { "regswap1", REG_XY, PSTATE_ALL | REG_A }, + { "regswap2", REG_XY, PSTATE_ALL | REG_A | REG_Y }, + { "return0", REG_NONE, PSTATE_ALL | REG_AX }, + { "return1", REG_NONE, PSTATE_ALL | REG_AX }, + { "shlax1", REG_AX, PSTATE_ALL | REG_AX | REG_TMP1 }, + { "shlax2", REG_AX, PSTATE_ALL | REG_AX | REG_TMP1 }, + { "shlax3", REG_AX, PSTATE_ALL | REG_AX | REG_TMP1 }, + { "shlax4", REG_AX, PSTATE_ALL | REG_AX | REG_TMP1 }, + { "shlaxy", REG_AXY, PSTATE_ALL | REG_AXY | REG_TMP1 }, + { "shleax1", REG_EAX, PSTATE_ALL | REG_EAX | REG_TMP1 }, + { "shleax2", REG_EAX, PSTATE_ALL | REG_EAX | REG_TMP1 }, + { "shleax3", REG_EAX, PSTATE_ALL | REG_EAX | REG_TMP1 }, + { "shleax4", REG_EAX, PSTATE_ALL | REG_EAXY | REG_TMP1 }, + { "shrax1", REG_AX, PSTATE_ALL | REG_AX | REG_TMP1 }, + { "shrax2", REG_AX, PSTATE_ALL | REG_AX | REG_TMP1 }, + { "shrax3", REG_AX, PSTATE_ALL | REG_AX | REG_TMP1 }, + { "shrax4", REG_AX, PSTATE_ALL | REG_AX | REG_TMP1 }, + { "shraxy", REG_AXY, PSTATE_ALL | REG_AXY | REG_TMP1 }, + { "shreax1", REG_EAX, PSTATE_ALL | REG_EAX | REG_TMP1 }, + { "shreax2", REG_EAX, PSTATE_ALL | REG_EAX | REG_TMP1 }, + { "shreax3", REG_EAX, PSTATE_ALL | REG_EAX | REG_TMP1 }, + { "shreax4", REG_EAX, PSTATE_ALL | REG_EAXY | REG_TMP1 }, + { "staspidx", REG_A | REG_Y, PSTATE_ALL | REG_Y | REG_TMP1 | REG_PTR1 }, + { "stax0sp", REG_AX, PSTATE_ALL | REG_Y }, + { "staxspidx", REG_AXY, PSTATE_ALL | REG_TMP1 | REG_PTR1 }, + { "staxysp", REG_AXY, PSTATE_ALL | REG_Y }, + { "steax0sp", REG_EAX, PSTATE_ALL | REG_Y }, + { "steaxysp", REG_EAXY, PSTATE_ALL | REG_Y }, + { "subeq0sp", REG_AX, PSTATE_ALL | REG_AXY }, + { "subeqysp", REG_AXY, PSTATE_ALL | REG_AXY }, + { "subysp", REG_Y, PSTATE_ALL | REG_AY }, + { "tosadd0ax", REG_AX, PSTATE_ALL | REG_EAXY | REG_TMP1 }, + { "tosadda0", REG_A, PSTATE_ALL | REG_AXY }, + { "tosaddax", REG_AX, PSTATE_ALL | REG_AXY }, + { "tosaddeax", REG_EAX, PSTATE_ALL | REG_EAXY | REG_TMP1 }, + { "tosand0ax", REG_AX, PSTATE_ALL | REG_EAXY | REG_TMP1 }, + { "tosanda0", REG_A, PSTATE_ALL | REG_AXY }, + { "tosandax", REG_AX, PSTATE_ALL | REG_AXY }, + { "tosandeax", REG_EAX, PSTATE_ALL | REG_EAXY | REG_TMP1 }, + { "tosaslax", REG_A, PSTATE_ALL | REG_AXY | REG_TMP1 }, + { "tosasleax", REG_A, PSTATE_ALL | REG_EAXY | REG_TMP1 }, + { "tosasrax", REG_A, PSTATE_ALL | REG_AXY | REG_TMP1 }, + { "tosasreax", REG_A, PSTATE_ALL | REG_EAXY | REG_TMP1 }, + { "tosdiv0ax", REG_AX, PSTATE_ALL | REG_ALL }, + { "tosdiva0", REG_A, PSTATE_ALL | REG_ALL }, + { "tosdivax", REG_AX, PSTATE_ALL | REG_ALL }, + { "tosdiveax", REG_EAX, PSTATE_ALL | REG_ALL }, + { "toseq00", REG_NONE, PSTATE_ALL | REG_AXY | REG_SREG }, + { "toseqa0", REG_A, PSTATE_ALL | REG_AXY | REG_SREG }, + { "toseqax", REG_AX, PSTATE_ALL | REG_AXY | REG_SREG }, + { "toseqeax", REG_EAX, PSTATE_ALL | REG_AXY | REG_PTR1 }, + { "tosge00", REG_NONE, PSTATE_ALL | REG_AXY | REG_SREG }, + { "tosgea0", REG_A, PSTATE_ALL | REG_AXY | REG_SREG }, + { "tosgeax", REG_AX, PSTATE_ALL | REG_AXY | REG_SREG }, + { "tosgeeax", REG_EAX, PSTATE_ALL | REG_AXY | REG_PTR1 }, + { "tosgt00", REG_NONE, PSTATE_ALL | REG_AXY | REG_SREG }, + { "tosgta0", REG_A, PSTATE_ALL | REG_AXY | REG_SREG }, + { "tosgtax", REG_AX, PSTATE_ALL | REG_AXY | REG_SREG }, + { "tosgteax", REG_EAX, PSTATE_ALL | REG_AXY | REG_PTR1 }, + { "tosicmp", REG_AX, PSTATE_ALL | REG_AXY | REG_SREG }, + { "tosicmp0", REG_A, PSTATE_ALL | REG_AXY | REG_SREG }, + { "toslcmp", REG_EAX, PSTATE_ALL | REG_A | REG_Y | REG_PTR1 }, + { "tosle00", REG_NONE, PSTATE_ALL | REG_AXY | REG_SREG }, + { "toslea0", REG_A, PSTATE_ALL | REG_AXY | REG_SREG }, + { "tosleax", REG_AX, PSTATE_ALL | REG_AXY | REG_SREG }, + { "tosleeax", REG_EAX, PSTATE_ALL | REG_AXY | REG_PTR1 }, + { "toslt00", REG_NONE, PSTATE_ALL | REG_AXY | REG_SREG }, + { "toslta0", REG_A, PSTATE_ALL | REG_AXY | REG_SREG }, + { "tosltax", REG_AX, PSTATE_ALL | REG_AXY | REG_SREG }, + { "toslteax", REG_EAX, PSTATE_ALL | REG_AXY | REG_PTR1 }, + { "tosmod0ax", REG_AX, PSTATE_ALL | REG_ALL }, + { "tosmodeax", REG_EAX, PSTATE_ALL | REG_ALL }, + { "tosmul0ax", REG_AX, PSTATE_ALL | REG_ALL }, + { "tosmula0", REG_A, PSTATE_ALL | REG_ALL }, + { "tosmulax", REG_AX, PSTATE_ALL | REG_ALL }, + { "tosmuleax", REG_EAX, PSTATE_ALL | REG_ALL }, + { "tosne00", REG_NONE, PSTATE_ALL | REG_AXY | REG_SREG }, + { "tosnea0", REG_A, PSTATE_ALL | REG_AXY | REG_SREG }, + { "tosneax", REG_AX, PSTATE_ALL | REG_AXY | REG_SREG }, + { "tosneeax", REG_EAX, PSTATE_ALL | REG_AXY | REG_PTR1 }, + { "tosor0ax", REG_AX, PSTATE_ALL | REG_EAXY | REG_TMP1 }, + { "tosora0", REG_A, PSTATE_ALL | REG_AXY | REG_TMP1 }, + { "tosorax", REG_AX, PSTATE_ALL | REG_AXY | REG_TMP1 }, + { "tosoreax", REG_EAX, PSTATE_ALL | REG_EAXY | REG_TMP1 }, + { "tosrsub0ax", REG_AX, PSTATE_ALL | REG_EAXY | REG_TMP1 }, + { "tosrsuba0", REG_A, PSTATE_ALL | REG_AXY | REG_TMP1 }, + { "tosrsubax", REG_AX, PSTATE_ALL | REG_AXY | REG_TMP1 }, + { "tosrsubeax", REG_EAX, PSTATE_ALL | REG_EAXY | REG_TMP1 }, + { "tosshlax", REG_A, PSTATE_ALL | REG_AXY | REG_TMP1 }, + { "tosshleax", REG_A, PSTATE_ALL | REG_EAXY | REG_TMP1 }, + { "tosshrax", REG_A, PSTATE_ALL | REG_AXY | REG_TMP1 }, + { "tosshreax", REG_A, PSTATE_ALL | REG_EAXY | REG_TMP1 }, + { "tossub0ax", REG_AX, PSTATE_ALL | REG_EAXY }, + { "tossuba0", REG_A, PSTATE_ALL | REG_AXY }, + { "tossubax", REG_AX, PSTATE_ALL | REG_AXY }, + { "tossubeax", REG_EAX, PSTATE_ALL | REG_EAXY }, + { "tosudiv0ax", REG_AX, PSTATE_ALL | (REG_ALL & ~REG_SAVE) }, + { "tosudiva0", REG_A, PSTATE_ALL | REG_EAXY | REG_PTR1 }, /* also ptr4 */ + { "tosudivax", REG_AX, PSTATE_ALL | REG_EAXY | REG_PTR1 }, /* also ptr4 */ + { "tosudiveax", REG_EAX, PSTATE_ALL | (REG_ALL & ~REG_SAVE) }, + { "tosuge00", REG_NONE, PSTATE_ALL | REG_AXY | REG_SREG }, + { "tosugea0", REG_A, PSTATE_ALL | REG_AXY | REG_SREG }, + { "tosugeax", REG_AX, PSTATE_ALL | REG_AXY | REG_SREG }, + { "tosugeeax", REG_EAX, PSTATE_ALL | REG_AXY | REG_PTR1 }, + { "tosugt00", REG_NONE, PSTATE_ALL | REG_AXY | REG_SREG }, + { "tosugta0", REG_A, PSTATE_ALL | REG_AXY | REG_SREG }, + { "tosugtax", REG_AX, PSTATE_ALL | REG_AXY | REG_SREG }, + { "tosugteax", REG_EAX, PSTATE_ALL | REG_AXY | REG_PTR1 }, + { "tosule00", REG_NONE, PSTATE_ALL | REG_AXY | REG_SREG }, + { "tosulea0", REG_A, PSTATE_ALL | REG_AXY | REG_SREG }, + { "tosuleax", REG_AX, PSTATE_ALL | REG_AXY | REG_SREG }, + { "tosuleeax", REG_EAX, PSTATE_ALL | REG_AXY | REG_PTR1 }, + { "tosult00", REG_NONE, PSTATE_ALL | REG_AXY | REG_SREG }, + { "tosulta0", REG_A, PSTATE_ALL | REG_AXY | REG_SREG }, + { "tosultax", REG_AX, PSTATE_ALL | REG_AXY | REG_SREG }, + { "tosulteax", REG_EAX, PSTATE_ALL | REG_AXY | REG_PTR1 }, + { "tosumod0ax", REG_AX, PSTATE_ALL | (REG_ALL & ~REG_SAVE) }, + { "tosumoda0", REG_A, PSTATE_ALL | REG_EAXY | REG_PTR1 }, /* also ptr4 */ + { "tosumodax", REG_AX, PSTATE_ALL | REG_EAXY | REG_PTR1 }, /* also ptr4 */ + { "tosumodeax", REG_EAX, PSTATE_ALL | (REG_ALL & ~REG_SAVE) }, + { "tosumul0ax", REG_AX, PSTATE_ALL | REG_ALL }, + { "tosumula0", REG_A, PSTATE_ALL | REG_ALL }, + { "tosumulax", REG_AX, PSTATE_ALL | REG_ALL }, + { "tosumuleax", REG_EAX, PSTATE_ALL | REG_ALL }, + { "tosxor0ax", REG_AX, PSTATE_ALL | REG_EAXY | REG_TMP1 }, + { "tosxora0", REG_A, PSTATE_ALL | REG_AXY | REG_TMP1 }, + { "tosxorax", REG_AX, PSTATE_ALL | REG_AXY | REG_TMP1 }, + { "tosxoreax", REG_EAX, PSTATE_ALL | REG_EAXY | REG_TMP1 }, + { "tsteax", REG_EAX, PSTATE_ALL | REG_Y }, + { "utsteax", REG_EAX, PSTATE_ALL | REG_Y }, }; #define FuncInfoCount (sizeof(FuncInfoTable) / sizeof(FuncInfoTable[0])) @@ -385,10 +385,10 @@ static int CompareFuncInfo (const void* Key, const void* Info) -fncls_t GetFuncInfo (const char* Name, unsigned short* Use, unsigned short* Chg) +fncls_t GetFuncInfo (const char* Name, unsigned int* Use, unsigned int* Chg) /* For the given function, lookup register information and store it into ** the given variables. If the function is unknown, assume it will use and -** load all registers. +** load all registers as well as touching the processor flags. */ { /* If the function name starts with an underline, it is an external @@ -441,6 +441,9 @@ fncls_t GetFuncInfo (const char* Name, unsigned short* Use, unsigned short* Chg) /* Will destroy all registers */ *Chg = REG_ALL; + /* and will destroy all processor flags */ + *Chg |= PSTATE_ALL; + /* Done */ return FNCLS_GLOBAL; } @@ -453,6 +456,7 @@ fncls_t GetFuncInfo (const char* Name, unsigned short* Use, unsigned short* Chg) */ *Use = REG_ALL; *Chg = REG_ALL; + *Chg |= PSTATE_ALL; return FNCLS_NUMERIC; } else { @@ -477,15 +481,17 @@ fncls_t GetFuncInfo (const char* Name, unsigned short* Use, unsigned short* Chg) } *Use = REG_ALL; *Chg = REG_ALL; + *Chg |= PSTATE_ALL; } return FNCLS_BUILTIN; } /* Function not found - assume that the primary register is input, and all - ** registers are changed + ** registers and processor flags are changed */ *Use = REG_EAXY; *Chg = REG_ALL; + *Chg |= PSTATE_ALL; return FNCLS_UNKNOWN; } diff --git a/src/cc65/codeinfo.h b/src/cc65/codeinfo.h index 763b947bf..32bc5dd9c 100644 --- a/src/cc65/codeinfo.h +++ b/src/cc65/codeinfo.h @@ -57,7 +57,7 @@ struct CodeSeg; /* Forward to struct RegContents */ struct RegContents; -/* Defines for registers. */ +/* Defines for registers */ #define REG_NONE 0x0000U #define REG_A 0x0001U #define REG_X 0x0002U @@ -74,6 +74,21 @@ struct RegContents; #define REG_SP_LO 0x1000U #define REG_SP_HI 0x2000U +/* Defines for some special register usage */ +#define SLV_SP65 0x00200000U /* Accesses 6502 stack pointer */ +#define SLV_PH65 0x00400000U /* Pushes onto 6502 stack */ +#define SLV_PL65 0x00800000U /* Pops from 6502 stack */ + +/* Defines for processor states */ +#define PSTATE_NONE 0x00000000U +#define PSTATE_C 0x01000000U /* Carry */ +#define PSTATE_Z 0x02000000U /* Zero */ +#define PSTATE_I 0x04000000U /* Interrupt */ +#define PSTATE_D 0x08000000U /* Decimal */ +#define PSTATE_U 0x10000000U /* Unused */ +#define PSTATE_B 0x20000000U /* Break */ +#define PSTATE_V 0x40000000U /* Overflow */ +#define PSTATE_N 0x80000000U /* Negative */ /* Combined register defines */ #define REG_PTR1 (REG_PTR1_LO | REG_PTR1_HI) @@ -89,6 +104,14 @@ struct RegContents; #define REG_EAXY (REG_EAX | REG_Y) #define REG_ZP 0xFFF8U #define REG_ALL 0xFFFFU +#define PSTATE_CZ (PSTATE_C | PSTATE_Z) +#define PSTATE_CZN (PSTATE_C | PSTATE_Z | PSTATE_N) +#define PSTATE_CZVN (PSTATE_C | PSTATE_Z | PSTATE_V | PSTATE_N) +#define PSTATE_ZN (PSTATE_Z | PSTATE_N) +#define PSTATE_ZVN (PSTATE_Z | PSTATE_V | PSTATE_N) +#define PSTATE_6502 0xE7000000U +#define PSTATE_ALL 0xFF000000U +#define REG_EVERYTHING 0xFFFFFFFFU @@ -139,7 +162,7 @@ typedef enum { -fncls_t GetFuncInfo (const char* Name, unsigned short* Use, unsigned short* Chg); +fncls_t GetFuncInfo (const char* Name, unsigned int* Use, unsigned int* Chg); /* For the given function, lookup register information and store it into ** the given variables. If the function is unknown, assume it will use and ** load all registers. diff --git a/src/cc65/codeseg.c b/src/cc65/codeseg.c index f2e0faf15..ad8a3148c 100644 --- a/src/cc65/codeseg.c +++ b/src/cc65/codeseg.c @@ -1468,6 +1468,7 @@ void CS_GenRegInfo (CodeSeg* S) /* On entry, the register contents are unknown */ RC_Invalidate (&Regs); + RC_InvalidatePS (&Regs); CurrentRegs = &Regs; /* Walk over all insns and note just the changes from one insn to the @@ -1502,6 +1503,7 @@ void CS_GenRegInfo (CodeSeg* S) Regs = J->RI->Out2; } else { RC_Invalidate (&Regs); + RC_InvalidatePS (&Regs); } Entry = 1; } else { @@ -1521,6 +1523,7 @@ void CS_GenRegInfo (CodeSeg* S) */ Done = 0; RC_Invalidate (&Regs); + RC_InvalidatePS (&Regs); break; } if (J->RI->Out2.RegA != Regs.RegA) { @@ -1541,6 +1544,9 @@ void CS_GenRegInfo (CodeSeg* S) if (J->RI->Out2.Tmp1 != Regs.Tmp1) { Regs.Tmp1 = UNKNOWN_REGVAL; } + unsigned PF = J->RI->Out2.PFlags ^ Regs.PFlags; + Regs.PFlags |= ((PF >> 8) | PF | (PF << 8)) & UNKNOWN_PFVAL_ALL; + Regs.ZNRegs &= J->RI->Out2.ZNRegs; ++Entry; } diff --git a/src/cc65/coptsize.c b/src/cc65/coptsize.c index 5c23e637c..a5da4736d 100644 --- a/src/cc65/coptsize.c +++ b/src/cc65/coptsize.c @@ -76,730 +76,730 @@ static const CallDesc CallTable [] = { { "addeqysp", { - /* A X Y SRegLo */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "addeq0sp" },{ "laddeq", { - /* A X Y SRegLo */ - 1, 0, UNKNOWN_REGVAL, 0, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + 1, 0, UNKNOWN_REGVAL, 0, 0, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "laddeq1" },{ "laddeq", { - /* A X Y SRegLo */ - UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, 0, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, 0, 0, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "laddeqa" },{ "laddeqysp", { - /* A X Y SRegLo */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "laddeq0sp" },{ "ldaxidx", { - /* A X Y SRegLo */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, 1, UNKNOWN_REGVAL, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, 1, UNKNOWN_REGVAL, UNKNOWN_REGVAL, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "ldaxi" },{ "ldaxysp", { - /* A X Y SRegLo */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, 1, UNKNOWN_REGVAL, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, 1, UNKNOWN_REGVAL, UNKNOWN_REGVAL, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "ldax0sp" },{ "ldeaxidx", { - /* A X Y SRegLo */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, 3, UNKNOWN_REGVAL, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, 3, UNKNOWN_REGVAL, UNKNOWN_REGVAL, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "ldeaxi" },{ "ldeaxysp", { - /* A X Y SRegLo */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, 3, UNKNOWN_REGVAL, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, 3, UNKNOWN_REGVAL, UNKNOWN_REGVAL, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "ldeax0sp" },{ "leaaxsp", { - /* A X Y SRegLo */ - UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "leaa0sp" },{ "lsubeq", { - /* A X Y SRegLo */ - 1, 0, UNKNOWN_REGVAL, 0, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + 1, 0, UNKNOWN_REGVAL, 0, 0, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "lsubeq1" },{ "lsubeq", { - /* A X Y SRegLo */ - UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, 0, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, 0, 0, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "lsubeqa" },{ "lsubeqysp", { - /* A X Y SRegLo */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "lsubeq0sp" },{ "pusha", { - /* A X Y SRegLo */ - 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_SLOWER, "pushc0" },{ "pusha", { - /* A X Y SRegLo */ - 1, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + 1, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_SLOWER, "pushc1" },{ "pusha", { - /* A X Y SRegLo */ - 2, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + 2, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_SLOWER, "pushc2" },{ "pushax", { - /* A X Y SRegLo */ - 0, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + 0, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "push0" },{ "pushax", { - /* A X Y SRegLo */ - 1, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + 1, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_SLOWER, "push1" },{ "pushax", { - /* A X Y SRegLo */ - 2, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + 2, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_SLOWER, "push2" },{ "pushax", { - /* A X Y SRegLo */ - 3, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + 3, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_SLOWER, "push3" },{ "pushax", { - /* A X Y SRegLo */ - 4, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + 4, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_SLOWER, "push4" },{ "pushax", { - /* A X Y SRegLo */ - 5, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + 5, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_SLOWER, "push5" },{ "pushax", { - /* A X Y SRegLo */ - 6, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + 6, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_SLOWER, "push6" },{ "pushax", { - /* A X Y SRegLo */ - 7, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + 7, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_SLOWER, "push7" },{ "pushax", { - /* A X Y SRegLo */ - UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "pusha0" },{ "pushax", { - /* A X Y SRegLo */ - UNKNOWN_REGVAL, 0xFF, UNKNOWN_REGVAL, UNKNOWN_REGVAL, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + UNKNOWN_REGVAL, 0xFF, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_SLOWER, "pushaFF" },{ "pushaysp", { - /* A X Y SRegLo */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "pusha0sp" },{ "pusheax", { - /* A X Y SRegLo */ - 0, 0, UNKNOWN_REGVAL, 0, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + 0, 0, UNKNOWN_REGVAL, 0, 0, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "pushl0" },{ "pusheax", { - /* A X Y SRegLo */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0, 0, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "push0ax" },{ "pushwidx", { - /* A X Y SRegLo */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, 1, UNKNOWN_REGVAL, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, 1, UNKNOWN_REGVAL, UNKNOWN_REGVAL, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "pushw" },{ "pushwysp", { - /* A X Y SRegLo */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, 3, UNKNOWN_REGVAL, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, 3, UNKNOWN_REGVAL, UNKNOWN_REGVAL, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "pushw0sp" },{ "staxysp", { - /* A X Y SRegLo */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "stax0sp" },{ "steaxysp", { - /* A X Y SRegLo */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "steax0sp" },{ "subeqysp", { - /* A X Y SRegLo */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "subeq0sp" },{ "tosaddax", { - /* A X Y SRegLo */ - UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "tosadda0" },{ "tosaddeax", { - /* A X Y SRegLo */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0, 0, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "tosadd0ax" },{ "tosandax", { - /* A X Y SRegLo */ - UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "tosanda0" },{ "tosandeax", { - /* A X Y SRegLo */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0, 0, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "tosand0ax" },{ "tosdivax", { - /* A X Y SRegLo */ - UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "tosdiva0" },{ "tosdiveax", { - /* A X Y SRegLo */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0, 0, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "tosdiv0ax" },{ "toseqax", { - /* A X Y SRegLo */ - 0, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + 0, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "toseq00" },{ "toseqax", { - /* A X Y SRegLo */ - UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "toseqa0" },{ "tosgeax", { - /* A X Y SRegLo */ - 0, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + 0, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "tosge00" },{ "tosgeax", { - /* A X Y SRegLo */ - UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "tosgea0" },{ "tosgtax", { - /* A X Y SRegLo */ - 0, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + 0, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "tosgt00" },{ "tosgtax", { - /* A X Y SRegLo */ - UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "tosgta0" },{ "tosicmp", { - /* A X Y SRegLo */ - UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "tosicmp0" },{ "tosleax", { - /* A X Y SRegLo */ - 0, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + 0, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "tosle00" },{ "tosleax", { - /* A X Y SRegLo */ - UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "toslea0" },{ "tosltax", { - /* A X Y SRegLo */ - 0, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + 0, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "toslt00" },{ "tosltax", { - /* A X Y SRegLo */ - UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "toslta0" },{ "tosmodax", { - /* A X Y SRegLo */ - UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "tosmoda0" },{ "tosmodeax", { - /* A X Y SRegLo */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0, 0, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "tosmod0ax" },{ "tosmulax", { - /* A X Y SRegLo */ - UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "tosmula0" },{ "tosmuleax", { - /* A X Y SRegLo */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0, 0, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "tosmul0ax" },{ "tosneax", { - /* A X Y SRegLo */ - UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "tosnea0" },{ "tosorax", { - /* A X Y SRegLo */ - UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "tosora0" },{ "tosoreax", { - /* A X Y SRegLo */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0, 0, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "tosor0ax" },{ "tosrsubax", { - /* A X Y SRegLo */ - UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "tosrsuba0" },{ "tosrsubeax", { - /* A X Y SRegLo */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0, 0, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "tosrsub0ax" },{ "tossubax", { - /* A X Y SRegLo */ - UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "tossuba0" },{ "tossubeax", { - /* A X Y SRegLo */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0, 0, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "tossub0ax" },{ "tosudivax", { - /* A X Y SRegLo */ - UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "tosudiva0" },{ "tosudiveax", { - /* A X Y SRegLo */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0, 0, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "tosudiv0ax" },{ "tosugeax", { - /* A X Y SRegLo */ - UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "tosugea0" },{ "tosugtax", { - /* A X Y SRegLo */ - UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "tosugta0" },{ "tosuleax", { - /* A X Y SRegLo */ - UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "tosulea0" },{ "tosultax", { - /* A X Y SRegLo */ - UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "tosulta0" },{ "tosumodax", { - /* A X Y SRegLo */ - UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "tosumoda0" },{ "tosumodeax", { - /* A X Y SRegLo */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0, 0, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "tosumod0ax" },{ "tosumulax", { - /* A X Y SRegLo */ - UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "tosumula0" },{ "tosumuleax", { - /* A X Y SRegLo */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0, 0, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "tosumul0ax" },{ "tosxorax", { - /* A X Y SRegLo */ - UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "tosxora0" },{ "tosxoreax", { - /* A X Y SRegLo */ - UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0, - /* SRegHi Ptr1Lo Ptr1Hi Tmp1 */ - 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL + /* A X Y SRegLo SRegHi */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0, 0, + /* Ptr1Lo Ptr1Hi Tmp1 PFlags ZNRegs */ + UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_PFVAL_ALL, ZNREG_NONE }, F_NONE, "tosxor0ax" diff --git a/src/cc65/coptstop.c b/src/cc65/coptstop.c index 34a9b88d6..c31b0ec97 100644 --- a/src/cc65/coptstop.c +++ b/src/cc65/coptstop.c @@ -320,10 +320,10 @@ static void AdjustLoadInfo (LoadInfo* LI, int Index, int Change) static int Affected (LoadRegInfo* RI, const CodeEntry* E) /* Check if the load src may be modified between the pushax and op */ { - fncls_t fncls; - unsigned short Use; - unsigned short Chg; - unsigned short UseToCheck = 0; + fncls_t fncls; + unsigned int Use; + unsigned int Chg; + unsigned int UseToCheck = 0; if ((RI->Flags & (LI_CHECK_ARG | LI_CHECK_Y)) != 0) { if (E->AM == AM65_IMM || E->AM == AM65_ACC || E->AM == AM65_IMP || E->AM == AM65_BRA) { diff --git a/src/cc65/reginfo.c b/src/cc65/reginfo.c index 383c6ec24..601f0f688 100644 --- a/src/cc65/reginfo.c +++ b/src/cc65/reginfo.c @@ -74,6 +74,15 @@ void RC_InvalidateZP (RegContents* C) +void RC_InvalidatePS (RegContents* C) +/* Invalidate processor status */ +{ + C->PFlags = UNKNOWN_PFVAL_ALL; + C->ZNRegs = ZNREG_NONE; +} + + + static void RC_Dump1 (FILE* F, const char* Desc, short Val) /* Dump one register value */ { @@ -102,6 +111,44 @@ void RC_Dump (FILE* F, const RegContents* RC) +#if !defined(HAVE_INLINE) +int PStatesAreKnown (unsigned short PFlags, unsigned WhatStates) +/* Return true if all queried processor states are known. +** Note: WhatStates takes PSTATE_* rather than PFVAL_*. +*/ +{ + return ((PFlags << (PSTATE_BITS_SHIFT - 8)) & WhatStates & PSTATE_BITS_MASK) == 0; +} +#endif + + + +#if !defined(HAVE_INLINE) +int PStatesAreSet (unsigned short PFlags, unsigned WhatStates) +/* Return true if all queried processor states are known to be set. +** Note: WhatStates takes PSTATE_* rather than PFVAL_*. +*/ +{ + return (PFlags & (WhatStates >> (PSTATE_BITS_SHIFT - 8))) == 0 && + (PFlags & (WhatStates >> PSTATE_BITS_SHIFT)) == WhatStates >> PSTATE_BITS_SHIFT; +} +#endif + + + +#if !defined(HAVE_INLINE) +int PStatesAreClear (unsigned short PFlags, unsigned WhatStates) +/* Return true if all queried processor states are known to be cleared. +** Note: WhatStates takes PSTATE_* rather than PFVAL_*. +*/ +{ + return (PFlags & (WhatStates >> (PSTATE_BITS_SHIFT - 8))) == 0 && + (PFlags & (WhatStates >> PSTATE_BITS_SHIFT)) == 0; +} +#endif + + + RegInfo* NewRegInfo (const RegContents* RC) /* Allocate a new register info, initialize and return it. If RC is not ** a NULL pointer, it is used to initialize both, the input and output @@ -120,6 +167,9 @@ RegInfo* NewRegInfo (const RegContents* RC) RC_Invalidate (&RI->In); RC_Invalidate (&RI->Out); RC_Invalidate (&RI->Out2); + RC_InvalidatePS (&RI->In); + RC_InvalidatePS (&RI->Out); + RC_InvalidatePS (&RI->Out2); } /* Return the new struct */ diff --git a/src/cc65/reginfo.h b/src/cc65/reginfo.h index 7354c301f..28b948e04 100644 --- a/src/cc65/reginfo.h +++ b/src/cc65/reginfo.h @@ -54,6 +54,69 @@ /* Encoding for an unknown register value */ #define UNKNOWN_REGVAL -1 +/* Encoding for an unknown processor status: +** For Bit N in the flags, ((flags >> N) & 0x0101) == 0x0101 means 'unknown' +*/ +#define UNKNOWN_PFVAL_C 0x0101U /* Carray */ +#define UNKNOWN_PFVAL_Z 0x0202U /* Zero */ +#define UNKNOWN_PFVAL_I 0x0404U /* Interrupt */ +#define UNKNOWN_PFVAL_D 0x0808U /* Decimal */ +#define UNKNOWN_PFVAL_U 0x1010U /* Unused */ +#define UNKNOWN_PFVAL_B 0x2020U /* Break */ +#define UNKNOWN_PFVAL_V 0x4040U /* Overflow */ +#define UNKNOWN_PFVAL_N 0x8080U /* Negative */ +#define UNKNOWN_PFVAL_CZ (UNKNOWN_PFVAL_C | UNKNOWN_PFVAL_Z) +#define UNKNOWN_PFVAL_CZN (UNKNOWN_PFVAL_N | UNKNOWN_PFVAL_CZ) +#define UNKNOWN_PFVAL_CZVN (UNKNOWN_PFVAL_V | UNKNOWN_PFVAL_CZN) +#define UNKNOWN_PFVAL_ZN (UNKNOWN_PFVAL_Z | UNKNOWN_PFVAL_N) +#define UNKNOWN_PFVAL_ZVN (UNKNOWN_PFVAL_V | UNKNOWN_PFVAL_ZN) +#define UNKNOWN_PFVAL_6502 0xE7E7U +#define UNKNOWN_PFVAL_ALL 0xFFFFU + +/* Encoding for a known processor status */ +#define PFVAL_C 0x0001U /* Carray set */ +#define PFVAL_Z 0x0002U /* Zero set */ +#define PFVAL_I 0x0004U /* Interrupt set */ +#define PFVAL_D 0x0008U /* Decimal set */ +#define PFVAL_U 0x0010U /* Unused set */ +#define PFVAL_B 0x0020U /* Break set */ +#define PFVAL_V 0x0040U /* Overflow set */ +#define PFVAL_N 0x0080U /* Negative set */ +#define PFVAL_CZ (PFVAL_C | PFVAL_Z) +#define PFVAL_CZN (PFVAL_N | PFVAL_CZ) +#define PFVAL_CZVN (PFVAL_V | PFVAL_CZN) +#define PFVAL_ZN (PFVAL_Z | PFVAL_N) +#define PFVAL_ZVN (PFVAL_V | PFVAL_ZN) +#define PFVAL_6502 0x00E7U +#define PFVAL_ALL 0x00FFU + +/* Used for functions to convert the processor states to processor flags */ +#define PSTATE_BITS_SHIFT 24 +#define PSTATE_BITS_MASK (0xFFU << PSTATE_BITS_SHIFT) + +/* Encoding for unknown Z/N status origin */ +#define UNKNOWN_ZNREG 0x0000U + +/* Encoding for known register Z/N status origins */ +#define ZNREG_NONE 0x0000U /* None */ +#define ZNREG_A REG_A +#define ZNREG_X REG_X +#define ZNREG_Y REG_Y +#define ZNREG_TMP1 REG_TMP1 +#define ZNREG_PTR1_LO REG_PTR1_LO +#define ZNREG_PTR1_HI REG_PTR1_HI +#define ZNREG_PTR2_LO REG_PTR2_LO +#define ZNREG_PTR2_HI REG_PTR2_HI +#define ZNREG_SREG_LO REG_SREG_LO +#define ZNREG_SREG_HI REG_SREG_HI +#define ZNREG_SAVE_LO REG_SAVE_LO +#define ZNREG_SAVE_HI REG_SAVE_HI +#define ZNREG_AX (REG_A | REG_X) +#define ZNREG_AY (REG_A | REG_Y) +#define ZNREG_AXY (REG_A | REG_X | REG_Y) + + + /* Register contents */ typedef struct RegContents RegContents; struct RegContents { @@ -65,6 +128,8 @@ struct RegContents { short Ptr1Lo; short Ptr1Hi; short Tmp1; + unsigned short PFlags; /* Processor flags */ + unsigned short ZNRegs; /* Which register(s) the Z/N flags reflect */ }; /* Register change info */ @@ -89,6 +154,9 @@ void RC_Invalidate (RegContents* C); void RC_InvalidateZP (RegContents* C); /* Invalidate all ZP registers */ +void RC_InvalidatePS (RegContents* C); +/* Invalidate processor status */ + void RC_Dump (FILE* F, const RegContents* RC); /* Dump the contents of the given RegContents struct */ @@ -112,6 +180,56 @@ INLINE int RegValIsUnknown (short Val) # define RegValIsUnknown(S) ((S) < 0) #endif +#if defined(HAVE_INLINE) +INLINE int PStatesAreKnown (unsigned short PFlags, unsigned WhatStates) +/* Return true if all queried processor states are known. +** Note: WhatStates takes PSTATE_* rather than PFVAL_*. +*/ +{ + return ((PFlags << (PSTATE_BITS_SHIFT - 8)) & WhatStates & PSTATE_BITS_MASK) == 0; +} +#else +int PStatesAreKnown (unsigned short PFlags, unsigned WhatStates); +#endif + +#if defined(HAVE_INLINE) +INLINE int PStatesAreUnknown (unsigned short PFlags, unsigned WhatStates) +/* Return true if any queried processor states are unknown. +** Note: WhatStates takes PSTATE_* rather than PFVAL_*. +*/ +{ + return !PStatesAreKnown (PFlags, WhatStates); +} +#else +# define PStatesAreUnknown(V, B) (!PStatesAreKnown (V, B)) +#endif + +#if defined(HAVE_INLINE) +INLINE int PStatesAreSet (unsigned short PFlags, unsigned WhatStates) +/* Return true if all queried processor states are known to be set. +** Note: WhatStates takes PSTATE_* rather than PFVAL_*. +*/ +{ + return (PFlags & (WhatStates >> (PSTATE_BITS_SHIFT - 8))) == 0 && + (PFlags & (WhatStates >> PSTATE_BITS_SHIFT)) == WhatStates >> PSTATE_BITS_SHIFT; +} +#else +int PStatesAreSet (unsigned short PFlags, unsigned WhatStates); +#endif + +#if defined(HAVE_INLINE) +INLINE int PStatesAreClear (unsigned short PFlags, unsigned WhatStates) +/* Return true if the queried processor states are known to be cleared. +** Note: WhatStates takes PSTATE_* rather than PFVAL_*. +*/ +{ + return (PFlags & (WhatStates >> (PSTATE_BITS_SHIFT - 8))) == 0 && + (PFlags & (WhatStates >> PSTATE_BITS_SHIFT)) == 0; +} +#else +int PStatesAreClear (unsigned short PFlags, unsigned WhatStates); +#endif + RegInfo* NewRegInfo (const RegContents* RC); /* Allocate a new register info, initialize and return it. If RC is not ** a NULL pointer, it is used to initialize both, the input and output