From 76c8f0d860f2ab56ca85049bcaa7864f8775ff07 Mon Sep 17 00:00:00 2001
From: mrdudz <mrdudz@users.noreply.github.com>
Date: Sat, 21 Jun 2025 01:39:33 +0200
Subject: [PATCH] fix test, add 45GS02 instructions

---
 test/asm/cpudetect/45GS02-cpudetect.ref | Bin 0 -> 80 bytes
 test/asm/cpudetect/allinst.inc          |  91 ++++++++++++++++++++++--
 test/asm/cpudetect/cpudetect.s          |   9 +++
 3 files changed, 96 insertions(+), 4 deletions(-)
 create mode 100644 test/asm/cpudetect/45GS02-cpudetect.ref

diff --git a/test/asm/cpudetect/45GS02-cpudetect.ref b/test/asm/cpudetect/45GS02-cpudetect.ref
new file mode 100644
index 0000000000000000000000000000000000000000..e9aa843cda2fb487e49b4380205f4b31d1ffb805
GIT binary patch
literal 80
tcmZ>A;x!Rsa1IEK_Y8Ioi8nJfFhb@9JEQVZxF)8C1_;F_rtZN8MgT636pjD@

literal 0
HcmV?d00001

diff --git a/test/asm/cpudetect/allinst.inc b/test/asm/cpudetect/allinst.inc
index ab266915e..e58577b7e 100644
--- a/test/asm/cpudetect/allinst.inc
+++ b/test/asm/cpudetect/allinst.inc
@@ -636,7 +636,7 @@ LABEL3:
 .endif
 
 
-; The 4502 is a superset of the 65CE02. Opcode 5c (originally a "4-byte NOP
+; The 4510 is a superset of the 65CE02. Opcode 5c (originally a "4-byte NOP
 ; reserved for future expansion") has been changed to the "map" instruction,
 ; now using implied addressing.
 ;
@@ -656,9 +656,92 @@ LABEL3:
 .endif
 
 
-; TODO: MEGA65
-; The m65 instruction set extends the 4502 instruction set using prefix bytes.
-; Therefore, the "normal" opcode table is the same as for the 4502 cpu
+; The 45GS02 instruction set extends the 4510 instruction set using prefix bytes.
+; Therefore, the "normal" opcode table is the same as for the 4510 cpu
+
+.if (.cpu .bitand CPU_ISET_45GS02)
+    .scope
+
+    orq $12          ; $42 $42 $05
+    aslq $12         ; $42 $42 $06
+    aslq             ; $42 $42 $0a
+    orq $1234        ; $42 $42 $0d
+    aslq $1234       ; $42 $42 $0f
+    orq ($12)        ; $42 $42 $12
+    aslq $12,x       ; $42 $42 $16
+    inq              ; $42 $42 $1a
+    aslq $124,x      ; $42 $42 $1e
+    bitq $12         ; $42 $42 $24
+    andq $12         ; $42 $42 $25
+    rolq $12         ; $42 $42 $26
+    rolq             ; $42 $42 $2a
+    bitq $1234       ; $42 $42 $2c
+    andq $1234       ; $42 $42 $2d
+    rolq $1234       ; $42 $42 $2e
+    andq ($12)       ; $42 $42 $32
+    rolq $12, x      ; $42 $42 $36
+    deq              ; $42 $42 $3a
+    rolq $1234, x    ; $42 $42 $3e
+    asrq             ; $42 $42 $43
+    asrq $12         ; $42 $42 $44
+    eorq $12         ; $42 $42 $45
+    lsrq $12         ; $42 $42 $46
+    lsrq             ; $42 $42 $4a
+    eorq $1234       ; $42 $42 $4d
+    lsrq $1234       ; $42 $42 $4e
+    eorq ($12)       ; $42 $42 $52
+    asrq $12, x      ; $42 $42 $54
+    lsrq $12, x      ; $42 $42 $56
+    lsrq $1234, x    ; $42 $42 $5e
+    adcq $12         ; $42 $42 $65
+    rorq $12         ; $42 $42 $66
+    rorq             ; $42 $42 $6a
+    adcq $1234       ; $42 $42 $6d
+    rorq $1234       ; $42 $42 $6e
+    adcq ($12)       ; $42 $42 $72
+    rorq $12, x      ; $42 $42 $76
+    rorq $1234, x    ; $42 $42 $7e
+    stq $12          ; $42 $42 $85
+    stq $1234        ; $42 $42 $8d
+    stq ($12)        ; $42 $42 $92
+    ldq $12          ; $42 $42 $a5
+    ldq $1234        ; $42 $42 $ad
+    ldq ($12), z     ; $42 $42 $b2
+    cmpq $12         ; $42 $42 $c5
+    deq $12          ; $42 $42 $c6
+    cmpq $1234       ; $42 $42 $cd
+    deq $1234        ; $42 $42 $ce
+    cmpq ($12)       ; $42 $42 $d2
+    deq $12, x       ; $42 $42 $d6
+    deq $1234, x     ; $42 $42 $de
+    sbcq $12         ; $42 $42 $e5
+    inq $12          ; $42 $42 $e6
+    sbcq $1234       ; $42 $42 $ed
+    inq $1234        ; $42 $42 $ee
+    sbcq ($12)       ; $42 $42 $f2
+    inq $12, x       ; $42 $42 $f6
+    inq $1234, x     ; $42 $42 $fe
+
+    ora [$12], z     ; $ea $12
+    and [$12], z     ; $ea $32
+    eor [$12], z     ; $ea $52
+    adc [$12], z     ; $ea $72
+    sta [$12], z     ; $ea $92
+    lda [$12], z     ; $ea $b2
+    cmp [$12], z     ; $ea $d2
+    sbc [$12], z     ; $ea $f2
+
+    orq [$12]        ; $42 $42 $ea $12
+    andq [$12]       ; $42 $42 $ea $32
+    eorq [$12]       ; $42 $42 $ea $52
+    adcq [$12]       ; $42 $42 $ea $72
+    stq [$12]        ; $42 $42 $ea $92
+    ldq [$12], z     ; $42 $42 $ea $b2
+    cmpq [$12]       ; $42 $42 $ea $d2
+    sbcq [$12]       ; $42 $42 $ea $f2
+
+    .endscope
+.endif
 
 
 ; The HUC6280 is a superset of the R65C02. It adds some other instructions:
diff --git a/test/asm/cpudetect/cpudetect.s b/test/asm/cpudetect/cpudetect.s
index a017e652d..545e2fa56 100644
--- a/test/asm/cpudetect/cpudetect.s
+++ b/test/asm/cpudetect/cpudetect.s
@@ -28,6 +28,10 @@
    taz
 .endif
 
+.ifp45GS02
+   orq $1234
+.endif
+
 .ifpdtv
    sac #$00
 .endif
@@ -76,6 +80,10 @@
    .byte 0,"CPU_ISET_4510"
 .endif
 
+.if (.cpu .bitand CPU_ISET_45GS02)
+   .byte 0,"CPU_ISET_45GS02"
+.endif
+
 .if (.cpu .bitand CPU_ISET_6502DTV)
    .byte 0,"CPU_ISET_6502DTV"
 .endif
@@ -98,5 +106,6 @@
 .pc02
 .p816
 .p4510
+.p45GS02
 .pdtv
 .pm740