From 91c9e32e4be6af83d387bf39fa39c754d8d9fa8a Mon Sep 17 00:00:00 2001
From: mrdudz <mrdudz@users.noreply.github.com>
Date: Sun, 29 Jun 2025 19:14:28 +0200
Subject: [PATCH] add sweet16 to the cpudetect test

---
 test/asm/cpudetect/allinst.inc           |  37 +++++++++++++++++++++++
 test/asm/cpudetect/cpudetect.s           |   6 +++-
 test/asm/cpudetect/sweet16-cpudetect.ref | Bin 0 -> 18 bytes
 3 files changed, 42 insertions(+), 1 deletion(-)
 create mode 100644 test/asm/cpudetect/sweet16-cpudetect.ref

diff --git a/test/asm/cpudetect/allinst.inc b/test/asm/cpudetect/allinst.inc
index d604c36b9..2ba44ff83 100644
--- a/test/asm/cpudetect/allinst.inc
+++ b/test/asm/cpudetect/allinst.inc
@@ -970,3 +970,40 @@ LABEL:
     .endscope
 
 .endif
+
+.if (.cpu .bitand CPU_ISET_SWEET16)
+
+    RTN                 ; $00      Return to 6502 code.
+    BR   LABEL          ; $01 ea   Unconditional Branch.
+    BNC  LABEL          ; $02 ea   Branch if Carry=0.
+    BC   LABEL          ; $03 ea   Branch if Carry=1.
+    BP   LABEL          ; $04 ea   Branch if last result positive.
+    BM   LABEL          ; $0S ea   Branch if last result negative.
+    BZ   LABEL          ; $06 ea   Branch if last result zero.
+    BNZ  LABEL          ; $07 ea   Branch if last result non-zero.
+    BM1  LABEL          ; $08 ea   Branch if last result = -1.
+    BNM1 LABEL          ; $09 ea   Branch if last result not -1.
+    BK                  ; $0A      Execute 6502 BRK instruction.
+    RS                  ; $0B      Return from SWEET-16 subroutine.
+    BS   LABEL          ; $0C ea   Call SWEET-16 subroutine.
+LABEL:
+
+.repeat 16, count
+    SET  count,$1234    ; $1n lo hi  Rn <-- value.
+    LD   count          ; $2n        R0 <-- (Rn).
+    ST   count          ; $3n        Rn <-- (R0).
+    LD   @count         ; $4n        MA = (Rn), ROL <-- (MA), Rn <-- MA+1, R0H <-- 0.
+    ST   @count         ; $5n        MA = (Rn), MA <-- (R0L), Rn <-- MA+1.
+    LDD  @count         ; $6n        MA = (Rn), R0 <-- (MA, MA+1), Rn <-- MA+2.
+    STD  @count         ; $7n        MA = (Rn), MA,MA+l <-- (R0), Rn <-- MA+2.
+    POP  @count         ; $8n        MA = (Rn)-1, R0L <-- (MA), R0H <-- 0, Rn <-- MA.
+    STP  @count         ; $9n        MA <-- (Rn)-1, (MA) <-- R0L, Rn <-- MA.
+    ADD  count          ; $An        R0 <-- (R0) + (Rn).
+    SUB  count          ; $Bn        R0 <-- (R0) - (Rn).
+    POPD @count         ; $Cn        MA = (Rn)-2, MA,MA+l <-- R0, Rn <-- MA.
+    CPR  count          ; $Dn        R13 <-- (R0) - (Rn), R14 <-- status flags.
+    INR  count          ; $En        Rn <-- (Rn) + 1.
+    DCR  count          ; $Fn        Rn <-- (Rn) - 1.
+.endrepeat
+
+.endif
diff --git a/test/asm/cpudetect/cpudetect.s b/test/asm/cpudetect/cpudetect.s
index 414afe68d..3022038a2 100644
--- a/test/asm/cpudetect/cpudetect.s
+++ b/test/asm/cpudetect/cpudetect.s
@@ -54,6 +54,10 @@
    xba
 .endif
 
+.ifpsweet16
+   bk
+.endif
+
 
 ; step 2: check for bitwise compatibility of instructions sets
 ;         (made verbose for better reading with hexdump/hd(1))
@@ -132,4 +136,4 @@
 .p6280
 .pm740
 .p816
-; FIXME: sweet16
+.psweet16
diff --git a/test/asm/cpudetect/sweet16-cpudetect.ref b/test/asm/cpudetect/sweet16-cpudetect.ref
new file mode 100644
index 0000000000000000000000000000000000000000..98d33127aeb50b9577095ed14649ddac5ad0a2d4
GIT binary patch
literal 18
Zcmd;La1IEK_Y8Ioi4P8Ubqz5z0{|-u1l0fl

literal 0
HcmV?d00001