From b04d79b1da2bc5b79c4ff78b6819ee0924376ec2 Mon Sep 17 00:00:00 2001 From: Carlo Bramini Date: Thu, 4 Jan 2024 13:12:52 +0100 Subject: [PATCH 01/21] [SIM65] Support undocumented opcodes for 6502 This PR is mostly a complete rewrite of the emulator for 6502/65c02 opcodes. It provides an easier to maintain implementation of the instructions, by using few macros rather than having hand-written code for each function. All undocumented, previously missing opcodes for 6502 are also implemented. The patch also includes a detailed documentation of those opcodes, for reference to developers. This PR should fix one of the milestones listed here for the next version of CC65: https://github.com/cc65/wiki/wiki/Before-the-next-release --- asminc/cpu.mac | 2 +- libsrc/sim6502/exehdr.s | 12 +- src/sim65/6502.c | 2703 ++++++++++++++++++++++++++------------- src/sim65/6502.h | 3 +- src/sim65/main.c | 10 +- 5 files changed, 1805 insertions(+), 925 deletions(-) diff --git a/asminc/cpu.mac b/asminc/cpu.mac index 31170fbed..084a42119 100644 --- a/asminc/cpu.mac +++ b/asminc/cpu.mac @@ -15,7 +15,7 @@ CPU_ISET_4510 = $0400 CPU_NONE = CPU_ISET_NONE CPU_6502 = CPU_ISET_6502 CPU_6502X = CPU_ISET_6502|CPU_ISET_6502X -CPU_6502DTV = CPU_ISET_6502|CPU_ISET_6502X|CPU_ISET_6502DTV +CPU_6502DTV = CPU_ISET_6502|CPU_ISET_6502DTV CPU_65SC02 = CPU_ISET_6502|CPU_ISET_65SC02 CPU_65C02 = CPU_ISET_6502|CPU_ISET_65SC02|CPU_ISET_65C02 CPU_65816 = CPU_ISET_6502|CPU_ISET_65SC02|CPU_ISET_65816 diff --git a/libsrc/sim6502/exehdr.s b/libsrc/sim6502/exehdr.s index 09d099da5..529ad9b94 100644 --- a/libsrc/sim6502/exehdr.s +++ b/libsrc/sim6502/exehdr.s @@ -9,11 +9,21 @@ .import __MAIN_START__ .import startup + .macpack cpu + .segment "EXEHDR" .byte $73, $69, $6D, $36, $35 ; 'sim65' .byte 2 ; header version - .byte .defined(__SIM65C02__) ; CPU type +.if (.cpu .bitand ::CPU_ISET_6502X) + .byte 2 +.elseif (.cpu .bitand ::CPU_ISET_65C02) + .byte 1 +.elseif (.cpu .bitand ::CPU_ISET_6502) + .byte 0 +.else + .error Unknow CPU type. +.endif .byte sp ; sp address .addr __MAIN_START__ ; load address .addr startup ; reset address diff --git a/src/sim65/6502.c b/src/sim65/6502.c index 9d2c93da8..448e81669 100644 --- a/src/sim65/6502.c +++ b/src/sim65/6502.c @@ -12,6 +12,8 @@ /* EMail: uz@cc65.org */ /* */ /* Mar-2017, Christian Krueger, added support for 65SC02 */ +/* Dec-2023, Carlo Bramini, rewritten for better maintenance and added */ +/* support for undocumented opcodes for 6502 */ /* */ /* This software is provided 'as-is', without any expressed or implied */ /* warranty. In no event will the authors be held liable for any damages */ @@ -44,7 +46,337 @@ #include "6502.h" #include "paravirt.h" +/* + 6502 opcode map: + + x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE xF +0x BRK ORA --- SLO NOP ORA ASL SLO PHP ORA ASL ANC NOP ORA ASL SLO + inx inx zp zp zp zp imm acc imm abs abs abs abs + +1x BPL ORA --- SLO NOP ORA ASL SLO CLC ORA NOP SLO NOP ORA ASL SLO + rel iny iny zpx zpx zpx zpy aby aby abx abx abx abx + +2x JSR AND --- RLA BIT AND ROL RLA PLP AND ROL ANC BIT AND ROL RLA + abs inx inx zp zp zp zp imm acc imm abs abs abs abs + +3x BMI AND --- RLA NOP AND ROL RLA SEC AND NOP RLA NOP AND ROL RLA + rel iny iny zpx zpx zpx zpy aby aby abx abx abx abx + +4x RTI EOR --- SRE NOP EOR LSR SRE PHA EOR LSR ASR JMP EOR LSR SRE + inx inx zp zp zp zp imm acc imm abs abs abs abs + +5x BVC EOR --- SRE NOP EOR LSR SRE CLI EOR NOP SRE NOP EOR LSR SRE + rel iny iny zpx zpx zpx zpx aby aby abx abx abx abx + +6x RTS ADC --- RRA NOP ADC ROR RRA PLA ADC ROR ARR JMP ADC ROR RRA + inx inx zp zp zp zp imm acc imm ind abs abs abs + +7x BVS ADC --- RRA NOP ADC ROR RRA SEI ADC NOP RRA NOP ADC ROR RRA + rel iny iny zpx zpx zpx zpx aby aby abx abx abx abx + +8x NOP STA NOP SAX STY STA STX SAX DEY NOP TXA ANE STY STA STX SAX + imm inx imm inx zp zp zp zp imm imm abs abs abs abs + +9x BCC STA --- SHA STY STA STX SAX TYA STA TXS TAS SHY STA SHX SHA + rel iny iny zpx zpx zpy zpy aby aby abx abx aby aby + +Ax LDY LDA LDX LAX LDY LDA LDX LAX TAY LDA TAX LXA LDY LDA LDX LAX + imm inx imm inx zp zp zp zp imm imm abs abs abs abs + +Bx BCS LDA --- LAX LDY LDA LDX LAX CLV LDA TSX LAS LDY LDA LDX LAX + rel iny iny zpx zpx zpy zpy aby aby abx abx aby aby + +Cx CPY CMP NOP DCP CPY CMP DEC DCP INY CMP DEX SBX CPY CMP DEC DCP + imm inx imm inx zp zp zp zp imm imm abs abs abs abs + +Dx BNE CMP --- DCP NOP CMP DEC DCP CLD CMP NOP DCP NOP CMP DEC DCP + rel iny iny zpx zpx zpx zpx aby zpx aby abx abx abx abx + +Ex CPX SBC NOP ISC CPX SBC INC ISC INX SBC NOP SBC CPX SBC INC ISC + imm inx imm inx zp zp zp zp imm imm abs abs abs abs + +Fx BEQ SBC --- ISC NOP SBC INC ISC SED SBC NOP ISC NOP SBC INC ISC + rel iny iny zpx zpx zpx zpx aby zpx aby abx abx abx abx + +--- = CPU JAM/HALT + +*/ + +/* + +65xx ILLEGAL INSTRUCTIONS + + +* SLO: shift left the contents of a memory location and then OR the result with + the accumulator. + +Address mode | opcode | cycles | N V B D I Z C +-------------+--------+--------+ FLAGS: X . . . . X X +SLO abs | 0Fh | 6 | +SLO abs,X | 1Fh | 7 | +SLO abs,Y | 1Bh | 7 | +SLO zp | 07h | 5 | +SLO zp,X | 17h | 6 | +SLO (zp,X) | 03h | 8 | +SLO (zp),Y | 13h | 8 | +-------------+--------+--------+ + + +* RLA: rotate left the contents of a memory location and then AND the result with + the accumulator. + +Address mode | opcode | cycles | N V B D I Z C +-------------+--------+--------+ FLAGS: X . . . . X X +RLA abs | 2Fh | 6 | +RLA abs,X | 3Fh | 7 | +RLA abs,Y | 3Bh | 7 | +RLA zp | 27h | 5 | +RLA zp,X | 37h | 6 | +RLA (zp,X) | 23h | 8 | +RLA (zp),Y | 33h | 8 | +-------------+--------+--------+ + + +* SRE: shift right the contents of a memory location and then X-OR the result + with the accumulator. + +Address mode | opcode | cycles | N V B D I Z C +-------------+--------+--------+ FLAGS: X . . . . X X +SRE abs | 4Fh | 6 | +SRE abs,X | 5Fh | 7 | +SRE abs,Y | 5Bh | 7 | +SRE zp | 47h | 5 | +SRE zp,X | 57h | 6 | +SRE (zp,X) | 43h | 8 | +SRE (zp),Y | 53h | 8 | +-------------+--------+--------+ + + +* RRA: rotate right the contents of a memory location and then adds with carry + the result with the accumulator. + +Address mode | opcode | cycles | N V B D I Z C +-------------+--------+--------+ FLAGS: X X . . . X X +RRA abs | 6Fh | 6 | +RRA abs,X | 7Fh | 7 | +RRA abs,Y | 7Bh | 7 | +RRA zp | 67h | 5 | +RRA zp,X | 77h | 6 | +RRA (zp,X) | 63h | 8 | +RRA (zp),Y | 73h | 8 | +-------------+--------+--------+ + + +* SAX: calculate AND between the A and X registers (without changing the + contents of the registers) and stores the result in memory. + Flags into P register are not modified. + +Address mode | opcode | cycles | N V B D I Z C +-------------+--------+--------+ FLAGS: . . . . . . . +SAX abs | 8Fh | 4 | +SAX zp | 87h | 3 | +SAX zp,Y | 97h | 4 | +SAX (zp,X) | 83h | 6 | +-------------+--------+--------+ + + +* LAX: loads both the accumulator and the X register with the content of a memory + location. + +Address mode | opcode | cycles | N V B D I Z C +-------------+--------+--------+ FLAGS: X . . . . X . +LAX abs | AFh | 4 | +LAX abs,Y | BFh | 4* | * = adds +1 if page cross is detected. +LAX zp | A7h | 3 | +LAX zp,Y | B7h | 4 | +LAX (zp,X) | A3h | 6 | +LAX (zp),Y | B3h | 5* | +-------------+--------+--------+ + + +* DCP: decrements the contents of a memory location and then compares the result + with the accumulator. + +Address mode | opcode | cycles | N V B D I Z C +-------------+--------+--------+ FLAGS: X . . . . X X +DCP abs | CFh | 6 | +DCP abs,X | DFh | 7 | +DCP abs,Y | DBh | 7 | +DCP zp | C7h | 5 | +DCP zp,X | D7h | 6 | +DCP (zp,X) | C3h | 8 | +DCP (zp),Y | D3h | 8 | +-------------+--------+--------+ + + +* ISC: increments the contents of a memory location and then subtract with carry + the result from the accumulator. + +Address mode | opcode | cycles | N V B D I Z C +-------------+--------+--------+ FLAGS: X X . . . X X +ISC abs | EFh | 6 | +ISC abs,X | FFh | 7 | +ISC abs,Y | FBh | 7 | +ISC zp | E7h | 5 | +ISC zp,X | F7h | 6 | +ISC (zp,X) | E3h | 8 | +ISC (zp),Y | F3h | 8 | +-------------+--------+--------+ + + +* ASR: calculates the AND between the accumulator and an immediate value and then + shift right the result. + +Address mode | opcode | cycles | N V B D I Z C +-------------+--------+--------+ FLAGS: X . . . . X X +ASR #imm | 4Bh | 2 | +-------------+--------+--------+ + + +* ARR: calculates the AND between the accumulator and an immediate value and then + rotate right the result. + +Address mode | opcode | cycles | N V B D I Z C +-------------+--------+--------+ FLAGS: X . . . . X X +ARR #imm | 6Bh | 2 | +-------------+--------+--------+ + + +* ANE: calculates the OR of the accumulator with an unstable constant, then it does + an AND with the X register and an immediate value. + The unstable constant varies with temperature, the production batch and + maybe other factors. Experimental measures assume its value to 0xEF. + +Address mode | opcode | cycles | N V B D I Z C +-------------+--------+--------+ FLAGS: X . . . . X . +ANE #imm | 8Bh | 2 | +-------------+--------+--------+ + + +* LXA: calculates the OR of the accumulator with an unstable constant, then it does + an AND with an immediate value. The result is copied into the X register and + the accumulator. + The unstable constant varies with temperature, the production batch and + maybe other factors. Experimental measures assume its value to 0xEE. + +Address mode | opcode | cycles | N V B D I Z C +-------------+--------+--------+ FLAGS: X . . . . X . +LXA #imm | ABh | 2 | +-------------+--------+--------+ + + +* SBX: calculates the AND of the accumulator with the X register and the subtracts + an immediate value. + +Address mode | opcode | cycles | N V B D I Z C +-------------+--------+--------+ FLAGS: X . . . . X X +SBX #imm | CBh | 2 | +-------------+--------+--------+ + + +* NOP: No-Operation. + +Address mode | opcode | cycles | N V B D I Z C +-------------+--------+--------+ FLAGS: . . . . . . . +NOP | 1Ah | 2 | +NOP | 3Ah | 2 | * = adds +1 if page cross is detected. +NOP | 5Ah | 2 | +NOP | 7Ah | 2 | +NOP | DAh | 2 | +NOP | FAh | 2 | +NOP #imm | 80h | 2 | +NOP #imm | 82h | 2 | +NOP #imm | 89h | 2 | +NOP #imm | C2h | 2 | +NOP #imm | E2h | 2 | +NOP zp | 04h | 3 | +NOP zp,x | 14h | 4 | +NOP zp,x | 34h | 4 | +NOP zp | 44h | 3 | +NOP zp,x | 54h | 4 | +NOP zp | 64h | 3 | +NOP zp,x | 74h | 4 | +NOP zp,x | D4h | 4 | +NOP zp,x | F4h | 4 | +NOP abs | 0Ch | 4 | +NOP abs,x | 1Ch | 4* | +NOP abs,x | 3Ch | 4* | +NOP abs,x | 5Ch | 4* | +NOP abs,x | 7Ch | 4* | +NOP abs,x | DCh | 4* | +NOP abs,x | FCh | 4* | +-------------+--------+--------+ + + +* TAS: calculates the AND of the accumulator with the X register and stores the result + into the stack pointer. Then, it calculates the AND of the result with the + high byte of the memory pointer plus 1 and it stores the final result in memory. + +Address mode | opcode | cycles | N V B D I Z C +-------------+--------+--------+ FLAGS: . . . . . . . +TAS abs,y | 9Bh | 5 | +-------------+--------+--------+ + + +* SHY: calculates the AND of the Y register with the high byte of the memory pointer + plus 1 and it stores the final result in memory. + +Address mode | opcode | cycles | N V B D I Z C +-------------+--------+--------+ FLAGS: . . . . . . . +SHY abs,x | 9Ch | 5 | +-------------+--------+--------+ + + +* SHX: calculates the AND of the X register with the high byte of the memory pointer + plus 1 and it stores the final result in memory. + +Address mode | opcode | cycles | N V B D I Z C +-------------+--------+--------+ FLAGS: . . . . . . . +SHX abs,y | 9Eh | 5 | +-------------+--------+--------+ + + +* SHA: calculates the AND of the accumulator with the X register with the high byte + of the memory pointer plus 1 and it stores the final result in memory. + +Address mode | opcode | cycles | N V B D I Z C +-------------+--------+--------+ FLAGS: . . . . . . . +SHX abs,y | 9Fh | 5 | +SHX (zp),y | 93h | 6 | +-------------+--------+--------+ + + +* ANC: calculates the AND of the accumulator with an immediate value and then + updates the status of N and Z bits of the status register. + The N flag is also copied into the Carry flag. + +Address mode | opcode | cycles | N V B D I Z C +-------------+--------+--------+ FLAGS: X . . . . X X +ANC #imm | 0Bh | 2 | +ANC #imm | 2Bh | 2 | +-------------+--------+--------+ + + +* LAS: calculates the contents of a memory location with the contents of the +stack pointer register and it stores the result in the accumulator, the X +register, and the stack pointer. + +Address mode | opcode | cycles | N V B D I Z C +-------------+--------+--------+ FLAGS: X . . . . X . +LAS abs,y | BBh | 4* | +-------------+--------+--------+ * = adds +1 if page cross is detected. + + +* SBC: alias of the official SBC opcode. + +Address mode | opcode | cycles | N V B D I Z C +-------------+--------+--------+ FLAGS: X X . . . X X +SBC #imm | EBh | 2 | +-------------+--------+--------+ + + +*/ /*****************************************************************************/ /* Data */ @@ -113,118 +445,223 @@ static unsigned HaveIRQRequest; /* Test for page cross */ #define PAGE_CROSS(addr,offs) ((((addr) & 0xFF) + offs) >= 0x100) -/* #imm */ -#define AC_OP_IMM(op) \ - Cycles = 2; \ - Regs.AC = Regs.AC op MemReadByte (Regs.PC+1); \ - TEST_ZF (Regs.AC); \ - TEST_SF (Regs.AC); \ - Regs.PC += 2 +/* Address operators */ /* zp */ -#define AC_OP_ZP(op) \ - Cycles = 3; \ - Regs.AC = Regs.AC op MemReadByte (MemReadByte (Regs.PC+1)); \ - TEST_ZF (Regs.AC); \ - TEST_SF (Regs.AC); \ +#define ADR_ZP(ad) \ + ad = MemReadByte (Regs.PC+1); \ Regs.PC += 2 /* zp,x */ -#define AC_OP_ZPX(op) \ - unsigned char ZPAddr; \ - Cycles = 4; \ - ZPAddr = MemReadByte (Regs.PC+1) + Regs.XR; \ - Regs.AC = Regs.AC op MemReadByte (ZPAddr); \ - TEST_ZF (Regs.AC); \ - TEST_SF (Regs.AC); \ +#define ADR_ZPX(ad) \ + ad = (MemReadByte (Regs.PC+1) + Regs.XR) & 0xFF; \ Regs.PC += 2 /* zp,y */ -#define AC_OP_ZPY(op) \ - unsigned char ZPAddr; \ - Cycles = 4; \ - ZPAddr = MemReadByte (Regs.PC+1) + Regs.YR; \ - Regs.AC = Regs.AC op MemReadByte (ZPAddr); \ - TEST_ZF (Regs.AC); \ - TEST_SF (Regs.AC); \ +#define ADR_ZPY(ad) \ + ad = (MemReadByte (Regs.PC+1) + Regs.YR) & 0xFF; \ Regs.PC += 2 /* abs */ -#define AC_OP_ABS(op) \ - unsigned Addr; \ - Cycles = 4; \ - Addr = MemReadWord (Regs.PC+1); \ - Regs.AC = Regs.AC op MemReadByte (Addr); \ - TEST_ZF (Regs.AC); \ - TEST_SF (Regs.AC); \ +#define ADR_ABS(ad) \ + ad = MemReadWord (Regs.PC+1); \ Regs.PC += 3 /* abs,x */ -#define AC_OP_ABSX(op) \ - unsigned Addr; \ - Cycles = 4; \ - Addr = MemReadWord (Regs.PC+1); \ - if (PAGE_CROSS (Addr, Regs.XR)) { \ +#define ADR_ABSX(ad) \ + ad = MemReadWord (Regs.PC+1); \ + if (PAGE_CROSS (ad, Regs.XR)) { \ ++Cycles; \ } \ - Regs.AC = Regs.AC op MemReadByte (Addr + Regs.XR); \ - TEST_ZF (Regs.AC); \ - TEST_SF (Regs.AC); \ + ad += Regs.XR; \ Regs.PC += 3 /* abs,y */ -#define AC_OP_ABSY(op) \ - unsigned Addr; \ - Cycles = 4; \ - Addr = MemReadWord (Regs.PC+1); \ - if (PAGE_CROSS (Addr, Regs.YR)) { \ +#define ADR_ABSY(ad) \ + ad = MemReadWord (Regs.PC+1); \ + if (PAGE_CROSS (ad, Regs.YR)) { \ ++Cycles; \ } \ - Regs.AC = Regs.AC op MemReadByte (Addr + Regs.YR); \ - TEST_ZF (Regs.AC); \ - TEST_SF (Regs.AC); \ + ad += Regs.YR; \ Regs.PC += 3 /* (zp,x) */ -#define AC_OP_ZPXIND(op) \ - unsigned char ZPAddr; \ - unsigned Addr; \ - Cycles = 6; \ - ZPAddr = MemReadByte (Regs.PC+1) + Regs.XR; \ - Addr = MemReadZPWord (ZPAddr); \ - Regs.AC = Regs.AC op MemReadByte (Addr); \ - TEST_ZF (Regs.AC); \ - TEST_SF (Regs.AC); \ +#define ADR_ZPXIND(ad) \ + ad = (MemReadByte (Regs.PC+1) + Regs.XR) & 0xFF; \ + ad = MemReadZPWord (ad); \ Regs.PC += 2 /* (zp),y */ -#define AC_OP_ZPINDY(op) \ - unsigned char ZPAddr; \ - unsigned Addr; \ - Cycles = 5; \ - ZPAddr = MemReadByte (Regs.PC+1); \ - Addr = MemReadZPWord (ZPAddr); \ - if (PAGE_CROSS (Addr, Regs.YR)) { \ +#define ADR_ZPINDY(ad) \ + ad = MemReadZPWord (MemReadByte (Regs.PC+1)); \ + if (PAGE_CROSS (ad, Regs.YR)) { \ ++Cycles; \ } \ - Addr += Regs.YR; \ - Regs.AC = Regs.AC op MemReadByte (Addr); \ - TEST_ZF (Regs.AC); \ - TEST_SF (Regs.AC); \ + ad += Regs.YR; \ Regs.PC += 2 /* (zp) */ -#define AC_OP_ZPIND(op) \ - unsigned char ZPAddr; \ - unsigned Addr; \ - Cycles = 5; \ - ZPAddr = MemReadByte (Regs.PC+1); \ - Addr = MemReadZPWord (ZPAddr); \ - Regs.AC = Regs.AC op MemReadByte (Addr); \ - TEST_ZF (Regs.AC); \ - TEST_SF (Regs.AC); \ +#define ADR_ZPIND(ad) \ + ad = MemReadZPWord (MemReadByte (Regs.PC+1)); \ Regs.PC += 2 +/* Address operators (no penalty on page cross) */ + +/* abs,x - no penalty */ +#define ADR_ABSX_NP(ad) \ + ad = MemReadWord (Regs.PC+1); \ + ad += Regs.XR; \ + Regs.PC += 3 + +/* abs,y - no penalty */ +#define ADR_ABSY_NP(ad) \ + ad = MemReadWord (Regs.PC+1); \ + ad += Regs.YR; \ + Regs.PC += 3 + +/* (zp),y - no penalty */ +#define ADR_ZPINDY_NP(ad) \ + ad = MemReadZPWord (MemReadByte (Regs.PC+1)); \ + ad += Regs.YR; \ + Regs.PC += 2 + + + +/* Memory operators */ + +/* #imm */ +#define MEM_AD_OP_IMM(op) \ + op = MemReadByte (Regs.PC+1); \ + Regs.PC += 2 + +/* zp / zp,x / zp,y / abs / abs,x / abs,y / (zp,x) / (zp),y / (zp) */ +#define MEM_AD_OP(mode, ad, op) \ + ADR_##mode(ad); \ + op = MemReadByte (ad) + +/* ALU opcode helpers */ + +/* Execution cycles for ALU opcodes */ +#define ALU_CY_ZP 3 +#define ALU_CY_ZPX 4 +#define ALU_CY_ZPY 4 +#define ALU_CY_ABS 4 +#define ALU_CY_ABSX 4 +#define ALU_CY_ABSY 4 +#define ALU_CY_ZPXIND 6 +#define ALU_CY_ZPINDY 5 +#define ALU_CY_ZPIND 5 + +/* #imm */ +#define ALU_OP_IMM(op) \ + unsigned char immediate; \ + MEM_AD_OP_IMM(immediate); \ + Cycles = 2; \ + op (immediate) + +/* zp / zp,x / zp,y / abs / abs,x / abs,y / (zp,x) / (zp),y / (zp) */ +#define ALU_OP(mode, op) \ + unsigned address, operand; \ + Cycles = ALU_CY_##mode; \ + MEM_AD_OP (mode, address, operand); \ + op (operand) + +/* Store opcode helpers */ + +/* Execution cycles for store opcodes */ +#define STO_CY_ZP 3 +#define STO_CY_ZPX 4 +#define STO_CY_ZPY 4 +#define STO_CY_ABS 4 +#define STO_CY_ABSX 5 +#define STO_CY_ABSY 5 +#define STO_CY_ZPXIND 6 +#define STO_CY_ZPINDY 6 +#define STO_CY_ZPIND 5 + +/* zp / zp,x / zp,y / abs / abs,x / abs,y / (zp,x) / (zp),y / (zp) */ +#define STO_OP(mode, op) \ + unsigned address; \ + Cycles = STO_CY_##mode; \ + ADR_##mode (address); \ + MemWriteByte(address, op) + +/* zp / zp,x / zp,y / abs / abs,x / abs,y / (zp,x) / (zp),y / (zp) */ +#define STO_CB(mode, cb) \ + unsigned address, operand; \ + Cycles = STO_CY_##mode; \ + ADR_##mode (address); \ + cb (operand); \ + MemWriteByte(address, operand) + +/* Read-Modify-Write opcode helpers */ + +/* Execution cycles for R-M-W opcodes */ +#define RMW_CY_ZP 5 +#define RMW_CY_ZPX 6 +#define RMW_CY_ZPY 6 +#define RMW_CY_ABS 6 +#define RMW_CY_ABSX 7 +#define RMW_CY_ABSY 7 +#define RMW_CY_ZPXIND 6 +#define RMW_CY_ZPINDY 5 +#define RMW_CY_ZPIND 5 + +#define RMW_CY_ABSX_NP RMW_CY_ABSX +#define RMW_CY_ABSY_NP RMW_CY_ABSY +#define RMW_CY_ZPINDY_NP RMW_CY_ZPINDY + +/* zp / zp,x / zp,y / abs / abs,x / abs,y / (zp,x) / (zp),y / (zp) */ +#define MEM_OP(mode, op) \ + unsigned address, operand; \ + Cycles = RMW_CY_##mode; \ + MEM_AD_OP (mode, address, operand); \ + op (operand); \ + MemWriteByte (address, (unsigned char)operand) + +/* 2 x Read-Modify-Write opcode helpers (illegal opcodes) */ + +/* Execution cycles for 2 x R-M-W opcodes */ +#define RMW2_CY_ZP 5 +#define RMW2_CY_ZPX 6 +#define RMW2_CY_ZPY 6 +#define RMW2_CY_ABS 6 +#define RMW2_CY_ABSX 7 +#define RMW2_CY_ABSY 7 +#define RMW2_CY_ZPXIND 8 +#define RMW2_CY_ZPINDY 8 + +/* zp / zp,x / zp,y / abs / abs,x / abs,y / (zp,x) / (zp),y */ +#define ILLx2_OP(mode, op) \ + unsigned address; \ + unsigned operand; \ + Cycles = RMW2_CY_##mode; \ + MEM_AD_OP (mode, address, operand); \ + op (operand); \ + MemWriteByte (address, (unsigned char)operand) + +/* AC opcode helpers */ + +/* #imm */ +#define AC_OP_IMM(op) \ + unsigned char immediate; \ + MEM_AD_OP_IMM(immediate); \ + Cycles = 2; \ + Regs.AC = Regs.AC op immediate; \ + TEST_ZF (Regs.AC); \ + TEST_SF (Regs.AC) + +/* zp / zp,x / zp,y / abs / abs,x / abs,y / (zp,x) / (zp),y / (zp) */ +#define AC_OP(mode, op) \ + unsigned address; \ + unsigned operand; \ + Cycles = ALU_CY_##mode; \ + MEM_AD_OP(mode, address, operand); \ + Regs.AC = Regs.AC op operand; \ + TEST_ZF (Regs.AC); \ + TEST_SF (Regs.AC) + + /* ADC */ #define ADC(v) \ do { \ @@ -248,7 +685,7 @@ static unsigned HaveIRQRequest; } \ TEST_CF (Regs.AC); \ SET_OF ((res < -128) || (res > 127)); \ - if (CPU != CPU_6502) { \ + if (CPU == CPU_65C02) { \ ++Cycles; \ } \ } else { \ @@ -271,7 +708,7 @@ static unsigned HaveIRQRequest; ++Cycles; \ Offs = (signed char) MemReadByte (Regs.PC+1); \ OldPCH = PCH; \ - Regs.PC += 2 + (int) Offs; \ + Regs.PC = (Regs.PC + 2 + (int) Offs) & 0xFFFF; \ if (PCH != OldPCH) { \ ++Cycles; \ } \ @@ -280,14 +717,22 @@ static unsigned HaveIRQRequest; } /* compares */ -#define CMP(v1, v2) \ +#define COMPARE(v1, v2) \ do { \ unsigned Result = v1 - v2; \ - TEST_ZF (Result & 0xFF); \ + TEST_ZF (Result); \ TEST_SF (Result); \ SET_CF (Result <= 0xFF); \ } while (0) +#define CPX(operand) \ + COMPARE (Regs.XR, operand) + +#define CPY(operand) \ + COMPARE (Regs.YR, operand) + +#define CMP(operand) \ + COMPARE (Regs.AC, operand) /* ROL */ #define ROL(Val) \ @@ -309,38 +754,243 @@ static unsigned HaveIRQRequest; TEST_ZF (Val); \ TEST_SF (Val) -/* SBC */ -#define SBC(v) \ +/* ASL */ +#define ASL(Val) \ + SET_CF (Val & 0x80); \ + Val = (Val << 1) & 0xFF; \ + TEST_ZF (Val); \ + TEST_SF (Val) + +/* LSR */ +#define LSR(Val) \ + SET_CF (Val & 0x01); \ + Val >>= 1; \ + TEST_ZF (Val); \ + TEST_SF (Val) + +/* INC */ +#define INC(Val) \ + Val = (Val + 1) & 0xFF; \ + TEST_ZF (Val); \ + TEST_SF (Val) + +/* DEC */ +#define DEC(Val) \ + Val = (Val - 1) & 0xFF; \ + TEST_ZF (Val); \ + TEST_SF (Val) + +/* SLO */ +#define SLO(Val) \ + Val <<= 1; \ + SET_CF (Val & 0x100); \ + Regs.AC |= Val; \ + Regs.AC &= 0xFF; \ + TEST_ZF (Regs.AC); \ + TEST_SF (Regs.AC) + +/* RLA */ +#define RLA(Val) \ + Val <<= 1; \ + if (GET_CF ()) { \ + Val |= 0x01; \ + } \ + SET_CF (Val & 0x100); \ + Regs.AC &= Val; \ + TEST_ZF (Regs.AC); \ + TEST_SF (Regs.AC) + +/* SRE */ +#define SRE(Val) \ + SET_CF (Val & 0x01); \ + Val >>= 1; \ + Regs.AC ^= Val; \ + TEST_ZF (Regs.AC); \ + TEST_SF (Regs.AC) + +/* RRA */ +#define RRA(Val) \ + if (GET_CF ()) { \ + Val |= 0x100; \ + } \ + SET_CF (Val & 0x01); \ + Val >>= 1; \ + ADC (Val) + +/* BIT */ +#define BIT(Val) \ + SET_SF (Val & 0x80); \ + SET_OF (Val & 0x40); \ + SET_ZF ((Val & Regs.AC) == 0) + +/* LDA */ +#define LDA(Val) \ + Regs.AC = Val; \ + TEST_SF (Val); \ + TEST_ZF (Val) + +/* LDX */ +#define LDX(Val) \ + Regs.XR = Val; \ + TEST_SF (Val); \ + TEST_ZF (Val) + +/* LDY */ +#define LDY(Val) \ + Regs.YR = Val; \ + TEST_SF (Val); \ + TEST_ZF (Val) + +/* LAX */ +#define LAX(Val) \ + Regs.AC = Val; \ + Regs.XR = Val; \ + TEST_SF (Val); \ + TEST_ZF (Val) + +/* TSB */ +#define TSB(Val) \ + SET_ZF ((Val & Regs.AC) == 0); \ + Val |= Regs.AC + +/* TRB */ +#define TRB(Val) \ + SET_ZF ((Val & Regs.AC) == 0); \ + Val &= ~Regs.AC + +/* DCP */ +#define DCP(Val) \ + Val = (Val - 1) & 0xFF; \ + COMPARE (Regs.AC, Val) + +/* ISC */ +#define ISC(Val) \ + Val = (Val + 1) & 0xFF; \ + SBC(Val) + +/* ASR */ +#define ASR(Val) \ + Regs.AC &= Val; \ + LSR(Regs.AC) + +/* ARR */ +#define ARR(Val) \ do { \ - unsigned old = Regs.AC; \ - unsigned rhs = (v & 0xFF); \ + unsigned tmp = Regs.AC & Val; \ + Val = tmp >> 1; \ + if (GET_CF ()) { \ + Val |= 0x80; \ + } \ if (GET_DF ()) { \ - unsigned lo; \ - int res; \ - lo = (old & 0x0F) - (rhs & 0x0F) + GET_CF () - 1; \ - if (lo & 0x80) { \ - lo = ((lo - 0x06) & 0x0F) - 0x10; \ + SET_SF (GET_CF ()); \ + TEST_ZF (Val); \ + SET_OF ((Val ^ tmp) & 0x40); \ + if (((tmp & 0x0f) + (tmp & 0x01)) > 0x05) { \ + Val = (Val & 0xf0) | ((Val + 0x06) & 0x0f); \ } \ - Regs.AC = (old & 0xF0) - (rhs & 0xF0) + lo; \ - if (Regs.AC & 0x80) { \ - Regs.AC -= 0x60; \ + if (((tmp & 0xf0) + (tmp & 0x10)) > 0x50) { \ + Val = (Val & 0x0f) | ((Val + 0x60) & 0xf0); \ + SET_CF(1); \ + } else { \ + SET_CF(0); \ } \ - res = Regs.AC - rhs + (!GET_CF ()); \ - TEST_ZF (res); \ - TEST_SF (res); \ - SET_CF (res <= 0xFF); \ - SET_OF (((old^rhs) & (old^res) & 0x80)); \ - if (CPU != CPU_6502) { \ + if (CPU == CPU_65C02) { \ ++Cycles; \ } \ } else { \ - Regs.AC -= rhs + (!GET_CF ()); \ - TEST_ZF (Regs.AC); \ - TEST_SF (Regs.AC); \ - SET_CF (Regs.AC <= 0xFF); \ - SET_OF (((old^rhs) & (old^Regs.AC) & 0x80)); \ - Regs.AC &= 0xFF; \ + TEST_SF (Val); \ + TEST_ZF (Val); \ + SET_CF (Val & 0x40); \ + SET_OF ((Val & 0x40) ^ ((Val & 0x20) << 1)); \ } \ + Regs.AC = Val; \ + } while (0); + +/* ANE */ +#define ANE(Val) \ + Val = (Regs.AC | 0xEF) & Regs.XR & Val; \ + Regs.AC = Val; \ + TEST_SF (Val); \ + TEST_ZF (Val) + +/* LXA */ +#define LXA(Val) \ + Val = (Regs.AC | 0xEE) & Val; \ + Regs.AC = Val; \ + Regs.XR = Val; \ + TEST_SF (Val); \ + TEST_ZF (Val) + +/* SBX */ +#define SBX(Val) \ + do { \ + unsigned tmp = (Regs.AC & Regs.XR) - (Val); \ + SET_CF (tmp < 0x100); \ + tmp &= 0xFF; \ + Regs.XR = tmp; \ + TEST_SF (tmp); \ + TEST_ZF (tmp); \ + } while (0); + +/* NOP */ +#define NOP(Val) \ + (void)Val + +/* TAS */ +#define TAS(Val) \ + Val = Regs.AC & Regs.XR; \ + Regs.SP = Val; \ + Val &= (address >> 8) + 1 + +/* SHA */ +#define SHA(Val) \ + Val = Regs.AC & Regs.XR & ((address >> 8) + 1) + +/* ANC */ +#define ANC(Val) \ + Val = Regs.AC & Val; \ + Regs.AC = Val; \ + SET_CF (Val & 0x80); \ + TEST_SF (Val); \ + TEST_ZF (Val) + + +/* LAS */ +#define LAS(Val) \ + Val = Regs.SP & Val; \ + Regs.AC = Val; \ + Regs.XR = Val; \ + Regs.SP = Val; \ + TEST_SF (Val); \ + TEST_ZF (Val) + + +/* SBC */ +#define SBC(v) \ + do { \ + unsigned r_a = Regs.AC; \ + unsigned src = (v) & 0xFF; \ + unsigned ccc = (Regs.SR & CF) ^ CF; \ + unsigned tmp = r_a - src - ccc; \ + \ + SET_CF(tmp < 0x100); \ + TEST_SF(tmp); \ + TEST_ZF(tmp); \ + SET_OF((r_a ^ tmp) & (r_a ^ src) & 0x80); \ + \ + if (GET_DF ()) { \ + unsigned low = (r_a & 0x0f) - (src & 0x0f) - ccc; \ + tmp = (r_a & 0xf0) - (src & 0xf0); \ + if (low & 0x10) { \ + low -= 6; \ + tmp -= 0x10; \ + } \ + tmp = (low & 0xf) | tmp; \ + if (tmp & 0x100) { \ + tmp -= 0x60; \ + } \ + } \ + Regs.AC = tmp & 0xFF; \ } while (0) @@ -368,7 +1018,7 @@ static void OPC_6502_00 (void) PUSH (PCL); PUSH (Regs.SR); SET_IF (1); - if (CPU != CPU_6502) + if (CPU == CPU_65C02) { SET_DF (0); } @@ -380,7 +1030,27 @@ static void OPC_6502_00 (void) static void OPC_6502_01 (void) /* Opcode $01: ORA (ind,x) */ { - AC_OP_ZPXIND (|); + AC_OP (ZPXIND, |); +} + + + +static void OPC_6502_03 (void) +/* Opcode $03: SLO (zp,x) */ +{ + ILLx2_OP (ZPXIND, SLO); +} + + + +/* Aliases of opcode $04 */ +#define OPC_6502_44 OPC_6502_04 +#define OPC_6502_64 OPC_6502_04 + +static void OPC_6502_04 (void) +/* Opcode $04: NOP zp */ +{ + ALU_OP (ZP, NOP); } @@ -388,14 +1058,7 @@ static void OPC_6502_01 (void) static void OPC_65SC02_04 (void) /* Opcode $04: TSB zp */ { - unsigned char ZPAddr; - unsigned char Val; - Cycles = 5; - ZPAddr = MemReadByte (Regs.PC+1); - Val = MemReadByte (ZPAddr); - SET_ZF ((Val & Regs.AC) == 0); - MemWriteByte (ZPAddr, (unsigned char)(Val | Regs.AC)); - Regs.PC += 2; + MEM_OP (ZP, TSB); } @@ -403,7 +1066,7 @@ static void OPC_65SC02_04 (void) static void OPC_6502_05 (void) /* Opcode $05: ORA zp */ { - AC_OP_ZP (|); + AC_OP (ZP, |); } @@ -411,16 +1074,15 @@ static void OPC_6502_05 (void) static void OPC_6502_06 (void) /* Opcode $06: ASL zp */ { - unsigned char ZPAddr; - unsigned Val; - Cycles = 5; - ZPAddr = MemReadByte (Regs.PC+1); - Val = MemReadByte (ZPAddr) << 1; - MemWriteByte (ZPAddr, (unsigned char) Val); - TEST_ZF (Val & 0xFF); - TEST_SF (Val); - SET_CF (Val & 0x100); - Regs.PC += 2; + MEM_OP (ZP, ASL); +} + + + +static void OPC_6502_07 (void) +/* Opcode $07: SLO zp */ +{ + ILLx2_OP (ZP, SLO); } @@ -447,27 +1109,35 @@ static void OPC_6502_0A (void) /* Opcode $0A: ASL a */ { Cycles = 2; - Regs.AC <<= 1; - TEST_ZF (Regs.AC & 0xFF); - TEST_SF (Regs.AC); - SET_CF (Regs.AC & 0x100); - Regs.AC &= 0xFF; + ASL(Regs.AC); Regs.PC += 1; } +/* Aliases of opcode $0B */ +#define OPC_6502_2B OPC_6502_0B + +static void OPC_6502_0B (void) +/* Opcode $0B: ANC #imm */ +{ + ALU_OP_IMM (ANC); +} + + + +static void OPC_6502_0C (void) +/* Opcode $0C: NOP abs */ +{ + ALU_OP (ABS, NOP); +} + + + static void OPC_65SC02_0C (void) /* Opcode $0C: TSB abs */ { - unsigned Addr; - unsigned char Val; - Cycles = 6; - Addr = MemReadWord (Regs.PC+1); - Val = MemReadByte (Addr); - SET_ZF ((Val & Regs.AC) == 0); - MemWriteByte (Addr, (unsigned char) (Val | Regs.AC)); - Regs.PC += 3; + MEM_OP (ABS, TSB); } @@ -475,24 +1145,23 @@ static void OPC_65SC02_0C (void) static void OPC_6502_0D (void) /* Opcode $0D: ORA abs */ { - AC_OP_ABS (|); + AC_OP (ABS, |); } static void OPC_6502_0E (void) -/* Opcode $0E: ALS abs */ +/* Opcode $0E: ASL abs */ { - unsigned Addr; - unsigned Val; - Cycles = 6; - Addr = MemReadWord (Regs.PC+1); - Val = MemReadByte (Addr) << 1; - MemWriteByte (Addr, (unsigned char) Val); - TEST_ZF (Val & 0xFF); - TEST_SF (Val); - SET_CF (Val & 0x100); - Regs.PC += 3; + MEM_OP (ABS, ASL); +} + + + +static void OPC_6502_0F (void) +/* Opcode $0F: SLO abs */ +{ + ILLx2_OP (ABS, SLO); } @@ -508,7 +1177,7 @@ static void OPC_6502_10 (void) static void OPC_6502_11 (void) /* Opcode $11: ORA (zp),y */ { - AC_OP_ZPINDY (|); + AC_OP (ZPINDY, |); } @@ -516,7 +1185,30 @@ static void OPC_6502_11 (void) static void OPC_65SC02_12 (void) /* Opcode $12: ORA (zp) */ { - AC_OP_ZPIND (|); + AC_OP (ZPIND, |); +} + + + +static void OPC_6502_13 (void) +/* Opcode $03: SLO (zp),y */ +{ + ILLx2_OP (ZPINDY, SLO); +} + + + +/* Aliases of opcode $14 */ +#define OPC_6502_34 OPC_6502_14 +#define OPC_6502_54 OPC_6502_14 +#define OPC_6502_74 OPC_6502_14 +#define OPC_6502_D4 OPC_6502_14 +#define OPC_6502_F4 OPC_6502_14 + +static void OPC_6502_14 (void) +/* Opcode $04: NOP zp,x */ +{ + ALU_OP (ZPX, NOP); } @@ -524,14 +1216,7 @@ static void OPC_65SC02_12 (void) static void OPC_65SC02_14 (void) /* Opcode $14: TRB zp */ { - unsigned char ZPAddr; - unsigned char Val; - Cycles = 5; - ZPAddr = MemReadByte (Regs.PC+1); - Val = MemReadByte (ZPAddr); - SET_ZF ((Val & Regs.AC) == 0); - MemWriteByte (ZPAddr, (unsigned char)(Val & ~Regs.AC)); - Regs.PC += 2; + MEM_OP (ZP, TRB); } @@ -539,7 +1224,7 @@ static void OPC_65SC02_14 (void) static void OPC_6502_15 (void) /* Opcode $15: ORA zp,x */ { - AC_OP_ZPX (|); + AC_OP (ZPX, |); } @@ -547,16 +1232,15 @@ static void OPC_6502_15 (void) static void OPC_6502_16 (void) /* Opcode $16: ASL zp,x */ { - unsigned char ZPAddr; - unsigned Val; - Cycles = 6; - ZPAddr = MemReadByte (Regs.PC+1) + Regs.XR; - Val = MemReadByte (ZPAddr) << 1; - MemWriteByte (ZPAddr, (unsigned char) Val); - TEST_ZF (Val & 0xFF); - TEST_SF (Val); - SET_CF (Val & 0x100); - Regs.PC += 2; + MEM_OP (ZPX, ASL); +} + + + +static void OPC_6502_17 (void) +/* Opcode $17: SLO zp,x */ +{ + ILLx2_OP (ZPX, SLO); } @@ -574,7 +1258,7 @@ static void OPC_6502_18 (void) static void OPC_6502_19 (void) /* Opcode $19: ORA abs,y */ { - AC_OP_ABSY (|); + AC_OP (ABSY, |); } @@ -583,25 +1267,39 @@ static void OPC_65SC02_1A (void) /* Opcode $1A: INC a */ { Cycles = 2; - Regs.AC = (Regs.AC + 1) & 0xFF; - TEST_ZF (Regs.AC); - TEST_SF (Regs.AC); + INC(Regs.AC); Regs.PC += 1; } +static void OPC_6502_1B (void) +/* Opcode $1B: SLO abs,y */ +{ + ILLx2_OP (ABSY, SLO); +} + + + +/* Aliases of opcode $1C */ +#define OPC_6502_3C OPC_6502_1C +#define OPC_6502_5C OPC_6502_1C +#define OPC_6502_7C OPC_6502_1C +#define OPC_6502_DC OPC_6502_1C +#define OPC_6502_FC OPC_6502_1C + +static void OPC_6502_1C (void) +/* Opcode $1C: NOP abs,x */ +{ + ALU_OP (ABSX, NOP); +} + + + static void OPC_65SC02_1C (void) /* Opcode $1C: TRB abs */ { - unsigned Addr; - unsigned char Val; - Cycles = 6; - Addr = MemReadWord (Regs.PC+1); - Val = MemReadByte (Addr); - SET_ZF ((Val & Regs.AC) == 0); - MemWriteByte (Addr, (unsigned char) (Val & ~Regs.AC)); - Regs.PC += 3; + MEM_OP (ABS, TRB); } @@ -609,7 +1307,7 @@ static void OPC_65SC02_1C (void) static void OPC_6502_1D (void) /* Opcode $1D: ORA abs,x */ { - AC_OP_ABSX (|); + AC_OP (ABSX, |); } @@ -617,18 +1315,23 @@ static void OPC_6502_1D (void) static void OPC_6502_1E (void) /* Opcode $1E: ASL abs,x */ { - unsigned Addr; - unsigned Val; - Cycles = 7; - Addr = MemReadWord (Regs.PC+1) + Regs.XR; - if (CPU != CPU_6502 && !PAGE_CROSS (Addr, Regs.XR)) - --Cycles; - Val = MemReadByte (Addr) << 1; - MemWriteByte (Addr, (unsigned char) Val); - TEST_ZF (Val & 0xFF); - TEST_SF (Val); - SET_CF (Val & 0x100); - Regs.PC += 3; + MEM_OP (ABSX, ASL); +} + + + +static void OPC_65C02_1E (void) +/* Opcode $1E: ASL abs,x */ +{ + MEM_OP (ABSX_NP, ASL); +} + + + +static void OPC_6502_1F (void) +/* Opcode $1F: SLO abs,x */ +{ + ILLx2_OP (ABSX, SLO); } @@ -652,23 +1355,23 @@ static void OPC_6502_20 (void) static void OPC_6502_21 (void) /* Opcode $21: AND (zp,x) */ { - AC_OP_ZPXIND (&); + AC_OP (ZPXIND, &); +} + + + +static void OPC_6502_23 (void) +/* Opcode $23: RLA (zp,x) */ +{ + ILLx2_OP (ZPXIND, RLA); } static void OPC_6502_24 (void) -/* Opcode $24: BIT zp */ { - unsigned char ZPAddr; - unsigned char Val; - Cycles = 3; - ZPAddr = MemReadByte (Regs.PC+1); - Val = MemReadByte (ZPAddr); - SET_SF (Val & 0x80); - SET_OF (Val & 0x40); - SET_ZF ((Val & Regs.AC) == 0); - Regs.PC += 2; +/* Opcode $24: BIT zp */ + ALU_OP (ZP, BIT); } @@ -676,7 +1379,7 @@ static void OPC_6502_24 (void) static void OPC_6502_25 (void) /* Opcode $25: AND zp */ { - AC_OP_ZP (&); + AC_OP (ZP, &); } @@ -684,14 +1387,15 @@ static void OPC_6502_25 (void) static void OPC_6502_26 (void) /* Opcode $26: ROL zp */ { - unsigned char ZPAddr; - unsigned Val; - Cycles = 5; - ZPAddr = MemReadByte (Regs.PC+1); - Val = MemReadByte (ZPAddr); - ROL (Val); - MemWriteByte (ZPAddr, Val); - Regs.PC += 2; + MEM_OP (ZP, ROL); +} + + + +static void OPC_6502_27 (void) +/* Opcode $27: RLA zp */ +{ + ILLx2_OP (ZP, RLA); } @@ -730,15 +1434,7 @@ static void OPC_6502_2A (void) static void OPC_6502_2C (void) /* Opcode $2C: BIT abs */ { - unsigned Addr; - unsigned char Val; - Cycles = 4; - Addr = MemReadWord (Regs.PC+1); - Val = MemReadByte (Addr); - SET_SF (Val & 0x80); - SET_OF (Val & 0x40); - SET_ZF ((Val & Regs.AC) == 0); - Regs.PC += 3; + ALU_OP (ABS, BIT); } @@ -746,7 +1442,7 @@ static void OPC_6502_2C (void) static void OPC_6502_2D (void) /* Opcode $2D: AND abs */ { - AC_OP_ABS (&); + AC_OP (ABS, &); } @@ -754,14 +1450,15 @@ static void OPC_6502_2D (void) static void OPC_6502_2E (void) /* Opcode $2E: ROL abs */ { - unsigned Addr; - unsigned Val; - Cycles = 6; - Addr = MemReadWord (Regs.PC+1); - Val = MemReadByte (Addr); - ROL (Val); - MemWriteByte (Addr, Val); - Regs.PC += 3; + MEM_OP (ABS, ROL); +} + + + +static void OPC_6502_2F (void) +/* Opcode $2F: RLA abs */ +{ + ILLx2_OP (ABS, RLA); } @@ -777,7 +1474,7 @@ static void OPC_6502_30 (void) static void OPC_6502_31 (void) /* Opcode $31: AND (zp),y */ { - AC_OP_ZPINDY (&); + AC_OP (ZPINDY, &); } @@ -785,7 +1482,15 @@ static void OPC_6502_31 (void) static void OPC_65SC02_32 (void) /* Opcode $32: AND (zp) */ { - AC_OP_ZPIND (&); + AC_OP (ZPIND, &); +} + + + +static void OPC_6502_33 (void) +/* Opcode $33: RLA (zp),y */ +{ + ILLx2_OP (ZPINDY, RLA); } @@ -793,15 +1498,7 @@ static void OPC_65SC02_32 (void) static void OPC_65SC02_34 (void) /* Opcode $34: BIT zp,x */ { - unsigned char ZPAddr; - unsigned char Val; - Cycles = 4; - ZPAddr = MemReadByte (Regs.PC+1) + Regs.XR; - Val = MemReadByte (ZPAddr); - SET_SF (Val & 0x80); - SET_OF (Val & 0x40); - SET_ZF ((Val & Regs.AC) == 0); - Regs.PC += 2; + ALU_OP (ZPX, BIT); } @@ -809,7 +1506,7 @@ static void OPC_65SC02_34 (void) static void OPC_6502_35 (void) /* Opcode $35: AND zp,x */ { - AC_OP_ZPX (&); + AC_OP (ZPX, &); } @@ -817,14 +1514,15 @@ static void OPC_6502_35 (void) static void OPC_6502_36 (void) /* Opcode $36: ROL zp,x */ { - unsigned char ZPAddr; - unsigned Val; - Cycles = 6; - ZPAddr = MemReadByte (Regs.PC+1) + Regs.XR; - Val = MemReadByte (ZPAddr); - ROL (Val); - MemWriteByte (ZPAddr, Val); - Regs.PC += 2; + MEM_OP (ZPX, ROL); +} + + + +static void OPC_6502_37 (void) +/* Opcode $37: RLA zp,x */ +{ + ILLx2_OP (ZPX, RLA); } @@ -842,7 +1540,7 @@ static void OPC_6502_38 (void) static void OPC_6502_39 (void) /* Opcode $39: AND abs,y */ { - AC_OP_ABSY (&); + AC_OP (ABSY, &); } @@ -851,28 +1549,24 @@ static void OPC_65SC02_3A (void) /* Opcode $3A: DEC a */ { Cycles = 2; - Regs.AC = (Regs.AC - 1) & 0xFF; - TEST_ZF (Regs.AC); - TEST_SF (Regs.AC); + DEC (Regs.AC); Regs.PC += 1; } +static void OPC_6502_3B (void) +/* Opcode $3B: RLA abs,y */ +{ + ILLx2_OP (ABSY, RLA); +} + + + static void OPC_65SC02_3C (void) /* Opcode $3C: BIT abs,x */ { - unsigned Addr; - unsigned char Val; - Cycles = 4; - Addr = MemReadWord (Regs.PC+1); - if (PAGE_CROSS (Addr, Regs.XR)) - ++Cycles; - Val = MemReadByte (Addr + Regs.XR); - SET_SF (Val & 0x80); - SET_OF (Val & 0x40); - SET_ZF ((Val & Regs.AC) == 0); - Regs.PC += 3; + ALU_OP (ABSX, BIT); } @@ -880,7 +1574,7 @@ static void OPC_65SC02_3C (void) static void OPC_6502_3D (void) /* Opcode $3D: AND abs,x */ { - AC_OP_ABSX (&); + AC_OP (ABSX, &); } @@ -888,16 +1582,23 @@ static void OPC_6502_3D (void) static void OPC_6502_3E (void) /* Opcode $3E: ROL abs,x */ { - unsigned Addr; - unsigned Val; - Cycles = 7; - Addr = MemReadWord (Regs.PC+1) + Regs.XR; - if (CPU != CPU_6502 && !PAGE_CROSS (Addr, Regs.XR)) - --Cycles; - Val = MemReadByte (Addr); - ROL (Val); - MemWriteByte (Addr, Val); - Regs.PC += 2; + MEM_OP (ABSX, ROL); +} + + + +static void OPC_65C02_3E (void) +/* Opcode $3E: ROL abs,x */ +{ + MEM_OP (ABSX_NP, ROL); +} + + + +static void OPC_6502_3F (void) +/* Opcode $3B: RLA abs,x */ +{ + ILLx2_OP (ABSX, RLA); } @@ -918,16 +1619,15 @@ static void OPC_6502_40 (void) static void OPC_6502_41 (void) /* Opcode $41: EOR (zp,x) */ { - AC_OP_ZPXIND (^); + AC_OP (ZPXIND, ^); } -static void OPC_65C02_44 (void) -/* Opcode $44: 'zp' 3 cycle NOP */ +static void OPC_6502_43 (void) +/* Opcode $43: SRE (zp,x) */ { - Cycles = 3; - Regs.PC += 2; + ILLx2_OP (ZPXIND, SRE); } @@ -935,7 +1635,7 @@ static void OPC_65C02_44 (void) static void OPC_6502_45 (void) /* Opcode $45: EOR zp */ { - AC_OP_ZP (^); + AC_OP (ZP, ^); } @@ -943,17 +1643,15 @@ static void OPC_6502_45 (void) static void OPC_6502_46 (void) /* Opcode $46: LSR zp */ { - unsigned char ZPAddr; - unsigned char Val; - Cycles = 5; - ZPAddr = MemReadByte (Regs.PC+1); - Val = MemReadByte (ZPAddr); - SET_CF (Val & 0x01); - Val >>= 1; - MemWriteByte (ZPAddr, Val); - TEST_ZF (Val); - TEST_SF (Val); - Regs.PC += 2; + MEM_OP (ZP, LSR); +} + + + +static void OPC_6502_47 (void) +/* Opcode $47: SRE zp */ +{ + ILLx2_OP (ZP, SRE); } @@ -980,15 +1678,20 @@ static void OPC_6502_4A (void) /* Opcode $4A: LSR a */ { Cycles = 2; - SET_CF (Regs.AC & 0x01); - Regs.AC >>= 1; - TEST_ZF (Regs.AC); - TEST_SF (Regs.AC); + LSR (Regs.AC); Regs.PC += 1; } +static void OPC_6502_4B (void) +/* Opcode $4B: ASR imm */ +{ + ALU_OP_IMM (ASR); +} + + + static void OPC_6502_4C (void) /* Opcode $4C: JMP abs */ { @@ -1003,7 +1706,7 @@ static void OPC_6502_4C (void) static void OPC_6502_4D (void) /* Opcode $4D: EOR abs */ { - AC_OP_ABS (^); + AC_OP (ABS, ^); } @@ -1011,17 +1714,15 @@ static void OPC_6502_4D (void) static void OPC_6502_4E (void) /* Opcode $4E: LSR abs */ { - unsigned Addr; - unsigned char Val; - Cycles = 6; - Addr = MemReadWord (Regs.PC+1); - Val = MemReadByte (Addr); - SET_CF (Val & 0x01); - Val >>= 1; - MemWriteByte (Addr, Val); - TEST_ZF (Val); - TEST_SF (Val); - Regs.PC += 3; + MEM_OP (ABS, LSR); +} + + + +static void OPC_6502_4F (void) +/* Opcode $4F: SRE abs */ +{ + ILLx2_OP (ABS, SRE); } @@ -1037,7 +1738,7 @@ static void OPC_6502_50 (void) static void OPC_6502_51 (void) /* Opcode $51: EOR (zp),y */ { - AC_OP_ZPINDY (^); + AC_OP (ZPINDY, ^); } @@ -1045,7 +1746,15 @@ static void OPC_6502_51 (void) static void OPC_65SC02_52 (void) /* Opcode $52: EOR (zp) */ { - AC_OP_ZPIND (^); + AC_OP (ZPIND, ^); +} + + + +static void OPC_6502_53 (void) +/* Opcode $43: SRE (zp),y */ +{ + ILLx2_OP (ZPINDY, SRE); } @@ -1053,7 +1762,7 @@ static void OPC_65SC02_52 (void) static void OPC_6502_55 (void) /* Opcode $55: EOR zp,x */ { - AC_OP_ZPX (^); + AC_OP (ZPX, ^); } @@ -1061,17 +1770,15 @@ static void OPC_6502_55 (void) static void OPC_6502_56 (void) /* Opcode $56: LSR zp,x */ { - unsigned char ZPAddr; - unsigned char Val; - Cycles = 6; - ZPAddr = MemReadByte (Regs.PC+1) + Regs.XR; - Val = MemReadByte (ZPAddr); - SET_CF (Val & 0x01); - Val >>= 1; - MemWriteByte (ZPAddr, Val); - TEST_ZF (Val); - TEST_SF (Val); - Regs.PC += 2; + MEM_OP (ZPX, LSR); +} + + + +static void OPC_6502_57 (void) +/* Opcode $57: SRE zp,x */ +{ + ILLx2_OP (ZPX, SRE); } @@ -1089,7 +1796,7 @@ static void OPC_6502_58 (void) static void OPC_6502_59 (void) /* Opcode $59: EOR abs,y */ { - AC_OP_ABSY (^); + AC_OP (ABSY, ^); } @@ -1104,6 +1811,14 @@ static void OPC_65SC02_5A (void) +static void OPC_6502_5B (void) +/* Opcode $5B: SRE abs,y */ +{ + ILLx2_OP (ABSY, SRE); +} + + + static void OPC_65C02_5C (void) /* Opcode $5C: 'Absolute' 8 cycle NOP */ { @@ -1116,7 +1831,7 @@ static void OPC_65C02_5C (void) static void OPC_6502_5D (void) /* Opcode $5D: EOR abs,x */ { - AC_OP_ABSX (^); + AC_OP (ABSX, ^); } @@ -1124,19 +1839,23 @@ static void OPC_6502_5D (void) static void OPC_6502_5E (void) /* Opcode $5E: LSR abs,x */ { - unsigned Addr; - unsigned char Val; - Cycles = 7; - Addr = MemReadWord (Regs.PC+1) + Regs.XR; - if (CPU != CPU_6502 && !PAGE_CROSS (Addr, Regs.XR)) - --Cycles; - Val = MemReadByte (Addr); - SET_CF (Val & 0x01); - Val >>= 1; - MemWriteByte (Addr, Val); - TEST_ZF (Val); - TEST_SF (Val); - Regs.PC += 3; + MEM_OP (ABSX, LSR); +} + + + +static void OPC_65C02_5E (void) +/* Opcode $5E: LSR abs,x */ +{ + MEM_OP (ABSX_NP, LSR); +} + + + +static void OPC_6502_5F (void) +/* Opcode $5F: SRE abs,x */ +{ + ILLx2_OP (ABSX, SRE); } @@ -1155,13 +1874,15 @@ static void OPC_6502_60 (void) static void OPC_6502_61 (void) /* Opcode $61: ADC (zp,x) */ { - unsigned char ZPAddr; - unsigned Addr; - Cycles = 6; - ZPAddr = MemReadByte (Regs.PC+1) + Regs.XR; - Addr = MemReadZPWord (ZPAddr); - ADC (MemReadByte (Addr)); - Regs.PC += 2; + ALU_OP (ZPXIND, ADC); +} + + + +static void OPC_6502_63 (void) +/* Opcode $63: RRA (zp,x) */ +{ + ILLx2_OP (ZPXIND, RRA); } @@ -1169,11 +1890,7 @@ static void OPC_6502_61 (void) static void OPC_65SC02_64 (void) /* Opcode $64: STZ zp */ { - unsigned char ZPAddr; - Cycles = 3; - ZPAddr = MemReadByte (Regs.PC+1); - MemWriteByte (ZPAddr, 0); - Regs.PC += 2; + STO_OP (ZP, 0); } @@ -1181,11 +1898,7 @@ static void OPC_65SC02_64 (void) static void OPC_6502_65 (void) /* Opcode $65: ADC zp */ { - unsigned char ZPAddr; - Cycles = 3; - ZPAddr = MemReadByte (Regs.PC+1); - ADC (MemReadByte (ZPAddr)); - Regs.PC += 2; + ALU_OP (ZP, ADC); } @@ -1193,14 +1906,15 @@ static void OPC_6502_65 (void) static void OPC_6502_66 (void) /* Opcode $66: ROR zp */ { - unsigned char ZPAddr; - unsigned Val; - Cycles = 5; - ZPAddr = MemReadByte (Regs.PC+1); - Val = MemReadByte (ZPAddr); - ROR (Val); - MemWriteByte (ZPAddr, Val); - Regs.PC += 2; + MEM_OP (ZP, ROR); +} + + + +static void OPC_6502_67 (void) +/* Opcode $67: RRA zp */ +{ + ILLx2_OP (ZP, RRA); } @@ -1220,9 +1934,7 @@ static void OPC_6502_68 (void) static void OPC_6502_69 (void) /* Opcode $69: ADC #imm */ { - Cycles = 2; - ADC (MemReadByte (Regs.PC+1)); - Regs.PC += 2; + ALU_OP_IMM (ADC); } @@ -1237,6 +1949,14 @@ static void OPC_6502_6A (void) +static void OPC_6502_6B (void) +/* Opcode $6B: ARR imm */ +{ + ALU_OP_IMM (ARR); +} + + + static void OPC_6502_6C (void) /* Opcode $6C: JMP (ind) */ { @@ -1285,11 +2005,7 @@ static void OPC_65C02_6C (void) static void OPC_6502_6D (void) /* Opcode $6D: ADC abs */ { - unsigned Addr; - Cycles = 4; - Addr = MemReadWord (Regs.PC+1); - ADC (MemReadByte (Addr)); - Regs.PC += 3; + ALU_OP (ABS, ADC); } @@ -1297,14 +2013,15 @@ static void OPC_6502_6D (void) static void OPC_6502_6E (void) /* Opcode $6E: ROR abs */ { - unsigned Addr; - unsigned Val; - Cycles = 6; - Addr = MemReadWord (Regs.PC+1); - Val = MemReadByte (Addr); - ROR (Val); - MemWriteByte (Addr, Val); - Regs.PC += 3; + MEM_OP (ABS, ROR); +} + + + +static void OPC_6502_6F (void) +/* Opcode $6F: RRA abs */ +{ + ILLx2_OP (ABS, RRA); } @@ -1320,16 +2037,7 @@ static void OPC_6502_70 (void) static void OPC_6502_71 (void) /* Opcode $71: ADC (zp),y */ { - unsigned char ZPAddr; - unsigned Addr; - Cycles = 5; - ZPAddr = MemReadByte (Regs.PC+1); - Addr = MemReadZPWord (ZPAddr); - if (PAGE_CROSS (Addr, Regs.YR)) { - ++Cycles; - } - ADC (MemReadByte (Addr + Regs.YR)); - Regs.PC += 2; + ALU_OP (ZPINDY, ADC); } @@ -1337,13 +2045,15 @@ static void OPC_6502_71 (void) static void OPC_65SC02_72 (void) /* Opcode $72: ADC (zp) */ { - unsigned char ZPAddr; - unsigned Addr; - Cycles = 5; - ZPAddr = MemReadByte (Regs.PC+1); - Addr = MemReadZPWord (ZPAddr); - ADC (MemReadByte (Addr)); - Regs.PC += 2; + ALU_OP (ZPIND, ADC); +} + + + +static void OPC_6502_73 (void) +/* Opcode $73: RRA (zp),y */ +{ + ILLx2_OP (ZPINDY, RRA); } @@ -1351,11 +2061,7 @@ static void OPC_65SC02_72 (void) static void OPC_65SC02_74 (void) /* Opcode $74: STZ zp,x */ { - unsigned char ZPAddr; - Cycles = 4; - ZPAddr = MemReadByte (Regs.PC+1) + Regs.XR; - MemWriteByte (ZPAddr, 0); - Regs.PC += 2; + STO_OP (ZPX, 0); } @@ -1363,11 +2069,7 @@ static void OPC_65SC02_74 (void) static void OPC_6502_75 (void) /* Opcode $75: ADC zp,x */ { - unsigned char ZPAddr; - Cycles = 4; - ZPAddr = MemReadByte (Regs.PC+1) + Regs.XR; - ADC (MemReadByte (ZPAddr)); - Regs.PC += 2; + ALU_OP (ZPX, ADC); } @@ -1375,14 +2077,15 @@ static void OPC_6502_75 (void) static void OPC_6502_76 (void) /* Opcode $76: ROR zp,x */ { - unsigned char ZPAddr; - unsigned Val; - Cycles = 6; - ZPAddr = MemReadByte (Regs.PC+1) + Regs.XR; - Val = MemReadByte (ZPAddr); - ROR (Val); - MemWriteByte (ZPAddr, Val); - Regs.PC += 2; + MEM_OP (ZPX, ROR); +} + + + +static void OPC_6502_77 (void) +/* Opcode $77: RRA zp,x */ +{ + ILLx2_OP (ZPX, RRA); } @@ -1400,14 +2103,7 @@ static void OPC_6502_78 (void) static void OPC_6502_79 (void) /* Opcode $79: ADC abs,y */ { - unsigned Addr; - Cycles = 4; - Addr = MemReadWord (Regs.PC+1); - if (PAGE_CROSS (Addr, Regs.YR)) { - ++Cycles; - } - ADC (MemReadByte (Addr + Regs.YR)); - Regs.PC += 3; + ALU_OP (ABSY, ADC); } @@ -1424,6 +2120,14 @@ static void OPC_65SC02_7A (void) +static void OPC_6502_7B (void) +/* Opcode $7B: RRA abs,y */ +{ + ILLx2_OP (ABSY, RRA); +} + + + static void OPC_65SC02_7C (void) /* Opcode $7C: JMP (ind,X) */ { @@ -1441,14 +2145,7 @@ static void OPC_65SC02_7C (void) static void OPC_6502_7D (void) /* Opcode $7D: ADC abs,x */ { - unsigned Addr; - Cycles = 4; - Addr = MemReadWord (Regs.PC+1); - if (PAGE_CROSS (Addr, Regs.XR)) { - ++Cycles; - } - ADC (MemReadByte (Addr + Regs.XR)); - Regs.PC += 3; + ALU_OP (ABSX, ADC); } @@ -1456,16 +2153,37 @@ static void OPC_6502_7D (void) static void OPC_6502_7E (void) /* Opcode $7E: ROR abs,x */ { - unsigned Addr; - unsigned Val; - Cycles = 7; - Addr = MemReadWord (Regs.PC+1) + Regs.XR; - if (CPU != CPU_6502 && !PAGE_CROSS (Addr, Regs.XR)) - --Cycles; - Val = MemReadByte (Addr); - ROR (Val); - MemWriteByte (Addr, Val); - Regs.PC += 3; + MEM_OP (ABSX, ROR); +} + + + +static void OPC_65C02_7E (void) +/* Opcode $7E: ROR abs,x */ +{ + MEM_OP (ABSX_NP, ROR); +} + + + +static void OPC_6502_7F (void) +/* Opcode $7F: RRA abs,x */ +{ + ILLx2_OP (ABSX, RRA); +} + + + +/* Aliases of opcode $80 */ +#define OPC_6502_82 OPC_6502_80 +#define OPC_6502_C2 OPC_6502_80 +#define OPC_6502_E2 OPC_6502_80 +#define OPC_6502_89 OPC_6502_80 + +static void OPC_6502_80 (void) +/* Opcode $80: NOP imm */ +{ + ALU_OP_IMM (NOP); } @@ -1481,13 +2199,15 @@ static void OPC_65SC02_80 (void) static void OPC_6502_81 (void) /* Opcode $81: STA (zp,x) */ { - unsigned char ZPAddr; - unsigned Addr; - Cycles = 6; - ZPAddr = MemReadByte (Regs.PC+1) + Regs.XR; - Addr = MemReadZPWord (ZPAddr); - MemWriteByte (Addr, Regs.AC); - Regs.PC += 2; + STO_OP (ZPXIND, Regs.AC); +} + + + +static void OPC_6502_83 (void) +/* Opcode $83: SAX (zp,x) */ +{ + STO_OP (ZPXIND, Regs.AC & Regs.XR); } @@ -1495,11 +2215,7 @@ static void OPC_6502_81 (void) static void OPC_6502_84 (void) /* Opcode $84: STY zp */ { - unsigned char ZPAddr; - Cycles = 3; - ZPAddr = MemReadByte (Regs.PC+1); - MemWriteByte (ZPAddr, Regs.YR); - Regs.PC += 2; + STO_OP (ZP, Regs.YR); } @@ -1507,11 +2223,7 @@ static void OPC_6502_84 (void) static void OPC_6502_85 (void) /* Opcode $85: STA zp */ { - unsigned char ZPAddr; - Cycles = 3; - ZPAddr = MemReadByte (Regs.PC+1); - MemWriteByte (ZPAddr, Regs.AC); - Regs.PC += 2; + STO_OP (ZP, Regs.AC); } @@ -1519,11 +2231,15 @@ static void OPC_6502_85 (void) static void OPC_6502_86 (void) /* Opcode $86: STX zp */ { - unsigned char ZPAddr; - Cycles = 3; - ZPAddr = MemReadByte (Regs.PC+1); - MemWriteByte (ZPAddr, Regs.XR); - Regs.PC += 2; + STO_OP (ZP, Regs.XR); +} + + + +static void OPC_6502_87 (void) +/* Opcode $87: SAX zp */ +{ + STO_OP (ZP, Regs.AC & Regs.XR); } @@ -1532,9 +2248,7 @@ static void OPC_6502_88 (void) /* Opcode $88: DEY */ { Cycles = 2; - Regs.YR = (Regs.YR - 1) & 0xFF; - TEST_ZF (Regs.YR); - TEST_SF (Regs.YR); + DEC (Regs.YR); Regs.PC += 1; } @@ -1543,13 +2257,7 @@ static void OPC_6502_88 (void) static void OPC_65SC02_89 (void) /* Opcode $89: BIT #imm */ { - unsigned char Val; - Cycles = 2; - Val = MemReadByte (Regs.PC+1); - SET_SF (Val & 0x80); - SET_OF (Val & 0x40); - SET_ZF ((Val & Regs.AC) == 0); - Regs.PC += 2; + ALU_OP_IMM (BIT); } @@ -1566,14 +2274,18 @@ static void OPC_6502_8A (void) +static void OPC_6502_8B (void) +/* Opcode $8B: ANE imm */ +{ + ALU_OP_IMM (ANE); +} + + + static void OPC_6502_8C (void) /* Opcode $8C: STY abs */ { - unsigned Addr; - Cycles = 4; - Addr = MemReadWord (Regs.PC+1); - MemWriteByte (Addr, Regs.YR); - Regs.PC += 3; + STO_OP (ABS, Regs.YR); } @@ -1581,11 +2293,7 @@ static void OPC_6502_8C (void) static void OPC_6502_8D (void) /* Opcode $8D: STA abs */ { - unsigned Addr; - Cycles = 4; - Addr = MemReadWord (Regs.PC+1); - MemWriteByte (Addr, Regs.AC); - Regs.PC += 3; + STO_OP (ABS, Regs.AC); } @@ -1593,11 +2301,15 @@ static void OPC_6502_8D (void) static void OPC_6502_8E (void) /* Opcode $8E: STX abs */ { - unsigned Addr; - Cycles = 4; - Addr = MemReadWord (Regs.PC+1); - MemWriteByte (Addr, Regs.XR); - Regs.PC += 3; + STO_OP (ABS, Regs.XR); +} + + + +static void OPC_6502_8F (void) +/* Opcode $8F: SAX abs */ +{ + STO_OP (ABS, Regs.AC & Regs.XR); } @@ -1613,13 +2325,7 @@ static void OPC_6502_90 (void) static void OPC_6502_91 (void) /* Opcode $91: sta (zp),y */ { - unsigned char ZPAddr; - unsigned Addr; - Cycles = 6; - ZPAddr = MemReadByte (Regs.PC+1); - Addr = MemReadZPWord (ZPAddr) + Regs.YR; - MemWriteByte (Addr, Regs.AC); - Regs.PC += 2; + STO_OP (ZPINDY, Regs.AC); } @@ -1627,13 +2333,15 @@ static void OPC_6502_91 (void) static void OPC_65SC02_92 (void) /* Opcode $92: sta (zp) */ { - unsigned char ZPAddr; - unsigned Addr; - Cycles = 5; - ZPAddr = MemReadByte (Regs.PC+1); - Addr = MemReadZPWord (ZPAddr); - MemWriteByte (Addr, Regs.AC); - Regs.PC += 2; + STO_OP (ZPIND, Regs.AC); +} + + + +static void OPC_6502_93 (void) +/* Opcode $93: SHA (zp),y */ +{ + STO_CB (ZPINDY, SHA); } @@ -1641,11 +2349,7 @@ static void OPC_65SC02_92 (void) static void OPC_6502_94 (void) /* Opcode $94: STY zp,x */ { - unsigned char ZPAddr; - Cycles = 4; - ZPAddr = MemReadByte (Regs.PC+1) + Regs.XR; - MemWriteByte (ZPAddr, Regs.YR); - Regs.PC += 2; + STO_OP (ZPX, Regs.YR); } @@ -1653,11 +2357,7 @@ static void OPC_6502_94 (void) static void OPC_6502_95 (void) /* Opcode $95: STA zp,x */ { - unsigned char ZPAddr; - Cycles = 4; - ZPAddr = MemReadByte (Regs.PC+1) + Regs.XR; - MemWriteByte (ZPAddr, Regs.AC); - Regs.PC += 2; + STO_OP (ZPX, Regs.AC); } @@ -1665,11 +2365,15 @@ static void OPC_6502_95 (void) static void OPC_6502_96 (void) /* Opcode $96: stx zp,y */ { - unsigned char ZPAddr; - Cycles = 4; - ZPAddr = MemReadByte (Regs.PC+1) + Regs.YR; - MemWriteByte (ZPAddr, Regs.XR); - Regs.PC += 2; + STO_OP (ZPY, Regs.XR); +} + + + +static void OPC_6502_97 (void) +/* Opcode $97: SAX zp,y */ +{ + STO_OP (ZPY, Regs.AC & Regs.XR); } @@ -1689,11 +2393,7 @@ static void OPC_6502_98 (void) static void OPC_6502_99 (void) /* Opcode $99: STA abs,y */ { - unsigned Addr; - Cycles = 5; - Addr = MemReadWord (Regs.PC+1) + Regs.YR; - MemWriteByte (Addr, Regs.AC); - Regs.PC += 3; + STO_OP (ABSY, Regs.AC); } @@ -1708,14 +2408,26 @@ static void OPC_6502_9A (void) +static void OPC_6502_9B (void) +/* Opcode $9B: TAS abs,y */ +{ + STO_CB (ABSY, TAS); +} + + + +static void OPC_6502_9C (void) +/* Opcode $9D: SHY abs,x */ +{ + STO_OP (ABSX, Regs.YR & ((address >> 8) + 1)); +} + + + static void OPC_65SC02_9C (void) /* Opcode $9C: STZ abs */ { - unsigned Addr; - Cycles = 4; - Addr = MemReadWord (Regs.PC+1); - MemWriteByte (Addr, 0); - Regs.PC += 3; + STO_OP (ABS, 0); } @@ -1723,11 +2435,23 @@ static void OPC_65SC02_9C (void) static void OPC_6502_9D (void) /* Opcode $9D: STA abs,x */ { - unsigned Addr; - Cycles = 5; - Addr = MemReadWord (Regs.PC+1) + Regs.XR; - MemWriteByte (Addr, Regs.AC); - Regs.PC += 3; + STO_OP (ABSX, Regs.AC); +} + + + +static void OPC_6502_9E (void) +/* Opcode $9E: SHX abs,x */ +{ + STO_OP (ABSY, Regs.XR & ((address >> 8) + 1)); +} + + + +static void OPC_6502_9F (void) +/* Opcode $9F: SHA abs,y */ +{ + STO_CB (ABSY, SHA); } @@ -1735,11 +2459,7 @@ static void OPC_6502_9D (void) static void OPC_65SC02_9E (void) /* Opcode $9E: STZ abs,x */ { - unsigned Addr; - Cycles = 5; - Addr = MemReadWord (Regs.PC+1) + Regs.XR; - MemWriteByte (Addr, 0); - Regs.PC += 3; + STO_OP (ABSX, 0); } @@ -1747,11 +2467,7 @@ static void OPC_65SC02_9E (void) static void OPC_6502_A0 (void) /* Opcode $A0: LDY #imm */ { - Cycles = 2; - Regs.YR = MemReadByte (Regs.PC+1); - TEST_ZF (Regs.YR); - TEST_SF (Regs.YR); - Regs.PC += 2; + ALU_OP_IMM (LDY); } @@ -1759,15 +2475,7 @@ static void OPC_6502_A0 (void) static void OPC_6502_A1 (void) /* Opcode $A1: LDA (zp,x) */ { - unsigned char ZPAddr; - unsigned Addr; - Cycles = 6; - ZPAddr = MemReadByte (Regs.PC+1) + Regs.XR; - Addr = MemReadZPWord (ZPAddr); - Regs.AC = MemReadByte (Addr); - TEST_ZF (Regs.AC); - TEST_SF (Regs.AC); - Regs.PC += 2; + ALU_OP (ZPXIND, LDA); } @@ -1775,11 +2483,15 @@ static void OPC_6502_A1 (void) static void OPC_6502_A2 (void) /* Opcode $A2: LDX #imm */ { - Cycles = 2; - Regs.XR = MemReadByte (Regs.PC+1); - TEST_ZF (Regs.XR); - TEST_SF (Regs.XR); - Regs.PC += 2; + ALU_OP_IMM (LDX); +} + + + +static void OPC_6502_A3 (void) +/* Opcode $A3: LAX (zp,x) */ +{ + ALU_OP (ZPXIND, LAX); } @@ -1787,13 +2499,7 @@ static void OPC_6502_A2 (void) static void OPC_6502_A4 (void) /* Opcode $A4: LDY zp */ { - unsigned char ZPAddr; - Cycles = 3; - ZPAddr = MemReadByte (Regs.PC+1); - Regs.YR = MemReadByte (ZPAddr); - TEST_ZF (Regs.YR); - TEST_SF (Regs.YR); - Regs.PC += 2; + ALU_OP (ZP, LDY); } @@ -1801,13 +2507,7 @@ static void OPC_6502_A4 (void) static void OPC_6502_A5 (void) /* Opcode $A5: LDA zp */ { - unsigned char ZPAddr; - Cycles = 3; - ZPAddr = MemReadByte (Regs.PC+1); - Regs.AC = MemReadByte (ZPAddr); - TEST_ZF (Regs.AC); - TEST_SF (Regs.AC); - Regs.PC += 2; + ALU_OP (ZP, LDA); } @@ -1815,13 +2515,15 @@ static void OPC_6502_A5 (void) static void OPC_6502_A6 (void) /* Opcode $A6: LDX zp */ { - unsigned char ZPAddr; - Cycles = 3; - ZPAddr = MemReadByte (Regs.PC+1); - Regs.XR = MemReadByte (ZPAddr); - TEST_ZF (Regs.XR); - TEST_SF (Regs.XR); - Regs.PC += 2; + ALU_OP (ZP, LDX); +} + + + +static void OPC_6502_A7 (void) +/* Opcode $A7: LAX zp */ +{ + ALU_OP (ZP, LAX); } @@ -1841,11 +2543,7 @@ static void OPC_6502_A8 (void) static void OPC_6502_A9 (void) /* Opcode $A9: LDA #imm */ { - Cycles = 2; - Regs.AC = MemReadByte (Regs.PC+1); - TEST_ZF (Regs.AC); - TEST_SF (Regs.AC); - Regs.PC += 2; + ALU_OP_IMM (LDA); } @@ -1862,16 +2560,18 @@ static void OPC_6502_AA (void) +static void OPC_6502_AB (void) +/* Opcode $AB: LXA imm */ +{ + ALU_OP_IMM (LXA); +} + + + static void OPC_6502_AC (void) /* Opcode $Regs.AC: LDY abs */ { - unsigned Addr; - Cycles = 4; - Addr = MemReadWord (Regs.PC+1); - Regs.YR = MemReadByte (Addr); - TEST_ZF (Regs.YR); - TEST_SF (Regs.YR); - Regs.PC += 3; + ALU_OP (ABS, LDY); } @@ -1879,13 +2579,7 @@ static void OPC_6502_AC (void) static void OPC_6502_AD (void) /* Opcode $AD: LDA abs */ { - unsigned Addr; - Cycles = 4; - Addr = MemReadWord (Regs.PC+1); - Regs.AC = MemReadByte (Addr); - TEST_ZF (Regs.AC); - TEST_SF (Regs.AC); - Regs.PC += 3; + ALU_OP (ABS, LDA); } @@ -1893,13 +2587,15 @@ static void OPC_6502_AD (void) static void OPC_6502_AE (void) /* Opcode $AE: LDX abs */ { - unsigned Addr; - Cycles = 4; - Addr = MemReadWord (Regs.PC+1); - Regs.XR = MemReadByte (Addr); - TEST_ZF (Regs.XR); - TEST_SF (Regs.XR); - Regs.PC += 3; + ALU_OP (ABS, LDX); +} + + + +static void OPC_6502_AF (void) +/* Opcode $AF: LAX abs */ +{ + ALU_OP (ABS, LAX); } @@ -1915,18 +2611,7 @@ static void OPC_6502_B0 (void) static void OPC_6502_B1 (void) /* Opcode $B1: LDA (zp),y */ { - unsigned char ZPAddr; - unsigned Addr; - Cycles = 5; - ZPAddr = MemReadByte (Regs.PC+1); - Addr = MemReadZPWord (ZPAddr); - if (PAGE_CROSS (Addr, Regs.YR)) { - ++Cycles; - } - Regs.AC = MemReadByte (Addr + Regs.YR); - TEST_ZF (Regs.AC); - TEST_SF (Regs.AC); - Regs.PC += 2; + ALU_OP (ZPINDY, LDA); } @@ -1934,15 +2619,15 @@ static void OPC_6502_B1 (void) static void OPC_65SC02_B2 (void) /* Opcode $B2: LDA (zp) */ { - unsigned char ZPAddr; - unsigned Addr; - Cycles = 5; - ZPAddr = MemReadByte (Regs.PC+1); - Addr = MemReadZPWord (ZPAddr); - Regs.AC = MemReadByte (Addr); - TEST_ZF (Regs.AC); - TEST_SF (Regs.AC); - Regs.PC += 2; + ALU_OP (ZPIND, LDA); +} + + + +static void OPC_6502_B3 (void) +/* Opcode $B3: LAX (zp),y */ +{ + ALU_OP (ZPINDY, LAX); } @@ -1950,13 +2635,7 @@ static void OPC_65SC02_B2 (void) static void OPC_6502_B4 (void) /* Opcode $B4: LDY zp,x */ { - unsigned char ZPAddr; - Cycles = 4; - ZPAddr = MemReadByte (Regs.PC+1) + Regs.XR; - Regs.YR = MemReadByte (ZPAddr); - TEST_ZF (Regs.YR); - TEST_SF (Regs.YR); - Regs.PC += 2; + ALU_OP (ZPX, LDY); } @@ -1964,13 +2643,7 @@ static void OPC_6502_B4 (void) static void OPC_6502_B5 (void) /* Opcode $B5: LDA zp,x */ { - unsigned char ZPAddr; - Cycles = 4; - ZPAddr = MemReadByte (Regs.PC+1) + Regs.XR; - Regs.AC = MemReadByte (ZPAddr); - TEST_ZF (Regs.AC); - TEST_SF (Regs.AC); - Regs.PC += 2; + ALU_OP (ZPX, LDA); } @@ -1978,13 +2651,15 @@ static void OPC_6502_B5 (void) static void OPC_6502_B6 (void) /* Opcode $B6: LDX zp,y */ { - unsigned char ZPAddr; - Cycles = 4; - ZPAddr = MemReadByte (Regs.PC+1) + Regs.YR; - Regs.XR = MemReadByte (ZPAddr); - TEST_ZF (Regs.XR); - TEST_SF (Regs.XR); - Regs.PC += 2; + ALU_OP (ZPY, LDX); +} + + + +static void OPC_6502_B7 (void) +/* Opcode $B7: LAX zp,y */ +{ + ALU_OP (ZPY, LAX); } @@ -2002,16 +2677,7 @@ static void OPC_6502_B8 (void) static void OPC_6502_B9 (void) /* Opcode $B9: LDA abs,y */ { - unsigned Addr; - Cycles = 4; - Addr = MemReadWord (Regs.PC+1); - if (PAGE_CROSS (Addr, Regs.YR)) { - ++Cycles; - } - Regs.AC = MemReadByte (Addr + Regs.YR); - TEST_ZF (Regs.AC); - TEST_SF (Regs.AC); - Regs.PC += 3; + ALU_OP (ABSY, LDA); } @@ -2028,19 +2694,18 @@ static void OPC_6502_BA (void) +static void OPC_6502_BB (void) +/* Opcode $BB: LAS abs,y */ +{ + ALU_OP (ABSY, LAS); +} + + + static void OPC_6502_BC (void) /* Opcode $BC: LDY abs,x */ { - unsigned Addr; - Cycles = 4; - Addr = MemReadWord (Regs.PC+1); - if (PAGE_CROSS (Addr, Regs.XR)) { - ++Cycles; - } - Regs.YR = MemReadByte (Addr + Regs.XR); - TEST_ZF (Regs.YR); - TEST_SF (Regs.YR); - Regs.PC += 3; + ALU_OP (ABSX, LDY); } @@ -2048,16 +2713,7 @@ static void OPC_6502_BC (void) static void OPC_6502_BD (void) /* Opcode $BD: LDA abs,x */ { - unsigned Addr; - Cycles = 4; - Addr = MemReadWord (Regs.PC+1); - if (PAGE_CROSS (Addr, Regs.XR)) { - ++Cycles; - } - Regs.AC = MemReadByte (Addr + Regs.XR); - TEST_ZF (Regs.AC); - TEST_SF (Regs.AC); - Regs.PC += 3; + ALU_OP (ABSX, LDA); } @@ -2065,16 +2721,15 @@ static void OPC_6502_BD (void) static void OPC_6502_BE (void) /* Opcode $BE: LDX abs,y */ { - unsigned Addr; - Cycles = 4; - Addr = MemReadWord (Regs.PC+1); - if (PAGE_CROSS (Addr, Regs.YR)) { - ++Cycles; - } - Regs.XR = MemReadByte (Addr + Regs.YR); - TEST_ZF (Regs.XR); - TEST_SF (Regs.XR); - Regs.PC += 3; + ALU_OP (ABSY, LDX); +} + + + +static void OPC_6502_BF (void) +/* Opcode $BF: LAX abs,y */ +{ + ALU_OP (ABSY, LAX); } @@ -2082,9 +2737,7 @@ static void OPC_6502_BE (void) static void OPC_6502_C0 (void) /* Opcode $C0: CPY #imm */ { - Cycles = 2; - CMP (Regs.YR, MemReadByte (Regs.PC+1)); - Regs.PC += 2; + ALU_OP_IMM (CPY); } @@ -2092,13 +2745,15 @@ static void OPC_6502_C0 (void) static void OPC_6502_C1 (void) /* Opcode $C1: CMP (zp,x) */ { - unsigned char ZPAddr; - unsigned Addr; - Cycles = 6; - ZPAddr = MemReadByte (Regs.PC+1) + Regs.XR; - Addr = MemReadZPWord (ZPAddr); - CMP (Regs.AC, MemReadByte (Addr)); - Regs.PC += 2; + ALU_OP (ZPXIND, CMP); +} + + + +static void OPC_6502_C3 (void) +/* Opcode $C3: DCP (zp,x) */ +{ + MEM_OP (ZPXIND, DCP); } @@ -2106,11 +2761,7 @@ static void OPC_6502_C1 (void) static void OPC_6502_C4 (void) /* Opcode $C4: CPY zp */ { - unsigned char ZPAddr; - Cycles = 3; - ZPAddr = MemReadByte (Regs.PC+1); - CMP (Regs.YR, MemReadByte (ZPAddr)); - Regs.PC += 2; + ALU_OP (ZP, CPY); } @@ -2118,11 +2769,7 @@ static void OPC_6502_C4 (void) static void OPC_6502_C5 (void) /* Opcode $C5: CMP zp */ { - unsigned char ZPAddr; - Cycles = 3; - ZPAddr = MemReadByte (Regs.PC+1); - CMP (Regs.AC, MemReadByte (ZPAddr)); - Regs.PC += 2; + ALU_OP (ZP, CMP); } @@ -2130,15 +2777,15 @@ static void OPC_6502_C5 (void) static void OPC_6502_C6 (void) /* Opcode $C6: DEC zp */ { - unsigned char ZPAddr; - unsigned char Val; - Cycles = 5; - ZPAddr = MemReadByte (Regs.PC+1); - Val = MemReadByte (ZPAddr) - 1; - MemWriteByte (ZPAddr, Val); - TEST_ZF (Val); - TEST_SF (Val); - Regs.PC += 2; + MEM_OP (ZP, DEC); +} + + + +static void OPC_6502_C7 (void) +/* Opcode $C7: DCP zp */ +{ + MEM_OP (ZP, DCP); } @@ -2147,9 +2794,7 @@ static void OPC_6502_C8 (void) /* Opcode $C8: INY */ { Cycles = 2; - Regs.YR = (Regs.YR + 1) & 0xFF; - TEST_ZF (Regs.YR); - TEST_SF (Regs.YR); + INC(Regs.YR); Regs.PC += 1; } @@ -2158,9 +2803,7 @@ static void OPC_6502_C8 (void) static void OPC_6502_C9 (void) /* Opcode $C9: CMP #imm */ { - Cycles = 2; - CMP (Regs.AC, MemReadByte (Regs.PC+1)); - Regs.PC += 2; + ALU_OP_IMM (CMP); } @@ -2169,22 +2812,24 @@ static void OPC_6502_CA (void) /* Opcode $CA: DEX */ { Cycles = 2; - Regs.XR = (Regs.XR - 1) & 0xFF; - TEST_ZF (Regs.XR); - TEST_SF (Regs.XR); + DEC (Regs.XR); Regs.PC += 1; } +static void OPC_6502_CB (void) +/* Opcode $CB: SBX imm */ +{ + ALU_OP_IMM (SBX); +} + + + static void OPC_6502_CC (void) /* Opcode $CC: CPY abs */ { - unsigned Addr; - Cycles = 4; - Addr = MemReadWord (Regs.PC+1); - CMP (Regs.YR, MemReadByte (Addr)); - Regs.PC += 3; + ALU_OP (ABS, CPY); } @@ -2192,11 +2837,7 @@ static void OPC_6502_CC (void) static void OPC_6502_CD (void) /* Opcode $CD: CMP abs */ { - unsigned Addr; - Cycles = 4; - Addr = MemReadWord (Regs.PC+1); - CMP (Regs.AC, MemReadByte (Addr)); - Regs.PC += 3; + ALU_OP (ABS, CMP); } @@ -2204,15 +2845,15 @@ static void OPC_6502_CD (void) static void OPC_6502_CE (void) /* Opcode $CE: DEC abs */ { - unsigned Addr; - unsigned char Val; - Cycles = 6; - Addr = MemReadWord (Regs.PC+1); - Val = MemReadByte (Addr) - 1; - MemWriteByte (Addr, Val); - TEST_ZF (Val); - TEST_SF (Val); - Regs.PC += 3; + MEM_OP (ABS, DEC); +} + + + +static void OPC_6502_CF (void) +/* Opcode $CF: DCP abs */ +{ + MEM_OP (ABS, DCP); } @@ -2228,16 +2869,7 @@ static void OPC_6502_D0 (void) static void OPC_6502_D1 (void) /* Opcode $D1: CMP (zp),y */ { - unsigned ZPAddr; - unsigned Addr; - Cycles = 5; - ZPAddr = MemReadByte (Regs.PC+1); - Addr = MemReadWord (ZPAddr); - if (PAGE_CROSS (Addr, Regs.YR)) { - ++Cycles; - } - CMP (Regs.AC, MemReadByte (Addr + Regs.YR)); - Regs.PC += 2; + ALU_OP (ZPINDY, CMP); } @@ -2245,13 +2877,15 @@ static void OPC_6502_D1 (void) static void OPC_65SC02_D2 (void) /* Opcode $D2: CMP (zp) */ { - unsigned ZPAddr; - unsigned Addr; - Cycles = 5; - ZPAddr = MemReadByte (Regs.PC+1); - Addr = MemReadWord (ZPAddr); - CMP (Regs.AC, MemReadByte (Addr)); - Regs.PC += 2; + ALU_OP (ZPIND, CMP); +} + + + +static void OPC_6502_D3 (void) +/* Opcode $D3: DCP (zp),y */ +{ + MEM_OP (ZPINDY, DCP); } @@ -2259,11 +2893,7 @@ static void OPC_65SC02_D2 (void) static void OPC_6502_D5 (void) /* Opcode $D5: CMP zp,x */ { - unsigned char ZPAddr; - Cycles = 4; - ZPAddr = MemReadByte (Regs.PC+1) + Regs.XR; - CMP (Regs.AC, MemReadByte (ZPAddr)); - Regs.PC += 2; + ALU_OP (ZPX, CMP); } @@ -2271,15 +2901,15 @@ static void OPC_6502_D5 (void) static void OPC_6502_D6 (void) /* Opcode $D6: DEC zp,x */ { - unsigned char ZPAddr; - unsigned char Val; - Cycles = 6; - ZPAddr = MemReadByte (Regs.PC+1) + Regs.XR; - Val = MemReadByte (ZPAddr) - 1; - MemWriteByte (ZPAddr, Val); - TEST_ZF (Val); - TEST_SF (Val); - Regs.PC += 2; + MEM_OP (ZPX, DEC); +} + + + +static void OPC_6502_D7 (void) +/* Opcode $D7: DCP zp,x */ +{ + MEM_OP (ZPX, DCP); } @@ -2297,14 +2927,7 @@ static void OPC_6502_D8 (void) static void OPC_6502_D9 (void) /* Opcode $D9: CMP abs,y */ { - unsigned Addr; - Cycles = 4; - Addr = MemReadWord (Regs.PC+1); - if (PAGE_CROSS (Addr, Regs.YR)) { - ++Cycles; - } - CMP (Regs.AC, MemReadByte (Addr + Regs.YR)); - Regs.PC += 3; + ALU_OP (ABSY, CMP); } @@ -2319,17 +2942,18 @@ static void OPC_65SC02_DA (void) +static void OPC_6502_DB (void) +/* Opcode $DB: DCP abs,y */ +{ + MEM_OP (ABSY, DCP); +} + + + static void OPC_6502_DD (void) /* Opcode $DD: CMP abs,x */ { - unsigned Addr; - Cycles = 4; - Addr = MemReadWord (Regs.PC+1); - if (PAGE_CROSS (Addr, Regs.XR)) { - ++Cycles; - } - CMP (Regs.AC, MemReadByte (Addr + Regs.XR)); - Regs.PC += 3; + ALU_OP (ABSX, CMP); } @@ -2337,15 +2961,15 @@ static void OPC_6502_DD (void) static void OPC_6502_DE (void) /* Opcode $DE: DEC abs,x */ { - unsigned Addr; - unsigned char Val; - Cycles = 7; - Addr = MemReadWord (Regs.PC+1) + Regs.XR; - Val = MemReadByte (Addr) - 1; - MemWriteByte (Addr, Val); - TEST_ZF (Val); - TEST_SF (Val); - Regs.PC += 3; + MEM_OP (ABSX, DEC); +} + + + +static void OPC_6502_DF (void) +/* Opcode $DF: DCP abs,x */ +{ + MEM_OP (ABSX, DCP); } @@ -2353,9 +2977,7 @@ static void OPC_6502_DE (void) static void OPC_6502_E0 (void) /* Opcode $E0: CPX #imm */ { - Cycles = 2; - CMP (Regs.XR, MemReadByte (Regs.PC+1)); - Regs.PC += 2; + ALU_OP_IMM (CPX); } @@ -2363,13 +2985,15 @@ static void OPC_6502_E0 (void) static void OPC_6502_E1 (void) /* Opcode $E1: SBC (zp,x) */ { - unsigned char ZPAddr; - unsigned Addr; - Cycles = 6; - ZPAddr = MemReadByte (Regs.PC+1) + Regs.XR; - Addr = MemReadZPWord (ZPAddr); - SBC (MemReadByte (Addr)); - Regs.PC += 2; + ALU_OP (ZPXIND, SBC); +} + + + +static void OPC_6502_E3 (void) +/* Opcode $E3: ISC (zp,x) */ +{ + MEM_OP (ZPXIND, ISC); } @@ -2377,11 +3001,7 @@ static void OPC_6502_E1 (void) static void OPC_6502_E4 (void) /* Opcode $E4: CPX zp */ { - unsigned char ZPAddr; - Cycles = 3; - ZPAddr = MemReadByte (Regs.PC+1); - CMP (Regs.XR, MemReadByte (ZPAddr)); - Regs.PC += 2; + ALU_OP (ZP, CPX); } @@ -2389,11 +3009,7 @@ static void OPC_6502_E4 (void) static void OPC_6502_E5 (void) /* Opcode $E5: SBC zp */ { - unsigned char ZPAddr; - Cycles = 3; - ZPAddr = MemReadByte (Regs.PC+1); - SBC (MemReadByte (ZPAddr)); - Regs.PC += 2; + ALU_OP (ZP, SBC); } @@ -2401,15 +3017,15 @@ static void OPC_6502_E5 (void) static void OPC_6502_E6 (void) /* Opcode $E6: INC zp */ { - unsigned char ZPAddr; - unsigned char Val; - Cycles = 5; - ZPAddr = MemReadByte (Regs.PC+1); - Val = MemReadByte (ZPAddr) + 1; - MemWriteByte (ZPAddr, Val); - TEST_ZF (Val); - TEST_SF (Val); - Regs.PC += 2; + MEM_OP (ZP, INC); +} + + + +static void OPC_6502_E7 (void) +/* Opcode $E7: ISC zp */ +{ + MEM_OP (ZP, ISC); } @@ -2418,24 +3034,31 @@ static void OPC_6502_E8 (void) /* Opcode $E8: INX */ { Cycles = 2; - Regs.XR = (Regs.XR + 1) & 0xFF; - TEST_ZF (Regs.XR); - TEST_SF (Regs.XR); + INC (Regs.XR); Regs.PC += 1; } +/* Aliases of opcode $EA */ +#define OPC_6502_EB OPC_6502_E9 + static void OPC_6502_E9 (void) /* Opcode $E9: SBC #imm */ { - Cycles = 2; - SBC (MemReadByte (Regs.PC+1)); - Regs.PC += 2; + ALU_OP_IMM (SBC); } +/* Aliases of opcode $EA */ +#define OPC_6502_1A OPC_6502_EA +#define OPC_6502_3A OPC_6502_EA +#define OPC_6502_5A OPC_6502_EA +#define OPC_6502_7A OPC_6502_EA +#define OPC_6502_DA OPC_6502_EA +#define OPC_6502_FA OPC_6502_EA + static void OPC_6502_EA (void) /* Opcode $EA: NOP */ { @@ -2485,11 +3108,7 @@ static void OPC_65C02_NOP34 (void) static void OPC_6502_EC (void) /* Opcode $EC: CPX abs */ { - unsigned Addr; - Cycles = 4; - Addr = MemReadWord (Regs.PC+1); - CMP (Regs.XR, MemReadByte (Addr)); - Regs.PC += 3; + ALU_OP (ABS, CPX); } @@ -2497,27 +3116,22 @@ static void OPC_6502_EC (void) static void OPC_6502_ED (void) /* Opcode $ED: SBC abs */ { - unsigned Addr; - Cycles = 4; - Addr = MemReadWord (Regs.PC+1); - SBC (MemReadByte (Addr)); - Regs.PC += 3; + ALU_OP (ABS, SBC); } - static void OPC_6502_EE (void) /* Opcode $EE: INC abs */ { - unsigned Addr; - unsigned char Val; - Cycles = 6; - Addr = MemReadWord (Regs.PC+1); - Val = MemReadByte (Addr) + 1; - MemWriteByte (Addr, Val); - TEST_ZF (Val); - TEST_SF (Val); - Regs.PC += 3; + MEM_OP (ABS, INC); +} + + + +static void OPC_6502_EF (void) +/* Opcode $EF: ISC abs */ +{ + MEM_OP (ABS, ISC); } @@ -2533,16 +3147,7 @@ static void OPC_6502_F0 (void) static void OPC_6502_F1 (void) /* Opcode $F1: SBC (zp),y */ { - unsigned char ZPAddr; - unsigned Addr; - Cycles = 5; - ZPAddr = MemReadByte (Regs.PC+1); - Addr = MemReadZPWord (ZPAddr); - if (PAGE_CROSS (Addr, Regs.YR)) { - ++Cycles; - } - SBC (MemReadByte (Addr + Regs.YR)); - Regs.PC += 2; + ALU_OP (ZPINDY, SBC); } @@ -2550,13 +3155,15 @@ static void OPC_6502_F1 (void) static void OPC_65SC02_F2 (void) /* Opcode $F2: SBC (zp) */ { - unsigned char ZPAddr; - unsigned Addr; - Cycles = 5; - ZPAddr = MemReadByte (Regs.PC+1); - Addr = MemReadZPWord (ZPAddr); - SBC (MemReadByte (Addr)); - Regs.PC += 2; + ALU_OP (ZPIND, SBC); +} + + + +static void OPC_6502_F3 (void) +/* Opcode $F3: ISC (zp),y */ +{ + MEM_OP (ZPINDY, ISC); } @@ -2564,11 +3171,7 @@ static void OPC_65SC02_F2 (void) static void OPC_6502_F5 (void) /* Opcode $F5: SBC zp,x */ { - unsigned char ZPAddr; - Cycles = 4; - ZPAddr = MemReadByte (Regs.PC+1) + Regs.XR; - SBC (MemReadByte (ZPAddr)); - Regs.PC += 2; + ALU_OP (ZPX, SBC); } @@ -2576,15 +3179,15 @@ static void OPC_6502_F5 (void) static void OPC_6502_F6 (void) /* Opcode $F6: INC zp,x */ { - unsigned char ZPAddr; - unsigned char Val; - Cycles = 6; - ZPAddr = MemReadByte (Regs.PC+1) + Regs.XR; - Val = MemReadByte (ZPAddr) + 1; - MemWriteByte (ZPAddr, Val); - TEST_ZF (Val); - TEST_SF (Val); - Regs.PC += 2; + MEM_OP (ZPX, INC); +} + + + +static void OPC_6502_F7 (void) +/* Opcode $F7: ISC zp,x */ +{ + MEM_OP (ZPX, ISC); } @@ -2602,14 +3205,7 @@ static void OPC_6502_F8 (void) static void OPC_6502_F9 (void) /* Opcode $F9: SBC abs,y */ { - unsigned Addr; - Cycles = 4; - Addr = MemReadWord (Regs.PC+1); - if (PAGE_CROSS (Addr, Regs.YR)) { - ++Cycles; - } - SBC (MemReadByte (Addr + Regs.YR)); - Regs.PC += 3; + ALU_OP (ABSY, SBC); } @@ -2626,17 +3222,18 @@ static void OPC_65SC02_FA (void) +static void OPC_6502_FB (void) +/* Opcode $FB: ISC abs,y */ +{ + MEM_OP (ABSY, ISC); +} + + + static void OPC_6502_FD (void) /* Opcode $FD: SBC abs,x */ { - unsigned Addr; - Cycles = 4; - Addr = MemReadWord (Regs.PC+1); - if (PAGE_CROSS (Addr, Regs.XR)) { - ++Cycles; - } - SBC (MemReadByte (Addr + Regs.XR)); - Regs.PC += 3; + ALU_OP (ABSX, SBC); } @@ -2644,15 +3241,15 @@ static void OPC_6502_FD (void) static void OPC_6502_FE (void) /* Opcode $FE: INC abs,x */ { - unsigned Addr; - unsigned char Val; - Cycles = 7; - Addr = MemReadWord (Regs.PC+1) + Regs.XR; - Val = MemReadByte (Addr) + 1; - MemWriteByte (Addr, Val); - TEST_ZF (Val); - TEST_SF (Val); - Regs.PC += 3; + MEM_OP (ABSX, INC); +} + + + +static void OPC_6502_FF (void) +/* Opcode $FF: ISC abs,x */ +{ + MEM_OP (ABSX, ISC); } @@ -2925,6 +3522,268 @@ static const OPFunc OP6502Table[256] = { +/* Opcode handler table for the 6502X */ +static const OPFunc OP6502XTable[256] = { + OPC_6502_00, + OPC_6502_01, + OPC_Illegal, + OPC_6502_03, + OPC_6502_04, + OPC_6502_05, + OPC_6502_06, + OPC_6502_07, + OPC_6502_08, + OPC_6502_09, + OPC_6502_0A, + OPC_6502_0B, + OPC_6502_0C, + OPC_6502_0D, + OPC_6502_0E, + OPC_6502_0F, + OPC_6502_10, + OPC_6502_11, + OPC_Illegal, + OPC_6502_13, + OPC_6502_14, + OPC_6502_15, + OPC_6502_16, + OPC_6502_17, + OPC_6502_18, + OPC_6502_19, + OPC_6502_1A, + OPC_6502_1B, + OPC_6502_1C, + OPC_6502_1D, + OPC_6502_1E, + OPC_6502_1F, + OPC_6502_20, + OPC_6502_21, + OPC_Illegal, + OPC_6502_23, + OPC_6502_24, + OPC_6502_25, + OPC_6502_26, + OPC_6502_27, + OPC_6502_28, + OPC_6502_29, + OPC_6502_2A, + OPC_6502_2B, + OPC_6502_2C, + OPC_6502_2D, + OPC_6502_2E, + OPC_6502_2F, + OPC_6502_30, + OPC_6502_31, + OPC_Illegal, + OPC_6502_33, + OPC_6502_34, + OPC_6502_35, + OPC_6502_36, + OPC_6502_37, + OPC_6502_38, + OPC_6502_39, + OPC_6502_3A, + OPC_6502_3B, + OPC_6502_3C, + OPC_6502_3D, + OPC_6502_3E, + OPC_6502_3F, + OPC_6502_40, + OPC_6502_41, + OPC_Illegal, + OPC_6502_43, + OPC_6502_44, + OPC_6502_45, + OPC_6502_46, + OPC_6502_47, + OPC_6502_48, + OPC_6502_49, + OPC_6502_4A, + OPC_6502_4B, + OPC_6502_4C, + OPC_6502_4D, + OPC_6502_4E, + OPC_6502_4F, + OPC_6502_50, + OPC_6502_51, + OPC_Illegal, + OPC_6502_53, + OPC_6502_54, + OPC_6502_55, + OPC_6502_56, + OPC_6502_57, + OPC_6502_58, + OPC_6502_59, + OPC_6502_5A, + OPC_6502_5B, + OPC_6502_5C, + OPC_6502_5D, + OPC_6502_5E, + OPC_6502_5F, + OPC_6502_60, + OPC_6502_61, + OPC_Illegal, + OPC_6502_63, + OPC_6502_64, + OPC_6502_65, + OPC_6502_66, + OPC_6502_67, + OPC_6502_68, + OPC_6502_69, + OPC_6502_6A, + OPC_6502_6B, + OPC_6502_6C, + OPC_6502_6D, + OPC_6502_6E, + OPC_6502_6F, + OPC_6502_70, + OPC_6502_71, + OPC_Illegal, + OPC_6502_73, + OPC_6502_74, + OPC_6502_75, + OPC_6502_76, + OPC_6502_77, + OPC_6502_78, + OPC_6502_79, + OPC_6502_7A, + OPC_6502_7B, + OPC_6502_7C, + OPC_6502_7D, + OPC_6502_7E, + OPC_6502_7F, + OPC_6502_80, + OPC_6502_81, + OPC_6502_82, + OPC_6502_83, + OPC_6502_84, + OPC_6502_85, + OPC_6502_86, + OPC_6502_87, + OPC_6502_88, + OPC_6502_89, + OPC_6502_8A, + OPC_6502_8B, + OPC_6502_8C, + OPC_6502_8D, + OPC_6502_8E, + OPC_6502_8F, + OPC_6502_90, + OPC_6502_91, + OPC_Illegal, + OPC_6502_93, + OPC_6502_94, + OPC_6502_95, + OPC_6502_96, + OPC_6502_97, + OPC_6502_98, + OPC_6502_99, + OPC_6502_9A, + OPC_6502_9B, + OPC_6502_9C, + OPC_6502_9D, + OPC_6502_9E, + OPC_6502_9F, + OPC_6502_A0, + OPC_6502_A1, + OPC_6502_A2, + OPC_6502_A3, + OPC_6502_A4, + OPC_6502_A5, + OPC_6502_A6, + OPC_6502_A7, + OPC_6502_A8, + OPC_6502_A9, + OPC_6502_AA, + OPC_6502_AB, + OPC_6502_AC, + OPC_6502_AD, + OPC_6502_AE, + OPC_6502_AF, + OPC_6502_B0, + OPC_6502_B1, + OPC_Illegal, + OPC_6502_B3, + OPC_6502_B4, + OPC_6502_B5, + OPC_6502_B6, + OPC_6502_B7, + OPC_6502_B8, + OPC_6502_B9, + OPC_6502_BA, + OPC_6502_BB, + OPC_6502_BC, + OPC_6502_BD, + OPC_6502_BE, + OPC_6502_BF, + OPC_6502_C0, + OPC_6502_C1, + OPC_6502_C2, + OPC_6502_C3, + OPC_6502_C4, + OPC_6502_C5, + OPC_6502_C6, + OPC_6502_C7, + OPC_6502_C8, + OPC_6502_C9, + OPC_6502_CA, + OPC_6502_CB, + OPC_6502_CC, + OPC_6502_CD, + OPC_6502_CE, + OPC_6502_CF, + OPC_6502_D0, + OPC_6502_D1, + OPC_Illegal, + OPC_6502_D3, + OPC_6502_D4, + OPC_6502_D5, + OPC_6502_D6, + OPC_6502_D7, + OPC_6502_D8, + OPC_6502_D9, + OPC_6502_DA, + OPC_6502_DB, + OPC_6502_DC, + OPC_6502_DD, + OPC_6502_DE, + OPC_6502_DF, + OPC_6502_E0, + OPC_6502_E1, + OPC_6502_E2, + OPC_6502_E3, + OPC_6502_E4, + OPC_6502_E5, + OPC_6502_E6, + OPC_6502_E7, + OPC_6502_E8, + OPC_6502_E9, + OPC_6502_EA, + OPC_6502_EB, + OPC_6502_EC, + OPC_6502_ED, + OPC_6502_EE, + OPC_6502_EF, + OPC_6502_F0, + OPC_6502_F1, + OPC_Illegal, + OPC_6502_F3, + OPC_6502_F4, + OPC_6502_F5, + OPC_6502_F6, + OPC_6502_F7, + OPC_6502_F8, + OPC_6502_F9, + OPC_6502_FA, + OPC_6502_FB, + OPC_6502_FC, + OPC_6502_FD, + OPC_6502_FE, + OPC_6502_FF +}; + + + /* Opcode handler table for the 65C02 */ static const OPFunc OP65C02Table[256] = { OPC_6502_00, @@ -2957,7 +3816,7 @@ static const OPFunc OP65C02Table[256] = { OPC_65C02_NOP11, // $1B OPC_65SC02_1C, OPC_6502_1D, - OPC_6502_1E, + OPC_65C02_1E, OPC_Illegal, // $1F: BBR1 currently unsupported OPC_6502_20, OPC_6502_21, @@ -2989,13 +3848,13 @@ static const OPFunc OP65C02Table[256] = { OPC_65C02_NOP11, // $3B OPC_65SC02_3C, OPC_6502_3D, - OPC_6502_3E, + OPC_65C02_3E, OPC_Illegal, // $3F: BBR3 currently unsupported OPC_6502_40, OPC_6502_41, OPC_65C02_NOP22, // $42 OPC_65C02_NOP11, // $43 - OPC_65C02_44, // $44 + OPC_6502_44, // $44 OPC_6502_45, OPC_6502_46, OPC_Illegal, // $47: RMB4 currently unsupported @@ -3021,7 +3880,7 @@ static const OPFunc OP65C02Table[256] = { OPC_65C02_NOP11, // $5B OPC_65C02_5C, OPC_6502_5D, - OPC_6502_5E, + OPC_65C02_5E, OPC_Illegal, // $5F: BBR5 currently unsupported OPC_6502_60, OPC_6502_61, @@ -3053,7 +3912,7 @@ static const OPFunc OP65C02Table[256] = { OPC_65C02_NOP11, // $7B OPC_65SC02_7C, OPC_6502_7D, - OPC_6502_7E, + OPC_65C02_7E, OPC_Illegal, // $7F: BBR7 currently unsupported OPC_65SC02_80, OPC_6502_81, @@ -3188,7 +4047,11 @@ static const OPFunc OP65C02Table[256] = { /* Tables with opcode handlers */ -static const OPFunc* Handlers[2] = {OP6502Table, OP65C02Table}; +static const OPFunc* Handlers[3] = { + OP6502Table, + OP65C02Table, + OP6502XTable +}; diff --git a/src/sim65/6502.h b/src/sim65/6502.h index 39b995793..a7a702521 100644 --- a/src/sim65/6502.h +++ b/src/sim65/6502.h @@ -47,7 +47,8 @@ /* Supported CPUs */ typedef enum CPUType { CPU_6502, - CPU_65C02 + CPU_65C02, + CPU_6502X } CPUType; /* Current CPU */ diff --git a/src/sim65/main.c b/src/sim65/main.c index 3c7cdc157..76c912c6b 100644 --- a/src/sim65/main.c +++ b/src/sim65/main.c @@ -177,10 +177,16 @@ static unsigned char ReadProgramFile (void) /* Get the CPU type from the file header */ if ((Val = fgetc(F)) != EOF) { - if (Val != CPU_6502 && Val != CPU_65C02) { + switch (Val) { + case CPU_6502: + case CPU_65C02: + case CPU_6502X: + CPU = Val; + break; + + default: Error ("'%s': Invalid CPU type", ProgramFile); } - CPU = Val; } /* Get the address of sp from the file header */ From 788ae82d30bcf29da0e160cd47532594780fe22b Mon Sep 17 00:00:00 2001 From: Alex Thissen Date: Fri, 9 Feb 2024 00:09:16 +0000 Subject: [PATCH 02/21] Fixes to serial driver implementation --- asminc/lynx.inc | 34 +++++++------- libsrc/lynx/crt0.s | 2 +- libsrc/lynx/ser/lynx-comlynx.s | 81 ++++++++++++++++++++-------------- 3 files changed, 67 insertions(+), 50 deletions(-) diff --git a/asminc/lynx.inc b/asminc/lynx.inc index 5ae17f6ef..d65b7f8a9 100644 --- a/asminc/lynx.inc +++ b/asminc/lynx.inc @@ -267,22 +267,26 @@ MIKEYHREV = $FD88 MIKEYSREV = $FD89 IODIR = $FD8A IODAT = $FD8B -TxIntEnable = %10000000 -RxIntEnable = %01000000 -TxParEnable = %00010000 -ResetErr = %00001000 -TxOpenColl = %00000100 -TxBreak = %00000010 -ParEven = %00000001 -TxReady = %10000000 -RxReady = %01000000 -TxEmpty = %00100000 -RxParityErr = %00010000 -RxOverrun = %00001000 -RxFrameErr = %00000100 -RxBreak = %00000010 -ParityBit = %00000001 + SERCTL = $FD8C +; SERCTL bit definitions for write operations +TXINTEN = $80 +RXINTEN = $40 +PAREN = $10 +RESETERR = $08 +TXOPEN = $04 +TXBRK = $02 +PAREVEN = $01 +; SERCTL bit definitions for read operations +TXRDY = $80 +RXRDY = $40 +TXEMPTY = $20 +PARERR = $10 +OVERRUN = $08 +FRAMERR = $04 +RXBRK = $02 +PARBIT = $01 + SERDAT = $FD8D SDONEACK = $FD90 CPUSLEEP = $FD91 diff --git a/libsrc/lynx/crt0.s b/libsrc/lynx/crt0.s index 238a2c99d..030f523e9 100644 --- a/libsrc/lynx/crt0.s +++ b/libsrc/lynx/crt0.s @@ -68,7 +68,7 @@ MikeyInitData: .byte $9e,$18,$68,$1f,$00,$00,$00,$00,$00,$ff,$1a,$1b,$04,$0d,$2 ; Disable the TX/RX IRQ; set to 8E1. - lda #%00011101 + lda #PAREN|RESETERR|TXOPEN|PAREVEN ; #%00011101 sta SERCTL ; Clear all pending interrupts. diff --git a/libsrc/lynx/ser/lynx-comlynx.s b/libsrc/lynx/ser/lynx-comlynx.s index 8aa3c838e..85703867b 100644 --- a/libsrc/lynx/ser/lynx-comlynx.s +++ b/libsrc/lynx/ser/lynx-comlynx.s @@ -73,7 +73,12 @@ SER_UNINSTALL: ; Must return an SER_ERR_xx code in a/x. SER_CLOSE: - ; Disable interrupts + ; Disable interrupts and stop timer 4 (serial) + lda #$0C ; TXOPEN|RESETERR + sta SERCTL + lda #$00 ; Disable count and no reload + sta TIM4CTLA + ; Done, return an error code lda #SER_ERR_OK .assert SER_ERR_OK = 0, error @@ -108,7 +113,7 @@ SER_OPEN: stz TxPtrIn stz TxPtrOut - ; clock = 8 * 15625 + ; source period is 1 us lda #%00011000 sta TIM4CTLA ldy #SER_PARAMS::BAUDRATE @@ -118,7 +123,7 @@ SER_OPEN: cmp #SER_BAUD_62500 beq setbaudrate - ldx #2 + ldx #3 cmp #SER_BAUD_31250 beq setbaudrate @@ -194,13 +199,14 @@ SER_OPEN: lda #SER_ERR_BAUD_UNAVAIL ldx #0 ; return value is char rts + setprescaler: stx TIM4CTLA bra baudsuccess setbaudrate: stx TIM4BKUP baudsuccess: - ldx #TxOpenColl|ParEven + ldx #TXOPEN|PAREVEN stx contrl ldy #SER_PARAMS::DATABITS ; Databits lda (ptr1),y @@ -218,15 +224,15 @@ baudsuccess: beq checkhs cmp #SER_PAR_SPACE bne @L0 - ldx #TxOpenColl + ldx #TXOPEN stx contrl bra checkhs @L0: - ldx #TxParEnable|TxOpenColl|ParEven + ldx #PAREN|TXOPEN|PAREVEN stx contrl cmp #SER_PAR_EVEN beq checkhs - ldx #TxParEnable|TxOpenColl + ldx #PAREN|TXOPEN stx contrl checkhs: ldx contrl @@ -237,7 +243,7 @@ checkhs: bne invparameter lda SERDAT lda contrl - ora #RxIntEnable|ResetErr + ora #RXINTEN|RESETERR ; Turn on interrupts for receive sta SERCTL lda #SER_ERR_OK .assert SER_ERR_OK = 0, error @@ -279,24 +285,26 @@ SER_PUT: ina cmp TxPtrOut bne PutByte + lda #SER_ERR_OVERFLOW ldx #0 ; return value is char rts + PutByte: ldy TxPtrIn txa sta TxBuffer,y inc TxPtrIn - bit TxDone - bmi @L1 + bit TxDone ; Check bit 7 of TxDone (TXINTEN) + bmi @L1 ; Was TXINTEN already set? php sei - lda contrl - ora #TxIntEnable|ResetErr - sta SERCTL ; Allow TX-IRQ to hang RX-IRQ + lda contrl ; contrl does not include RXINTEN setting + ora #TXINTEN|RESETERR + sta SERCTL ; Allow TX-IRQ to hang RX-IRQ (no receive while transmitting) sta TxDone - plp + plp ; Restore processor and interrupt enable @L1: lda #SER_ERR_OK .assert SER_ERR_OK = 0, error @@ -308,7 +316,7 @@ PutByte: ; Must return an SER_ERR_xx code in a/x. SER_STATUS: - ldy SerialStat + lda SerialStat ldx #$00 sta (ptr1,x) txa ; Return code = 0 @@ -342,27 +350,32 @@ SER_IRQ: @L0: bit TxDone bmi @tx_irq ; Transmit in progress - ldx SERDAT - lda SERCTL - and #RxParityErr|RxOverrun|RxFrameErr|RxBreak - beq @rx_irq + + ldx SERDAT ; Read received data + lda contrl + and #PAREN ; Parity enabled implies SER_PAR_EVEN or SER_PAR_ODD + ora #OVERRUN|FRAMERR|RXBRK + bit SERCTL ; Compare with SERCTL + + beq @rx_irq ; No errors so far + tsb SerialStat ; Save error condition - bit #RxBreak + bit #RXBRK ; Check for break signal beq @noBreak + stz TxPtrIn ; Break received - drop buffers stz TxPtrOut stz RxPtrIn stz RxPtrOut @noBreak: lda contrl - ora #RxIntEnable|ResetErr + ora #RXINTEN|RESETERR sta SERCTL - lda #$10 - sta INTRST bra @IRQexit + @rx_irq: lda contrl - ora #RxIntEnable|ResetErr + ora #RXINTEN|RESETERR sta SERCTL txa ldx RxPtrIn @@ -370,20 +383,22 @@ SER_IRQ: txa inx -@cont0: cpx RxPtrOut beq @1 stx RxPtrIn - lda #SERIAL_INTERRUPT - sta INTRST bra @IRQexit @1: sta RxPtrIn lda #$80 tsb SerialStat + lda contrl + ora #RXINTEN|RESETERR + sta SERCTL + bra @IRQexit + @tx_irq: - ldx TxPtrOut ; Has all bytes been sent? + ldx TxPtrOut ; Have all bytes been sent? cpx TxPtrIn beq @allSent @@ -393,24 +408,22 @@ SER_IRQ: @exit1: lda contrl - ora #TxIntEnable|ResetErr + ora #TXINTEN|RESETERR sta SERCTL - lda #SERIAL_INTERRUPT - sta INTRST bra @IRQexit @allSent: lda SERCTL ; All bytes sent - bit #TxEmpty + bit #TXEMPTY beq @exit1 bvs @exit1 stz TxDone lda contrl - ora #RxIntEnable|ResetErr + ora #RXINTEN|RESETERR ; Re-enable receive interrupt sta SERCTL +@IRQexit: lda #SERIAL_INTERRUPT sta INTRST -@IRQexit: clc rts From 014f85f226b38f434722ecc085d621e9d3d730d1 Mon Sep 17 00:00:00 2001 From: Alex Thissen Date: Fri, 9 Feb 2024 10:42:52 +0000 Subject: [PATCH 03/21] Fixed baud rates --- libsrc/lynx/ser/lynx-comlynx.s | 86 +++++++++++++--------------------- 1 file changed, 33 insertions(+), 53 deletions(-) diff --git a/libsrc/lynx/ser/lynx-comlynx.s b/libsrc/lynx/ser/lynx-comlynx.s index 85703867b..9564bcb4f 100644 --- a/libsrc/lynx/ser/lynx-comlynx.s +++ b/libsrc/lynx/ser/lynx-comlynx.s @@ -113,12 +113,12 @@ SER_OPEN: stz TxPtrIn stz TxPtrOut - ; source period is 1 us - lda #%00011000 - sta TIM4CTLA ldy #SER_PARAMS::BAUDRATE lda (ptr1),y + ; Source period is 1 us + ldy #%00011000 ; ENABLE_RELOAD|ENABLE_COUNT|AUD_1 + ldx #1 cmp #SER_BAUD_62500 beq setbaudrate @@ -139,6 +139,10 @@ SER_OPEN: cmp #SER_BAUD_2400 beq setbaudrate + ldx #68 + cmp #SER_BAUD_1800 + beq setbaudrate + ldx #103 cmp #SER_BAUD_1200 beq setbaudrate @@ -147,65 +151,48 @@ SER_OPEN: cmp #SER_BAUD_600 beq setbaudrate - ; clock = 6 * 15625 - ldx #%00011010 - stx TIM4CTLA + ; Source period is 4 us + ldy #%00011011 ; ENABLE_RELOAD|ENABLE_COUNT|AUD_8 - ldx #12 - cmp #SER_BAUD_7200 - beq setbaudrate - - ldx #25 - cmp #SER_BAUD_3600 - beq setbaudrate - - ldx #207 - stx TIM4BKUP - - ; clock = 4 * 15625 - ldx #%00011100 + ldx #51 cmp #SER_BAUD_300 - beq setprescaler + beq setbaudrate - ; clock = 6 * 15625 - ldx #%00011110 + ldx #103 cmp #SER_BAUD_150 - beq setprescaler + beq setbaudrate - ; clock = 1 * 15625 - ldx #%00011111 - stx TIM4CTLA - cmp #SER_BAUD_75 - beq baudsuccess + ldx #115 + cmp #SER_BAUD_134_5 + beq setbaudrate ldx #141 cmp #SER_BAUD_110 beq setbaudrate - ; clock = 2 * 15625 - ldx #%00011010 - stx TIM4CTLA - ldx #68 - cmp #SER_BAUD_1800 + ; Source period is 32 us + ldy #%00011101 ; ENABLE_RELOAD|ENABLE_COUNT|AUD_32 + + ldx #51 + cmp #SER_BAUD_75 beq setbaudrate - ; clock = 6 * 15625 - ldx #%00011110 - stx TIM4CTLA - ldx #231 - cmp #SER_BAUD_134_5 + ldx #68 + cmp #SER_BAUD_56_875 + beq setbaudrate + + ldx #77 + cmp #SER_BAUD_50 beq setbaudrate lda #SER_ERR_BAUD_UNAVAIL ldx #0 ; return value is char rts -setprescaler: - stx TIM4CTLA - bra baudsuccess setbaudrate: + sty TIM4CTLA stx TIM4BKUP -baudsuccess: + ldx #TXOPEN|PAREVEN stx contrl ldy #SER_PARAMS::DATABITS ; Databits @@ -368,15 +355,9 @@ SER_IRQ: stz RxPtrIn stz RxPtrOut @noBreak: - lda contrl - ora #RXINTEN|RESETERR - sta SERCTL - bra @IRQexit + bra @exit0 @rx_irq: - lda contrl - ora #RXINTEN|RESETERR - sta SERCTL txa ldx RxPtrIn sta RxBuffer,x @@ -392,10 +373,7 @@ SER_IRQ: sta RxPtrIn lda #$80 tsb SerialStat - lda contrl - ora #RXINTEN|RESETERR - sta SERCTL - bra @IRQexit + bra @exit0 @tx_irq: ldx TxPtrOut ; Have all bytes been sent? @@ -418,6 +396,8 @@ SER_IRQ: beq @exit1 bvs @exit1 stz TxDone + +@exit0: lda contrl ora #RXINTEN|RESETERR ; Re-enable receive interrupt sta SERCTL From 65bce9ecdeda7a2214a27fafa4ccbfcd5daa5449 Mon Sep 17 00:00:00 2001 From: Alex Thissen Date: Fri, 9 Feb 2024 12:54:00 +0000 Subject: [PATCH 04/21] Implemented mark and space checks. --- libsrc/lynx/ser/lynx-comlynx.s | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/libsrc/lynx/ser/lynx-comlynx.s b/libsrc/lynx/ser/lynx-comlynx.s index 9564bcb4f..3b6f18af6 100644 --- a/libsrc/lynx/ser/lynx-comlynx.s +++ b/libsrc/lynx/ser/lynx-comlynx.s @@ -151,7 +151,7 @@ SER_OPEN: cmp #SER_BAUD_600 beq setbaudrate - ; Source period is 4 us + ; Source period is 8 us ldy #%00011011 ; ENABLE_RELOAD|ENABLE_COUNT|AUD_8 ldx #51 @@ -341,8 +341,9 @@ SER_IRQ: ldx SERDAT ; Read received data lda contrl and #PAREN ; Parity enabled implies SER_PAR_EVEN or SER_PAR_ODD + tay ora #OVERRUN|FRAMERR|RXBRK - bit SERCTL ; Compare with SERCTL + bit SERCTL ; Check error flags in SERCTL beq @rx_irq ; No errors so far @@ -358,6 +359,15 @@ SER_IRQ: bra @exit0 @rx_irq: + tya + bne @2 ; Parity was enabled so no marker bit check needed + + lda contrl + eor SERCTL ; Should match current parity bit + and #PARBIT ; Check for mark or space value + bne @exit0 + +@2: txa ldx RxPtrIn sta RxBuffer,x From 6cf8ee8eb563f50ceef74605a95e202054e2991c Mon Sep 17 00:00:00 2001 From: Alex Thissen Date: Sat, 10 Feb 2024 21:15:05 +0000 Subject: [PATCH 05/21] Removed baud rates from 150 and lower. Fixed tab Replaced uploader references to SERIAL_INTERRUPT --- libsrc/lynx/ser/lynx-comlynx.s | 31 ++----------------------------- libsrc/lynx/uploader.s | 6 +++--- 2 files changed, 5 insertions(+), 32 deletions(-) diff --git a/libsrc/lynx/ser/lynx-comlynx.s b/libsrc/lynx/ser/lynx-comlynx.s index 3b6f18af6..486981184 100644 --- a/libsrc/lynx/ser/lynx-comlynx.s +++ b/libsrc/lynx/ser/lynx-comlynx.s @@ -158,33 +158,6 @@ SER_OPEN: cmp #SER_BAUD_300 beq setbaudrate - ldx #103 - cmp #SER_BAUD_150 - beq setbaudrate - - ldx #115 - cmp #SER_BAUD_134_5 - beq setbaudrate - - ldx #141 - cmp #SER_BAUD_110 - beq setbaudrate - - ; Source period is 32 us - ldy #%00011101 ; ENABLE_RELOAD|ENABLE_COUNT|AUD_32 - - ldx #51 - cmp #SER_BAUD_75 - beq setbaudrate - - ldx #68 - cmp #SER_BAUD_56_875 - beq setbaudrate - - ldx #77 - cmp #SER_BAUD_50 - beq setbaudrate - lda #SER_ERR_BAUD_UNAVAIL ldx #0 ; return value is char rts @@ -342,8 +315,8 @@ SER_IRQ: lda contrl and #PAREN ; Parity enabled implies SER_PAR_EVEN or SER_PAR_ODD tay - ora #OVERRUN|FRAMERR|RXBRK - bit SERCTL ; Check error flags in SERCTL + ora #OVERRUN|FRAMERR|RXBRK + bit SERCTL ; Check presence of relevant error flags in SERCTL beq @rx_irq ; No errors so far diff --git a/libsrc/lynx/uploader.s b/libsrc/lynx/uploader.s index df3e5df40..5ce21b489 100644 --- a/libsrc/lynx/uploader.s +++ b/libsrc/lynx/uploader.s @@ -40,14 +40,14 @@ cont1: bra loop1 read_byte: - bit SERCTL + bit SERCTL ; Check for RXRDY ($40) bvc read_byte lda SERDAT rts _UpLoaderIRQ: lda INTSET - and #$10 + and #SERIAL_INTERRUPT bne @L0 clc rts @@ -69,7 +69,7 @@ again: ; last action : clear interrupt ; exit: - lda #$10 + lda #SERIAL_INTERRUPT sta INTRST clc rts From acff429eb8788ab6f1b1e40bb8cef0ac7de94930 Mon Sep 17 00:00:00 2001 From: Alex Thissen Date: Sun, 11 Feb 2024 15:33:22 +0000 Subject: [PATCH 06/21] Added redeye check for SER_HS_SW handshake --- asminc/lynx.inc | 16 +++++++++++++--- libsrc/lynx/ser/lynx-comlynx.s | 12 ++++++++++++ 2 files changed, 25 insertions(+), 3 deletions(-) diff --git a/asminc/lynx.inc b/asminc/lynx.inc index d65b7f8a9..0d34e1c7c 100644 --- a/asminc/lynx.inc +++ b/asminc/lynx.inc @@ -259,16 +259,26 @@ SND_INTERRUPT = TIMER7_INTERRUPT INTRST = $FD80 INTSET = $FD81 + MAGRDY0 = $FD84 MAGRDY1 = $FD85 AUDIN = $FD86 SYSCTL1 = $FD87 MIKEYHREV = $FD88 MIKEYSREV = $FD89 -IODIR = $FD8A -IODAT = $FD8B -SERCTL = $FD8C +IODIR = $FD8A +IODAT = $FD8B +; IODIR and IODAT bit definitions +AUDIN_BIT = $10 ; Note that there is also the address AUDIN +READ_ENABLE = $10 ; Same bit for AUDIN_BIT +RESTLESS = $08 +NOEXP = $04 ; If set, redeye is not connected +CART_ADDR_DATA = $02 +CART_POWER_OFF = $02 ; Same bit for CART_ADDR_DATA +EXTERNAL_POWER = $01 + +SERCTL = $FD8C ; SERCTL bit definitions for write operations TXINTEN = $80 RXINTEN = $40 diff --git a/libsrc/lynx/ser/lynx-comlynx.s b/libsrc/lynx/ser/lynx-comlynx.s index 486981184..7201264b7 100644 --- a/libsrc/lynx/ser/lynx-comlynx.s +++ b/libsrc/lynx/ser/lynx-comlynx.s @@ -200,7 +200,18 @@ checkhs: ldy #SER_PARAMS::HANDSHAKE ; Handshake lda (ptr1),y cmp #SER_HS_NONE + beq redeye_ok + cmp #SER_HS_SW ; Software handshake will check for connected redeye bne invparameter + + lda IODAT + and #NOEXP ; Check if redeye bit flag is unset + beq redeye_ok + lda #SER_ERR_NO_DEVICE ; ComLynx cable is not inserted + ldx #0 + rts + +redeye_ok: lda SERDAT lda contrl ora #RXINTEN|RESETERR ; Turn on interrupts for receive @@ -209,6 +220,7 @@ checkhs: .assert SER_ERR_OK = 0, error tax rts + invparameter: lda #SER_ERR_INIT_FAILED ldx #0 ; return value is char From 1deb9e52aec938ae338168035c743b04b91e20d0 Mon Sep 17 00:00:00 2001 From: Alex Thissen Date: Sun, 11 Feb 2024 15:46:23 +0000 Subject: [PATCH 07/21] Replaced last literal value for SERCTL --- libsrc/lynx/ser/lynx-comlynx.s | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libsrc/lynx/ser/lynx-comlynx.s b/libsrc/lynx/ser/lynx-comlynx.s index 7201264b7..9b007c6e0 100644 --- a/libsrc/lynx/ser/lynx-comlynx.s +++ b/libsrc/lynx/ser/lynx-comlynx.s @@ -74,7 +74,7 @@ SER_UNINSTALL: SER_CLOSE: ; Disable interrupts and stop timer 4 (serial) - lda #$0C ; TXOPEN|RESETERR + lda #TXOPEN|RESETERR sta SERCTL lda #$00 ; Disable count and no reload sta TIM4CTLA From 8b172e05bc4c39b53ee1dd05be082c01fea0d7e0 Mon Sep 17 00:00:00 2001 From: Alex Thissen Date: Sun, 11 Feb 2024 20:59:08 +0000 Subject: [PATCH 08/21] Applied optimization as per review 42Bastian --- libsrc/lynx/ser/lynx-comlynx.s | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/libsrc/lynx/ser/lynx-comlynx.s b/libsrc/lynx/ser/lynx-comlynx.s index 9b007c6e0..aa4d71ad3 100644 --- a/libsrc/lynx/ser/lynx-comlynx.s +++ b/libsrc/lynx/ser/lynx-comlynx.s @@ -76,8 +76,7 @@ SER_CLOSE: ; Disable interrupts and stop timer 4 (serial) lda #TXOPEN|RESETERR sta SERCTL - lda #$00 ; Disable count and no reload - sta TIM4CTLA + stz TIM4CTLA ; Disable count and no reload ; Done, return an error code lda #SER_ERR_OK From 7d6f3d24d434953679c176708c67a0abc845eaa0 Mon Sep 17 00:00:00 2001 From: Alex Thissen Date: Sun, 11 Feb 2024 23:12:27 +0000 Subject: [PATCH 09/21] Changed sta (ptr1,x) to sta (ptr1) Reset serial status on ser_close Fixed error for saving serial state --- libsrc/lynx/ser/lynx-comlynx.s | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/libsrc/lynx/ser/lynx-comlynx.s b/libsrc/lynx/ser/lynx-comlynx.s index aa4d71ad3..c4ae3d5b6 100644 --- a/libsrc/lynx/ser/lynx-comlynx.s +++ b/libsrc/lynx/ser/lynx-comlynx.s @@ -76,7 +76,8 @@ SER_CLOSE: ; Disable interrupts and stop timer 4 (serial) lda #TXOPEN|RESETERR sta SERCTL - stz TIM4CTLA ; Disable count and no reload + stz TIM4CTLA ; Disable count and no reload + stz SerialStat ; Reset status ; Done, return an error code lda #SER_ERR_OK @@ -241,8 +242,8 @@ GetByte: ldy RxPtrOut lda RxBuffer,y inc RxPtrOut + sta (ptr1) ldx #$00 - sta (ptr1,x) txa ; Return code = 0 rts @@ -288,8 +289,8 @@ PutByte: SER_STATUS: lda SerialStat + sta (ptr1) ldx #$00 - sta (ptr1,x) txa ; Return code = 0 rts @@ -327,7 +328,7 @@ SER_IRQ: and #PAREN ; Parity enabled implies SER_PAR_EVEN or SER_PAR_ODD tay ora #OVERRUN|FRAMERR|RXBRK - bit SERCTL ; Check presence of relevant error flags in SERCTL + and SERCTL ; Check presence of relevant error flags in SERCTL beq @rx_irq ; No errors so far From 8173c850fd5fe0a0038baa3bf8767c920f127174 Mon Sep 17 00:00:00 2001 From: Sven Michael Klose Date: Thu, 15 Feb 2024 00:00:46 +0100 Subject: [PATCH 10/21] Fix size of MAIN to end at $1E00. Caused negative size of MAIN in cc65-contrib/quikmans2k8. --- cfg/vic20-asm.cfg | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cfg/vic20-asm.cfg b/cfg/vic20-asm.cfg index 286a7f95c..fc9d668e4 100644 --- a/cfg/vic20-asm.cfg +++ b/cfg/vic20-asm.cfg @@ -7,7 +7,7 @@ SYMBOLS { MEMORY { ZP: file = "", start = $0002, size = $001A, define = yes; LOADADDR: file = %O, start = %S - 2, size = $0002; - MAIN: file = %O, start = %S, size = $0DF3 - %S; + MAIN: file = %O, start = %S, size = $1E00 - %S; } SEGMENTS { ZEROPAGE: load = ZP, type = zp, optional = yes; From 3a7bd539568e25f33c64a88fd6e76a9e015c74f2 Mon Sep 17 00:00:00 2001 From: Sven Michael Klose Date: Thu, 15 Feb 2024 01:05:35 +0100 Subject: [PATCH 11/21] Test strtok(). --- test/ref/strtok.c | 43 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 test/ref/strtok.c diff --git a/test/ref/strtok.c b/test/ref/strtok.c new file mode 100644 index 000000000..15c3a289d --- /dev/null +++ b/test/ref/strtok.c @@ -0,0 +1,43 @@ +// 2024-02-14 Sven Michael Klose + +#include +#include +#include + +void +error (void) +{ + printf ("strtok() test failed!\n"); + exit (-1); +} + +void +test (char * s) +{ + if (strcmp ("test", strtok (s, "/"))) + error (); + if (strcmp ("foo", strtok (NULL, "/"))) + error (); + if (strcmp ("bar", strtok (NULL, "/"))) + error (); + if (strtok (NULL, "/")) + error (); + if (strtok (NULL, "/")) + error (); +} + +int +main (void) +{ + char s1[] = "test/foo/bar"; + char s2[] = "/test/foo/bar"; + char s3[] = "//test/foo/bar"; + char s4[] = "//test/foo/bar//"; + + test (s1); + test (s2); + test (s3); + test (s4); + + return 0; +} From 8d4946b3f451aec4547415ad09419ad90330b2bb Mon Sep 17 00:00:00 2001 From: Stefan Date: Thu, 15 Feb 2024 07:52:42 +0100 Subject: [PATCH 12/21] Fixed segv touch /tmp/xx grc65 /tmp/xx --- src/grc65/main.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/src/grc65/main.c b/src/grc65/main.c index 7d31bfc52..6b3ca04de 100644 --- a/src/grc65/main.c +++ b/src/grc65/main.c @@ -231,10 +231,11 @@ static int findToken (const char * const *tokenTbl, const char *token) /* takes as input table of tokens and token, returns position in table or -1 if not found */ int i; - for (i = 0; tokenTbl[i][0]; i++) { - if (strcmp (tokenTbl[i], token) == 0) { - return i; - } + if (token != NULL) { + for (i = 0; tokenTbl[i][0]; i++) { + if (strcmp (tokenTbl[i], token) == 0) { + return i; + } } return -1; From ab0eb4fe58450649c698ebead914a97069dfbe7f Mon Sep 17 00:00:00 2001 From: Stefan Date: Thu, 15 Feb 2024 09:03:46 +0100 Subject: [PATCH 13/21] oops --- src/grc65/main.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/grc65/main.c b/src/grc65/main.c index 6b3ca04de..5ef9e9645 100644 --- a/src/grc65/main.c +++ b/src/grc65/main.c @@ -236,6 +236,7 @@ static int findToken (const char * const *tokenTbl, const char *token) if (strcmp (tokenTbl[i], token) == 0) { return i; } + } } return -1; From 294b034920ecf67cc436415fa84fd1529463ae04 Mon Sep 17 00:00:00 2001 From: Sven Michael Klose Date: Thu, 15 Feb 2024 17:32:44 +0100 Subject: [PATCH 14/21] Add configuration files for expanded VICs. --- cfg/vic20-asm-32k.cfg | 21 +++++++++++++++++++++ cfg/vic20-asm-3k.cfg | 21 +++++++++++++++++++++ cfg/vic20-asm.cfg | 2 ++ 3 files changed, 44 insertions(+) create mode 100644 cfg/vic20-asm-32k.cfg create mode 100644 cfg/vic20-asm-3k.cfg diff --git a/cfg/vic20-asm-32k.cfg b/cfg/vic20-asm-32k.cfg new file mode 100644 index 000000000..622cfb26f --- /dev/null +++ b/cfg/vic20-asm-32k.cfg @@ -0,0 +1,21 @@ +# Assembly program configuration for expanded VICs (>= +8K). + +FEATURES { + STARTADDRESS: default = $1201; +} +SYMBOLS { + __LOADADDR__: type = import; +} +MEMORY { + ZP: file = "", start = $0002, size = $001A, define = yes; + LOADADDR: file = %O, start = %S - 2, size = $0002; + MAIN: file = %O, start = %S, size = $8000 - %S; +} +SEGMENTS { + ZEROPAGE: load = ZP, type = zp, optional = yes; + LOADADDR: load = LOADADDR, type = ro; + CODE: load = MAIN, type = ro; + RODATA: load = MAIN, type = ro; + DATA: load = MAIN, type = rw; + BSS: load = MAIN, type = bss, optional = yes, define = yes; +} diff --git a/cfg/vic20-asm-3k.cfg b/cfg/vic20-asm-3k.cfg new file mode 100644 index 000000000..1afaf0b30 --- /dev/null +++ b/cfg/vic20-asm-3k.cfg @@ -0,0 +1,21 @@ +# Assembly program configuration for expanded VICs (+3K only). + +FEATURES { + STARTADDRESS: default = $0401; +} +SYMBOLS { + __LOADADDR__: type = import; +} +MEMORY { + ZP: file = "", start = $0002, size = $001A, define = yes; + LOADADDR: file = %O, start = %S - 2, size = $0002; + MAIN: file = %O, start = %S, size = $1E00 - %S; +} +SEGMENTS { + ZEROPAGE: load = ZP, type = zp, optional = yes; + LOADADDR: load = LOADADDR, type = ro; + CODE: load = MAIN, type = ro; + RODATA: load = MAIN, type = ro; + DATA: load = MAIN, type = rw; + BSS: load = MAIN, type = bss, optional = yes, define = yes; +} diff --git a/cfg/vic20-asm.cfg b/cfg/vic20-asm.cfg index fc9d668e4..5f6c7cc74 100644 --- a/cfg/vic20-asm.cfg +++ b/cfg/vic20-asm.cfg @@ -1,3 +1,5 @@ +# Assembly program configuration for unexpanded VICs. + FEATURES { STARTADDRESS: default = $1001; } From 7a12399b39acd656da3d8802dca0ed1ef09d18c3 Mon Sep 17 00:00:00 2001 From: Colin Leroy-Mira Date: Mon, 19 Feb 2024 13:27:42 +0100 Subject: [PATCH 15/21] Allow choosing 115200bps as the card allows it Of course, that won't work full speed with the standard IRQ-based RX. But that will allow users to setup the port at this speed without duplicating the setup part of the code. Up to them to add hooks to disable IRQs and read directly in a tight asm loop. --- libsrc/apple2/ser/a2.ssc.s | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libsrc/apple2/ser/a2.ssc.s b/libsrc/apple2/ser/a2.ssc.s index c8aa6e9a5..7053b7bb1 100644 --- a/libsrc/apple2/ser/a2.ssc.s +++ b/libsrc/apple2/ser/a2.ssc.s @@ -121,7 +121,7 @@ BaudTable: ; Table used to translate RS232 baudrate param .byte $0F ; SER_BAUD_19200 .byte $FF ; SER_BAUD_38400 .byte $FF ; SER_BAUD_57600 - .byte $FF ; SER_BAUD_115200 + .byte $00 ; SER_BAUD_115200 .byte $FF ; SER_BAUD_230400 BitTable: ; Table used to translate RS232 databits param From 3fd78208bab5cd7d8fa601a4a94af3f66ed39ec1 Mon Sep 17 00:00:00 2001 From: Colin Leroy-Mira Date: Mon, 19 Feb 2024 18:27:34 +0100 Subject: [PATCH 16/21] Disable IRQ if opening at 115200 bps --- doc/apple2.sgml | 5 +++++ doc/apple2enh.sgml | 5 +++++ libsrc/apple2/ser/a2.ssc.s | 10 ++++++++-- 3 files changed, 18 insertions(+), 2 deletions(-) diff --git a/doc/apple2.sgml b/doc/apple2.sgml index e6ec870ee..99ff8139e 100644 --- a/doc/apple2.sgml +++ b/doc/apple2.sgml @@ -452,10 +452,15 @@ The names in the parentheses denote the symbols to be used for static linking of (RTS/CTS) and does interrupt driven receives. Speeds faster than 9600 baud aren't reachable because the ROM and ProDOS IRQ handlers are too slow. Software flow control (XON/XOFF) is not supported. + Note that because of the peculiarities of the 6551 chip transmits are not interrupt driven, and the transceiver blocks if the receiver asserts flow control because of a full buffer. + Note that using the driver at SER_BAUD_115200 will disable IRQs. It will be up + to the users to use the serial port, either by re-enabling IRQs themselves, + or by directly poll-reading the ACIA DATA register without the help of ser_get(). + The driver defaults to slot 2. Call Date: Mon, 19 Feb 2024 21:30:26 +0100 Subject: [PATCH 17/21] IIgs SCC: Allow choosing 115200bps as the card allows it Of course, that won't work full speed with the standard IRQ-based RX. But that will allow users to setup the port at this speed without duplicating the setup part of the code. Up to them to add hooks to disable IRQs and read directly in a tight asm loop. --- libsrc/apple2/ser/a2.gs.s | 66 +++++++++++++++++++++++++++++---------- 1 file changed, 49 insertions(+), 17 deletions(-) diff --git a/libsrc/apple2/ser/a2.gs.s b/libsrc/apple2/ser/a2.gs.s index 3a2db1926..c53fe7ecb 100644 --- a/libsrc/apple2/ser/a2.gs.s +++ b/libsrc/apple2/ser/a2.gs.s @@ -66,6 +66,8 @@ HSType: .res 1 ; Flow-control type RecvBuf: .res 256 ; Receive buffers: 256 bytes SendBuf: .res 256 ; Send buffers: 256 bytes +ClockSource: .res 1 ; Whether to use BRG or XTAL for clock + .data Opened: .byte $00 ; 1 when opened @@ -106,6 +108,15 @@ TxBitTable: .byte %00000000 ; SER_BITS_5, in WR_TX_CTRL (WR5) .rodata +ClockMultiplier:.byte %01000000 ; Clock x16 (300-57600bps, ref page 5-8) + .byte %10000000 ; Clock x32 (115200bps, ref page 5-8) + +ClockSourceA: .byte %11010000 ; Use baud rate generator (page 5-17) + .byte %10000000 ; Use XTAL (115200bps) + +ClockSourceB: .byte %01010000 ; Use baud rate generator + .byte %00000000 ; Use XTAL (115200bps) + BaudTable: ; bit7 = 1 means setting is invalid ; Otherwise refers to the index in ; Baud(Low/High)Table @@ -127,7 +138,7 @@ BaudTable: ; bit7 = 1 means setting is invalid .byte $05 ; SER_BAUD_19200 .byte $06 ; SER_BAUD_38400 .byte $07 ; SER_BAUD_57600 - .byte $FF ; SER_BAUD_115200 + .byte $00 ; SER_BAUD_115200 .byte $FF ; SER_BAUD_230400 StopTable: .byte %00000100 ; SER_STOP_1, in WR_TX_RX_CTRL (WR4) @@ -180,7 +191,6 @@ RX_CTRL_OFF = %11111110 ; ANDed,Rx disabled WR_TX_RX_CTRL = 4 RR_TX_RX_STATUS = 4 -TX_RX_CLOCK_MUL = %01000000 ; Clock x16 (Ref page 5-8) WR_TX_CTRL = 5 ; (Ref page 5-9) RR_TX_STATUS = 5 ; Corresponding status register @@ -197,15 +207,13 @@ MASTER_IRQ_MIE_RST = %00001010 ; STA'd MASTER_IRQ_SET = %00011001 ; STA'd WR_CLOCK_CTRL = 11 ; (Ref page 5-17) -CLOCK_CTRL_CH_A = %11010000 -CLOCK_CTRL_CH_B = %01010000 WR_BAUDL_CTRL = 12 ; (Ref page 5-18) WR_BAUDH_CTRL = 13 ; (Ref page 5-19) WR_MISC_CTRL = 14 ; (Ref page 5-19) -MISC_CTRL_RATE_GEN_ON = %00000001 ; ORed -MISC_CTRL_RATE_GEN_OFF = %11111110 ; ANDed +MISC_CTRL_RATE_GEN_ON = %00000001 ; STA'd +MISC_CTRL_RATE_GEN_OFF = %00000000 ; STA'd WR_IRQ_CTRL = 15 ; (Ref page 5-20) IRQ_CLEANUP_EIRQ = %00001000 @@ -329,6 +337,16 @@ IIgs: : txa ; Promote char return value rts +getClockSource: + ldy #SER_PARAMS::BAUDRATE + lda (ptr1),y ; Baudrate index - cc65 value + ldy #$01 + cmp #SER_BAUD_115200 + beq :+ + ldy #$00 +: sty ClockSource + rts + ;---------------------------------------------------------------------------- ; SER_OPEN: A pointer to a ser_params structure is passed in ptr1. ; Must return an SER_ERR_xx code in a/x. @@ -364,6 +382,8 @@ SER_OPEN: lda #$00 jsr writeSCCReg + jsr getClockSource ; Should we use BRG or XTAL? + ldy #SER_PARAMS::STOPBITS lda (ptr1),y ; Stop bits tay @@ -377,16 +397,18 @@ SER_OPEN: ora ParityTable,y ; Get value bmi InvParam - ora #TX_RX_CLOCK_MUL + ldy ClockSource ; Setup clock multiplier + ora ClockMultiplier,y ldy #WR_TX_RX_CTRL ; Setup stop & parity bits jsr writeSCCReg + ldy ClockSource cpx #CHANNEL_B bne ClockA ClockB: + lda ClockSourceB,y ldy #WR_CLOCK_CTRL - lda #CLOCK_CTRL_CH_B jsr writeSCCReg lda #INTR_PENDING_RX_EXT_B ; Store which IRQ bits we'll check @@ -394,8 +416,8 @@ ClockB: bra SetBaud ClockA: + lda ClockSourceA,y ldy #WR_CLOCK_CTRL - lda #CLOCK_CTRL_CH_A jsr writeSCCReg lda #INTR_PENDING_RX_EXT_A ; Store which IRQ bits we'll check @@ -411,11 +433,16 @@ SetBaud: InvParam: lda #SER_ERR_INIT_FAILED - ldy #$00 ; Mark port closed - bra SetupOut + ldx #$00 ; Promote char return value + stz Opened ; Mark port closed + cli + rts BaudOK: tay + cpy #SER_BAUD_115200 + beq :+ ; Skip baud rate generator setup: + ; For 115200bps, we use XTAL instead lda BaudLowTable,y ; Get low byte @@ -428,8 +455,13 @@ BaudOK: ldy #WR_BAUDH_CTRL jsr writeSCCReg - ldy #WR_MISC_CTRL ; Time to turn this thing on - lda #MISC_CTRL_RATE_GEN_ON +: lda #MISC_CTRL_RATE_GEN_ON ; Setup BRG according to selected rate + ldy ClockSource + cpy #$00 + beq :+ + lda #MISC_CTRL_RATE_GEN_OFF + +: ldy #WR_MISC_CTRL ; Time to turn this thing on jsr writeSCCReg ldy #SER_PARAMS::DATABITS @@ -486,11 +518,11 @@ StoreFlag: sta SER_FLAG ldy #$01 ; Mark port opened - lda #SER_ERR_OK - -SetupOut: - ldx #$00 ; Promote char return value sty Opened + + lda #SER_ERR_OK + ldx #$00 ; Promote char return value + cli rts From 86317711e0931af0dc735ca7a0715369d0d0310c Mon Sep 17 00:00:00 2001 From: Colin Leroy-Mira Date: Tue, 20 Feb 2024 07:17:12 +0100 Subject: [PATCH 18/21] IIgs SCC: Rework branches to X-indexed variables and general cleanup/commenting --- libsrc/apple2/ser/a2.gs.s | 244 +++++++++++++++++--------------------- 1 file changed, 110 insertions(+), 134 deletions(-) diff --git a/libsrc/apple2/ser/a2.gs.s b/libsrc/apple2/ser/a2.gs.s index c53fe7ecb..e35c6156b 100644 --- a/libsrc/apple2/ser/a2.gs.s +++ b/libsrc/apple2/ser/a2.gs.s @@ -66,36 +66,16 @@ HSType: .res 1 ; Flow-control type RecvBuf: .res 256 ; Receive buffers: 256 bytes SendBuf: .res 256 ; Send buffers: 256 bytes -ClockSource: .res 1 ; Whether to use BRG or XTAL for clock +CurClockSource: .res 1 ; Whether to use BRG or RTxC for clock .data Opened: .byte $00 ; 1 when opened Channel: .byte $00 ; Channel B by default -CurChanIrqFlags:.byte INTR_PENDING_RX_EXT_B +CurChanIrqFlags:.byte $00 SerFlagOrig: .byte $00 -; Tables used to translate cc65 RS232 params into register values -; (Ref page 5-18 and 5-19) -BaudLowTable: .byte $7E ; SER_BAUD_300 - .byte $5E ; SER_BAUD_1200 - .byte $2E ; SER_BAUD_2400 - .byte $16 ; SER_BAUD_4800 - .byte $0A ; SER_BAUD_9600 - .byte $04 ; SER_BAUD_19200 - .byte $01 ; SER_BAUD_38400 - .byte $00 ; SER_BAUD_57600 - -BaudHighTable: .byte $01 ; SER_BAUD_300 - .byte $00 ; SER_BAUD_1200 - .byte $00 ; SER_BAUD_2400 - .byte $00 ; SER_BAUD_4800 - .byte $00 ; SER_BAUD_9600 - .byte $00 ; SER_BAUD_19200 - .byte $00 ; SER_BAUD_38400 - .byte $00 ; SER_BAUD_57600 - RxBitTable: .byte %00000000 ; SER_BITS_5, in WR_RX_CTRL (WR3) .byte %10000000 ; SER_BITS_6 (Ref page 5-7) .byte %01000000 ; SER_BITS_7 @@ -108,38 +88,65 @@ TxBitTable: .byte %00000000 ; SER_BITS_5, in WR_TX_CTRL (WR5) .rodata -ClockMultiplier:.byte %01000000 ; Clock x16 (300-57600bps, ref page 5-8) +ClockMultiplier:.byte %01000000 ; Clock x16 (300-57600bps, WR4, ref page 5-8) .byte %10000000 ; Clock x32 (115200bps, ref page 5-8) -ClockSourceA: .byte %11010000 ; Use baud rate generator (page 5-17) - .byte %10000000 ; Use XTAL (115200bps) +ClockSource: .byte %01010000 ; Use baud rate generator (ch. B) (WR11, page 5-17) + .byte %00000000 ; Use RTxC (115200bps) (ch. B) + .byte %11010000 ; Use baud rate generator (ch. A) + .byte %10000000 ; Use RTxC (115200bps) (ch. A) -ClockSourceB: .byte %01010000 ; Use baud rate generator - .byte %00000000 ; Use XTAL (115200bps) +BrgEnabled: .byte %00000001 ; Baud rate generator on (WR14, page 5-19) + .byte %00000000 ; BRG Off + +ChanIrqFlags: .byte %00000101 ; ANDed (RX/special IRQ, ch. B) (page 5-25) + .byte %00101000 ; ANDed (RX/special IRQ, ch. A) + +ChanIrqMask: .byte %00000111 ; Ch. B IRQ flags mask + .byte %00111000 ; Ch. A IRQ flags mask BaudTable: ; bit7 = 1 means setting is invalid - ; Otherwise refers to the index in - ; Baud(Low/High)Table - .byte $FF ; SER_BAUD_45_5 - .byte $FF ; SER_BAUD_50 - .byte $FF ; SER_BAUD_75 - .byte $FF ; SER_BAUD_110 - .byte $FF ; SER_BAUD_134_5 - .byte $FF ; SER_BAUD_150 - .byte $00 ; SER_BAUD_300 - .byte $FF ; SER_BAUD_600 - .byte $01 ; SER_BAUD_1200 - .byte $FF ; SER_BAUD_1800 - .byte $02 ; SER_BAUD_2400 - .byte $FF ; SER_BAUD_3600 - .byte $03 ; SER_BAUD_4800 - .byte $FF ; SER_BAUD_7200 - .byte $04 ; SER_BAUD_9600 - .byte $05 ; SER_BAUD_19200 - .byte $06 ; SER_BAUD_38400 - .byte $07 ; SER_BAUD_57600 - .byte $00 ; SER_BAUD_115200 - .byte $FF ; SER_BAUD_230400 + ; Indexes cc65 RS232 SER_BAUD enum + ; into WR12/13 register values + ; (Ref page 5-18 and 5-19) + .word $FFFF ; SER_BAUD_45_5 + .word $FFFF ; SER_BAUD_50 + .word $FFFF ; SER_BAUD_75 + .word $FFFF ; SER_BAUD_110 + .word $FFFF ; SER_BAUD_134_5 + .word $FFFF ; SER_BAUD_150 + .word $017E ; SER_BAUD_300 + .word $FFFF ; SER_BAUD_600 + .word $005E ; SER_BAUD_1200 + .word $FFFF ; SER_BAUD_1800 + .word $002E ; SER_BAUD_2400 + .word $FFFF ; SER_BAUD_3600 + .word $0016 ; SER_BAUD_4800 + .word $FFFF ; SER_BAUD_7200 + .word $000A ; SER_BAUD_9600 + .word $0004 ; SER_BAUD_19200 + .word $0001 ; SER_BAUD_38400 + .word $0000 ; SER_BAUD_57600 + .word $0000 ; SER_BAUD_115200 (constant unused at that speed) + .word $FFFF ; SER_BAUD_230400 + +; About the speed selection: either we use the baud rate generator: +; - Load the time constants from BaudTable into WR12/WR13 +; - Setup the TX/RX clock source to BRG (ClockSource into WR11) +; - Setup the clock multiplier (WR4) +; - Enable the baud rate generator (WR14) +; In this case, the baud rate will be: +; rate = crystal_clock/(2+BRG_time_constant))/(2*clock_multiplier) +; Example: (3686400/(2+0x0004)) / (2*16) = 19200 bps +; +; Or we don't use the baud rate generator: +; - Setup the TX/RX clock source to RTxC +; - Setup the clock multiplier +; - Disable the baud rate generator +; - WR12 and 13 are ignored +; In this case, the baud rate will be: +; rate = crystal_clock/clock_multiplier +; Example: 3686400/32 = 115200 bps StopTable: .byte %00000100 ; SER_STOP_1, in WR_TX_RX_CTRL (WR4) .byte %00001100 ; SER_STOP_2 (Ref page 5-8) @@ -167,6 +174,7 @@ SER_FLAG := $E10104 ; ------------------------------------------------------------------------ ; Channels + CHANNEL_B = 0 CHANNEL_A = 1 @@ -212,8 +220,6 @@ WR_BAUDL_CTRL = 12 ; (Ref page 5-18) WR_BAUDH_CTRL = 13 ; (Ref page 5-19) WR_MISC_CTRL = 14 ; (Ref page 5-19) -MISC_CTRL_RATE_GEN_ON = %00000001 ; STA'd -MISC_CTRL_RATE_GEN_OFF = %00000000 ; STA'd WR_IRQ_CTRL = 15 ; (Ref page 5-20) IRQ_CLEANUP_EIRQ = %00001000 @@ -228,13 +234,8 @@ IRQ_RX = %00100000 IRQ_SPECIAL = %01100000 RR_INTR_PENDING_STATUS = 3 ; (Ref page 5-25) -INTR_PENDING_RX_EXT_A = %00101000 ; ANDed (RX or special IRQ) -INTR_PENDING_RX_EXT_B = %00000101 ; ANDed (RX or special IRQ) INTR_IS_RX = %00100100 ; ANDed (RX IRQ, channel A or B) -SER_FLAG_CH_A = %00111000 -SER_FLAG_CH_B = %00000111 - .code ; Read register value to A. @@ -338,13 +339,12 @@ IIgs: rts getClockSource: - ldy #SER_PARAMS::BAUDRATE - lda (ptr1),y ; Baudrate index - cc65 value - ldy #$01 + .assert SER_PARAMS::BAUDRATE = 0, error + lda (ptr1) ; Baudrate index - cc65 value cmp #SER_BAUD_115200 - beq :+ - ldy #$00 -: sty ClockSource + lda #$00 + adc #$00 + sta CurClockSource ; 0 = BRG, 1 = RTxC rts ;---------------------------------------------------------------------------- @@ -378,13 +378,13 @@ SER_OPEN: ldy #RR_INIT_STATUS ; Hit rr0 once to sync up jsr readSSCReg - ldy #WR_MISC_CTRL ; Turn everything off + ldy #WR_MISC_CTRL ; WR14: Turn everything off lda #$00 jsr writeSCCReg - jsr getClockSource ; Should we use BRG or XTAL? + jsr getClockSource ; Should we use BRG or RTxC? - ldy #SER_PARAMS::STOPBITS + ldy #SER_PARAMS::STOPBITS ; WR4 setup: clock mult., stop & parity lda (ptr1),y ; Stop bits tay lda StopTable,y ; Get value @@ -397,109 +397,92 @@ SER_OPEN: ora ParityTable,y ; Get value bmi InvParam - ldy ClockSource ; Setup clock multiplier + ldy CurClockSource ; Clock multiplier ora ClockMultiplier,y - ldy #WR_TX_RX_CTRL ; Setup stop & parity bits - jsr writeSCCReg + ldy #WR_TX_RX_CTRL + jsr writeSCCReg ; End of WR4 setup - ldy ClockSource + ldy CurClockSource ; WR11 setup: clock source cpx #CHANNEL_B - bne ClockA -ClockB: - lda ClockSourceB,y + beq SetClock + iny ; Shift to get correct ClockSource val + iny ; depending on our channel + +SetClock: + lda ClockSource,y ldy #WR_CLOCK_CTRL - jsr writeSCCReg + jsr writeSCCReg ; End of WR11 setup - lda #INTR_PENDING_RX_EXT_B ; Store which IRQ bits we'll check - sta CurChanIrqFlags - - bra SetBaud -ClockA: - lda ClockSourceA,y - ldy #WR_CLOCK_CTRL - jsr writeSCCReg - - lda #INTR_PENDING_RX_EXT_A ; Store which IRQ bits we'll check + lda ChanIrqFlags,x ; Store which IRQ bits we'll check sta CurChanIrqFlags SetBaud: - ldy #SER_PARAMS::BAUDRATE - lda (ptr1),y ; Baudrate index - cc65 value + .assert SER_PARAMS::BAUDRATE = 0, error + lda (ptr1) ; Baudrate index - cc65 value + asl tay - lda BaudTable,y ; Get chip value from Low/High tables + lda BaudTable,y ; Get low byte of register value bpl BaudOK ; Verify baudrate is supported InvParam: lda #SER_ERR_INIT_FAILED - ldx #$00 ; Promote char return value - stz Opened ; Mark port closed - cli - rts + ldy #$00 ; Mark port closed + bra SetupOut BaudOK: - tay - cpy #SER_BAUD_115200 - beq :+ ; Skip baud rate generator setup: - ; For 115200bps, we use XTAL instead - - lda BaudLowTable,y ; Get low byte - - phy - ldy #WR_BAUDL_CTRL - jsr writeSCCReg + phy ; WR12 setup: BRG time constant, low byte + ldy #WR_BAUDL_CTRL ; Setting WR12 & 13 is useless if we're using + jsr writeSCCReg ; RTxC, but doing it anyway makes code smaller ply - lda BaudHighTable,y ; Get high byte + iny + lda BaudTable,y ; WR13 setup: BRG time constant, high byte ldy #WR_BAUDH_CTRL jsr writeSCCReg -: lda #MISC_CTRL_RATE_GEN_ON ; Setup BRG according to selected rate - ldy ClockSource - cpy #$00 - beq :+ - lda #MISC_CTRL_RATE_GEN_OFF - -: ldy #WR_MISC_CTRL ; Time to turn this thing on + ldy CurClockSource ; WR14 setup: BRG enabling + lda BrgEnabled,y + ldy #WR_MISC_CTRL ; Time to turn this thing on jsr writeSCCReg - ldy #SER_PARAMS::DATABITS - lda (ptr1),y ; Data bits + ldy #SER_PARAMS::DATABITS ; WR3 setup: RX data bits + lda (ptr1),y tay - lda RxBitTable,y ; Data bits for RX - ora #RX_CTRL_ON ; and turn RX on + lda RxBitTable,y + ora #RX_CTRL_ON ; and turn receiver on phy ldy #WR_RX_CTRL - jsr writeSCCReg + jsr writeSCCReg ; End of WR3 setup ply - lda TxBitTable,y ; Data bits for TX - ora #TX_CTRL_ON ; and turn TX on - and #TX_DTR_ON + lda TxBitTable,y ; WR5 setup: TX data bits + ora #TX_CTRL_ON ; and turn transmitter on + and #TX_DTR_ON ; and turn DTR on sta RtsOff ; Save value for flow control - ora #TX_RTS_ON + ora #TX_RTS_ON ; and turn RTS on ldy #WR_TX_CTRL - jsr writeSCCReg + jsr writeSCCReg ; End of WR5 setup - ldy #WR_IRQ_CTRL + ldy #WR_IRQ_CTRL ; WR15 setup: IRQ lda #IRQ_CLEANUP_EIRQ jsr writeSCCReg - ldy #WR_INIT_CTRL ; Clear ext status (write twice) + ldy #WR_INIT_CTRL ; WR0 setup: clear existing IRQs lda #INIT_CTRL_CLEAR_EIRQ - jsr writeSCCReg + jsr writeSCCReg ; Clear (write twice) jsr writeSCCReg - ldy #WR_TX_RX_MODE_CTRL ; Activate RX IRQ + ldy #WR_TX_RX_MODE_CTRL ; WR1 setup: Activate RX IRQ lda #TX_RX_MODE_RXIRQ jsr writeSCCReg - lda SCCBREG ; Activate master IRQ + lda SCCBREG ; WR9 setup: Activate master IRQ ldy #WR_MASTER_IRQ_RST lda #MASTER_IRQ_SET jsr writeSCCReg @@ -507,22 +490,15 @@ BaudOK: lda SER_FLAG ; Get SerFlag's current value sta SerFlagOrig ; and save it - cpx #CHANNEL_B - bne IntA -IntB: - ora #SER_FLAG_CH_B ; Inform firmware we want channel B IRQs - bra StoreFlag -IntA: - ora #SER_FLAG_CH_A ; Inform firmware we want channel A IRQs -StoreFlag: + ora ChanIrqMask,x ; Tell firmware which channel IRQs we want sta SER_FLAG ldy #$01 ; Mark port opened - sty Opened - lda #SER_ERR_OK - ldx #$00 ; Promote char return value +SetupOut: + ldx #$00 ; Promote char return value + sty Opened cli rts From 23aa562094bdfeca0eb9d2e13b94b5f3208fa575 Mon Sep 17 00:00:00 2001 From: acqn Date: Sat, 24 Feb 2024 15:34:38 +0800 Subject: [PATCH 19/21] Fixed potential errors with subtraction evaluation of identifiers at different memory locations. --- src/cc65/expr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cc65/expr.c b/src/cc65/expr.c index a855e5b3c..f6c681db8 100644 --- a/src/cc65/expr.c +++ b/src/cc65/expr.c @@ -3272,7 +3272,7 @@ static void parsesub (ExprDesc* Expr) /* The right hand side is constant. Check left hand side. */ if (ED_IsQuasiConst (Expr)) { /* We can't do all 'ptr1 - ptr2' constantly at the moment */ - if (Expr->Sym == Expr2.Sym) { + if (ED_GetLoc (Expr) == ED_GetLoc (&Expr2) && Expr->Sym == Expr2.Sym) { Expr->IVal = (Expr->IVal - Expr2.IVal) / rscale; /* Get rid of unneeded flags etc. */ ED_MakeConstAbsInt (Expr, Expr->IVal); From 9b2d27d1e1a24a912978f8fa496f921523e3f909 Mon Sep 17 00:00:00 2001 From: acqn Date: Thu, 29 Feb 2024 18:23:04 +0800 Subject: [PATCH 20/21] Fixed the error recovery integer type used for bit-fields. --- src/cc65/declare.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/src/cc65/declare.c b/src/cc65/declare.c index e1e66ab85..11e6c5227 100644 --- a/src/cc65/declare.c +++ b/src/cc65/declare.c @@ -905,6 +905,8 @@ static int ParseFieldWidth (Declarator* D) ** otherwise the width of the field. */ { + ExprDesc Expr; + if (CurTok.Tok != TOK_COLON) { /* No bit-field declaration */ return -1; @@ -918,7 +920,16 @@ static int ParseFieldWidth (Declarator* D) /* Avoid a diagnostic storm by giving the bit-field the widest valid ** signed type, and continuing to parse. */ - D->Type[0].C = T_INT; + D->Type[0].C = T_LONG; + } + + if (IsTypeEnum (D->Type) && IsIncompleteESUType (D->Type)) { + /* If the type is an enum, it must be complete */ + Error ("Bit-field has incomplete type '%s'", + GetFullTypeName (D->Type)); + + /* Avoid a diagnostic storm */ + D->Type[0].C = T_LONG; } /* We currently support integral types up to long */ @@ -927,12 +938,12 @@ static int ParseFieldWidth (Declarator* D) Error ("cc65 currently supports only long-sized and smaller bit-field types"); /* Avoid a diagnostic storm */ - D->Type[0].C = T_INT; + D->Type[0].C = T_LONG; } /* Read the width */ NextToken (); - ExprDesc Expr = NoCodeConstAbsIntExpr (hie1); + Expr = NoCodeConstAbsIntExpr (hie1); if (Expr.IVal < 0) { Error ("Negative width in bit-field"); From a887b29ffb8b138dba83b00aff4b5ab4d2288e19 Mon Sep 17 00:00:00 2001 From: Sven Michael Klose Date: Tue, 5 Mar 2024 07:04:59 +0100 Subject: [PATCH 21/21] Revert "Test strtok()." This reverts commit 3a7bd539568e25f33c64a88fd6e76a9e015c74f2. --- test/ref/strtok.c | 43 ------------------------------------------- 1 file changed, 43 deletions(-) delete mode 100644 test/ref/strtok.c diff --git a/test/ref/strtok.c b/test/ref/strtok.c deleted file mode 100644 index 15c3a289d..000000000 --- a/test/ref/strtok.c +++ /dev/null @@ -1,43 +0,0 @@ -// 2024-02-14 Sven Michael Klose - -#include -#include -#include - -void -error (void) -{ - printf ("strtok() test failed!\n"); - exit (-1); -} - -void -test (char * s) -{ - if (strcmp ("test", strtok (s, "/"))) - error (); - if (strcmp ("foo", strtok (NULL, "/"))) - error (); - if (strcmp ("bar", strtok (NULL, "/"))) - error (); - if (strtok (NULL, "/")) - error (); - if (strtok (NULL, "/")) - error (); -} - -int -main (void) -{ - char s1[] = "test/foo/bar"; - char s2[] = "/test/foo/bar"; - char s3[] = "//test/foo/bar"; - char s4[] = "//test/foo/bar//"; - - test (s1); - test (s2); - test (s3); - test (s4); - - return 0; -}