diff --git a/cfg/cx16-asm.cfg b/cfg/cx16-asm.cfg index c3c08aec3..92c9d96f7 100644 --- a/cfg/cx16-asm.cfg +++ b/cfg/cx16-asm.cfg @@ -22,9 +22,11 @@ SEGMENTS { EXEHDR: load = MAIN, type = ro, optional = yes; CODE: load = MAIN, type = ro; LOWCODE: load = MAIN, type = ro, optional = yes; + ONCE: load = MAIN, type = ro, optional = yes; RODATA: load = MAIN, type = ro; DATA: load = MAIN, type = rw; - BSS: load = MAIN, type = bss, define = yes; + INIT: load = MAIN, type = bss, optional = yes; + BSS: load = MAIN, type = bss, define = yes; } FEATURES { CONDES: type = constructor, diff --git a/cfg/cx16-bank.cfg b/cfg/cx16-bank.cfg index 36b0edb02..d3c2c02ae 100644 --- a/cfg/cx16-bank.cfg +++ b/cfg/cx16-bank.cfg @@ -16,8 +16,6 @@ MEMORY { HEADER: file = %O, define = yes, start = %S, size = $000D; MAIN: file = %O, define = yes, start = __HEADER_LAST__, size = __HIMEM__ - __HEADER_LAST__; BSS: file = "", start = __ONCE_RUN__, size = __HIMEM__ - __ONCE_RUN__ - __STACKSIZE__; -# BRAM00ADDR: file = "%O.00", start = __BANKRAMSTART__ - 2, size = $0002; -# BRAM00: file = "%O.00", start = __BANKRAMSTART__, size = __BANKRAMSIZE__; BRAM01ADDR: file = "%O.01", start = __BANKRAMSTART__ - 2, size = $0002; BRAM01: file = "%O.01", start = __BANKRAMSTART__, size = __BANKRAMSIZE__, bank = $01; BRAM02ADDR: file = "%O.02", start = __BANKRAMSTART__ - 2, size = $0002; @@ -36,64 +34,62 @@ MEMORY { BRAM08: file = "%O.08", start = __BANKRAMSTART__, size = __BANKRAMSIZE__, bank = $08; BRAM09ADDR: file = "%O.09", start = __BANKRAMSTART__ - 2, size = $0002; BRAM09: file = "%O.09", start = __BANKRAMSTART__, size = __BANKRAMSIZE__, bank = $09; - BRAM0AADDR: file = "%O.0a", start = __BANKRAMSTART__ - 2, size = $0002; - BRAM0A: file = "%O.0a", start = __BANKRAMSTART__, size = __BANKRAMSIZE__, bank = $0A; - BRAM0BADDR: file = "%O.0b", start = __BANKRAMSTART__ - 2, size = $0002; - BRAM0B: file = "%O.0b", start = __BANKRAMSTART__, size = __BANKRAMSIZE__, bank = $0B; - BRAM0CADDR: file = "%O.0c", start = __BANKRAMSTART__ - 2, size = $0002; - BRAM0C: file = "%O.0c", start = __BANKRAMSTART__, size = __BANKRAMSIZE__, bank = $0C; - BRAM0DADDR: file = "%O.0d", start = __BANKRAMSTART__ - 2, size = $0002; - BRAM0D: file = "%O.0d", start = __BANKRAMSTART__, size = __BANKRAMSIZE__, bank = $0D; - BRAM0EADDR: file = "%O.0e", start = __BANKRAMSTART__ - 2, size = $0002; - BRAM0E: file = "%O.0e", start = __BANKRAMSTART__, size = __BANKRAMSIZE__, bank = $0E; - BRAM0FADDR: file = "%O.0f", start = __BANKRAMSTART__ - 2, size = $0002; - BRAM0F: file = "%O.0f", start = __BANKRAMSTART__, size = __BANKRAMSIZE__, bank = $0F; + BRAM0AADDR: file = "%O.0A", start = __BANKRAMSTART__ - 2, size = $0002; + BRAM0A: file = "%O.0A", start = __BANKRAMSTART__, size = __BANKRAMSIZE__, bank = $0A; + BRAM0BADDR: file = "%O.0B", start = __BANKRAMSTART__ - 2, size = $0002; + BRAM0B: file = "%O.0B", start = __BANKRAMSTART__, size = __BANKRAMSIZE__, bank = $0B; + BRAM0CADDR: file = "%O.0C", start = __BANKRAMSTART__ - 2, size = $0002; + BRAM0C: file = "%O.0C", start = __BANKRAMSTART__, size = __BANKRAMSIZE__, bank = $0C; + BRAM0DADDR: file = "%O.0D", start = __BANKRAMSTART__ - 2, size = $0002; + BRAM0D: file = "%O.0D", start = __BANKRAMSTART__, size = __BANKRAMSIZE__, bank = $0D; + BRAM0EADDR: file = "%O.0E", start = __BANKRAMSTART__ - 2, size = $0002; + BRAM0E: file = "%O.0E", start = __BANKRAMSTART__, size = __BANKRAMSIZE__, bank = $0E; + BRAM0FADDR: file = "%O.0F", start = __BANKRAMSTART__ - 2, size = $0002; + BRAM0F: file = "%O.0F", start = __BANKRAMSTART__, size = __BANKRAMSIZE__, bank = $0F; } SEGMENTS { ZEROPAGE: load = ZP, type = zp; - EXTZP: load = ZP, type = zp, optional = yes; + EXTZP: load = ZP, type = zp, optional = yes; LOADADDR: load = LOADADDR, type = ro; EXEHDR: load = HEADER, type = ro; - STARTUP: load = MAIN, type = ro; - LOWCODE: load = MAIN, type = ro, optional = yes; + STARTUP: load = MAIN, type = ro, optional = yes; + LOWCODE: load = MAIN, type = ro, optional = yes; CODE: load = MAIN, type = ro; RODATA: load = MAIN, type = ro; DATA: load = MAIN, type = rw; - INIT: load = MAIN, type = rw; - ONCE: load = MAIN, type = ro, define = yes; - BSS: load = BSS, type = bss, define = yes; -# BRAM00ADDR: load = BRAM00ADDR, type = ro, optional = yes; -# BANKRAM00: load = BRAM00, type = rw, define = yes, optional = yes; - BRAM01ADDR: load = BRAM01ADDR, type = ro, optional = yes; - BANKRAM01: load = BRAM01, type = rw, define = yes, optional = yes; - BRAM02ADDR: load = BRAM02ADDR, type = ro, optional = yes; - BANKRAM02: load = BRAM02, type = rw, define = yes, optional = yes; - BRAM03ADDR: load = BRAM03ADDR, type = ro, optional = yes; - BANKRAM03: load = BRAM03, type = rw, define = yes, optional = yes; - BRAM04ADDR: load = BRAM04ADDR, type = ro, optional = yes; - BANKRAM04: load = BRAM04, type = rw, define = yes, optional = yes; - BRAM05ADDR: load = BRAM05ADDR, type = ro, optional = yes; - BANKRAM05: load = BRAM05, type = rw, define = yes, optional = yes; - BRAM06ADDR: load = BRAM06ADDR, type = ro, optional = yes; - BANKRAM06: load = BRAM06, type = rw, define = yes, optional = yes; - BRAM07ADDR: load = BRAM07ADDR, type = ro, optional = yes; - BANKRAM07: load = BRAM07, type = rw, define = yes, optional = yes; - BRAM08ADDR: load = BRAM08ADDR, type = ro, optional = yes; - BANKRAM08: load = BRAM08, type = rw, define = yes, optional = yes; - BRAM09ADDR: load = BRAM09ADDR, type = ro, optional = yes; - BANKRAM09: load = BRAM09, type = rw, define = yes, optional = yes; - BRAM0AADDR: load = BRAM0AADDR, type = ro, optional = yes; - BANKRAM0A: load = BRAM0A, type = rw, define = yes, optional = yes; - BRAM0BADDR: load = BRAM0BADDR, type = ro, optional = yes; - BANKRAM0B: load = BRAM0B, type = rw, define = yes, optional = yes; - BRAM0CADDR: load = BRAM0CADDR, type = ro, optional = yes; - BANKRAM0C: load = BRAM0C, type = rw, define = yes, optional = yes; - BRAM0DADDR: load = BRAM0DADDR, type = ro, optional = yes; - BANKRAM0D: load = BRAM0D, type = rw, define = yes, optional = yes; - BRAM0EADDR: load = BRAM0EADDR, type = ro, optional = yes; - BANKRAM0E: load = BRAM0E, type = rw, define = yes, optional = yes; - BRAM0FADDR: load = BRAM0FADDR, type = ro, optional = yes; - BANKRAM0F: load = BRAM0F, type = rw, define = yes, optional = yes; + INIT: load = MAIN, type = rw, optional = yes; + ONCE: load = MAIN, type = ro, define = yes; + BSS: load = BSS, type = bss, define = yes; + BRAM01ADDR: load = BRAM01ADDR, type = ro, optional = yes; + BANKRAM01: load = BRAM01, type = rw, optional = yes, define = yes; + BRAM02ADDR: load = BRAM02ADDR, type = ro, optional = yes; + BANKRAM02: load = BRAM02, type = rw, optional = yes, define = yes; + BRAM03ADDR: load = BRAM03ADDR, type = ro, optional = yes; + BANKRAM03: load = BRAM03, type = rw, optional = yes, define = yes; + BRAM04ADDR: load = BRAM04ADDR, type = ro, optional = yes; + BANKRAM04: load = BRAM04, type = rw, optional = yes, define = yes; + BRAM05ADDR: load = BRAM05ADDR, type = ro, optional = yes; + BANKRAM05: load = BRAM05, type = rw, optional = yes, define = yes; + BRAM06ADDR: load = BRAM06ADDR, type = ro, optional = yes; + BANKRAM06: load = BRAM06, type = rw, optional = yes, define = yes; + BRAM07ADDR: load = BRAM07ADDR, type = ro, optional = yes; + BANKRAM07: load = BRAM07, type = rw, optional = yes, define = yes; + BRAM08ADDR: load = BRAM08ADDR, type = ro, optional = yes; + BANKRAM08: load = BRAM08, type = rw, optional = yes, define = yes; + BRAM09ADDR: load = BRAM09ADDR, type = ro, optional = yes; + BANKRAM09: load = BRAM09, type = rw, optional = yes, define = yes; + BRAM0AADDR: load = BRAM0AADDR, type = ro, optional = yes; + BANKRAM0A: load = BRAM0A, type = rw, optional = yes, define = yes; + BRAM0BADDR: load = BRAM0BADDR, type = ro, optional = yes; + BANKRAM0B: load = BRAM0B, type = rw, optional = yes, define = yes; + BRAM0CADDR: load = BRAM0CADDR, type = ro, optional = yes; + BANKRAM0C: load = BRAM0C, type = rw, optional = yes, define = yes; + BRAM0DADDR: load = BRAM0DADDR, type = ro, optional = yes; + BANKRAM0D: load = BRAM0D, type = rw, optional = yes, define = yes; + BRAM0EADDR: load = BRAM0EADDR, type = ro, optional = yes; + BANKRAM0E: load = BRAM0E, type = rw, optional = yes, define = yes; + BRAM0FADDR: load = BRAM0FADDR, type = ro, optional = yes; + BANKRAM0F: load = BRAM0F, type = rw, optional = yes, define = yes; } FEATURES { CONDES: type = constructor, diff --git a/cfg/cx16.cfg b/cfg/cx16.cfg index 72fc2fe91..4b6025fb6 100644 --- a/cfg/cx16.cfg +++ b/cfg/cx16.cfg @@ -16,17 +16,17 @@ MEMORY { } SEGMENTS { ZEROPAGE: load = ZP, type = zp; - EXTZP: load = ZP, type = zp, optional = yes; + EXTZP: load = ZP, type = zp, optional = yes; LOADADDR: load = LOADADDR, type = ro; EXEHDR: load = HEADER, type = ro; - STARTUP: load = MAIN, type = ro; - LOWCODE: load = MAIN, type = ro, optional = yes; + STARTUP: load = MAIN, type = ro, optional = yes; + LOWCODE: load = MAIN, type = ro, optional = yes; CODE: load = MAIN, type = ro; RODATA: load = MAIN, type = ro; DATA: load = MAIN, type = rw; - INIT: load = MAIN, type = rw; - ONCE: load = MAIN, type = ro, define = yes; - BSS: load = BSS, type = bss, define = yes; + INIT: load = MAIN, type = rw, optional = yes; + ONCE: load = MAIN, type = ro, define = yes; + BSS: load = BSS, type = bss, define = yes; } FEATURES { CONDES: type = constructor,