diff --git a/asminc/lynx.inc b/asminc/lynx.inc index 0d34e1c7c..d6a8cd70a 100644 --- a/asminc/lynx.inc +++ b/asminc/lynx.inc @@ -83,7 +83,7 @@ MATHJ = $FC6F SPRCTL0 = $FC80 ; Sprite bits-per-pixel definitions -BPP_MASK = %11000000 ; Mask for settings bits per pixel +BPP_MASK = %11000000 ; Mask for settings bits per pixel BPP_1 = %00000000 BPP_2 = %01000000 BPP_3 = %10000000 @@ -94,23 +94,23 @@ VFLIP = %00010000 ; Sprite types - redefined to reflect the reality caused by the shadow error TYPE_SHADOW = %00000111 TYPE_XOR = %00000110 -TYPE_NONCOLL = %00000101 ; Non-colliding +TYPE_NONCOLL = %00000101 ; Non-colliding TYPE_NORMAL = %00000100 TYPE_BOUNDARY = %00000011 -TYPE_BSHADOW = %00000010 ; Background shadow -TYPE_BACKNONCOLL = %00000001 ; Background non-colliding +TYPE_BSHADOW = %00000010 ; Background shadow +TYPE_BACKNONCOLL = %00000001 ; Background non-colliding TYPE_BACKGROUND = %00000000 SPRCTL1 = $FC81 LITERAL = %10000000 PACKED = %00000000 -ALGO3 = %01000000 ; Broken, do not set this bit! +ALGO3 = %01000000 ; Broken, do not set this bit! ; Sprite reload mask definitions RELOAD_MASK = %00110000 -RENONE = %00000000 ; Reload nothing -REHV = %00010000 ; Reload hsize, vsize -REHVS = %00100000 ; Reload hsize, vsize, stretch -REHVST = %00110000 ; Reload hsize, vsize, stretch, tilt +RENONE = %00000000 ; Reload nothing +REHV = %00010000 ; Reload hsize, vsize +REHVS = %00100000 ; Reload hsize, vsize, stretch +REHVST = %00110000 ; Reload hsize, vsize, stretch, tilt ; More sprite control 1 bit definitions REUSEPAL = %00001000 SKIP = %00000100 @@ -138,8 +138,9 @@ HOWIE = $FCC4 ; *** Mikey Addresses ; *** -; Mikey Timers +; Mikey timers +; Logical timer names TIMER0 = $FD00 TIMER1 = $FD04 TIMER2 = $FD08 @@ -148,20 +149,20 @@ TIMER4 = $FD10 TIMER5 = $FD14 TIMER6 = $FD18 TIMER7 = $FD1C -HTIMER = $FD00 ; horizontal line timer (timer 0) -VTIMER = $FD08 ; vertical blank timer (timer 2) -STIMER = $FD1C ; sound timer (timer 7) +HTIMER = TIMER0 ; horizontal line timer (timer 0) +VTIMER = TIMER2 ; vertical blank timer (timer 2) +STIMER = TIMER7 ; sound timer (timer 7) -HTIMBKUP = $FD00 ; horizontal line timer (timer 0) +HTIMBKUP = $FD00 ; horizontal line timer (timer 0) HTIMCTLA = $FD01 HTIMCNT = $FD02 HTIMCTLB = $FD03 -VTIMBKUP = $FD08 ; vertical blank timer (timer 2) +VTIMBKUP = $FD08 ; vertical blank timer (timer 2) VTIMCTLA = $FD09 VTIMCNT = $FD0A VTIMCTLB = $FD0B -BAUDBKUP = $FD10 ; serial timer (timer 4) -STIMBKUP = $FD1C ; sound timer (timer 7) +BAUDBKUP = $FD10 ; serial timer (timer 4) +STIMBKUP = $FD1C ; sound timer (timer 7) STIMCTLA = $FD1D STIMCNT = $FD1E STIMCTLB = $FD1F @@ -199,129 +200,227 @@ TIM7CTLA = $FD1D TIM7CNT = $FD1E TIM7CTLB = $FD1F +; Timer offsets +TIM_BACKUP = 0 +TIM_CONTROLA = 1 +TIM_COUNT = 2 +TIM_CONTROLB = 3 + +; TIM_CONTROLA control bits +ENABLE_INT = %10000000 +RESET_DONE = %01000000 +ENABLE_RELOAD = %00010000 +ENABLE_COUNT = %00001000 +AUD_CLOCK_MASK = %00000111 + +; Clock settings +AUD_LINKING = %00000111 +AUD_64 = %00000110 +AUD_32 = %00000101 +AUD_16 = %00000100 +AUD_8 = %00000011 +AUD_4 = %00000010 +AUD_2 = %00000001 +AUD_1 = %00000000 + +; TIM_CONTROLB control bits +TIMER_DONE = %00001000 +LAST_CLOCK = %00000100 +BORROW_IN = %00000010 +BORROW_OUT = %00000001 + ; Mikey Audio -AUDIO0 = $FD20 ; audio channel 0 -AUDIO1 = $FD28 ; audio channel 1 -AUDIO2 = $FD30 ; audio channel 2 -AUDIO3 = $FD38 ; audio channel 3 +AUDIO0 = $FD20 ; audio channel 0 +AUDIO1 = $FD28 ; audio channel 1 +AUDIO2 = $FD30 ; audio channel 2 +AUDIO3 = $FD38 ; audio channel 3 -AUD0VOL = $FD20 -AUD0FEED = $FD21 -AUD0OUT = $FD22 -AUD0SHIFT = $FD23 -AUD0BKUP = $FD24 -AUD0CTLA = $FD25 -AUD0CNT = $FD26 -AUD0CTLB = $FD27 -AUD1VOL = $FD28 -AUD1FEED = $FD29 -AUD1OUT = $FD2A -AUD1SHIFT = $FD2B -AUD1BKUP = $FD2C -AUD1CTLA = $FD2D -AUD1CNT = $FD2E -AUD1CTLB = $FD2F -AUD2VOL = $FD30 -AUD2FEED = $FD31 -AUD2OUT = $FD32 -AUD2SHIFT = $FD33 -AUD2BKUP = $FD34 -AUD2CTLA = $FD35 -AUD2CNT = $FD36 -AUD2CTLB = $FD37 -AUD3VOL = $FD38 -AUD3FEED = $FD39 -AUD3OUT = $FD3A -AUD3SHIFT = $FD3B -AUD3BKUP = $FD3C -AUD3CTLA = $FD3D -AUD3CNT = $FD3E -AUD3CTLB = $FD3F +AUD0VOL = $FD20 +AUD0FEED = $FD21 +AUD0OUT = $FD22 +AUD0SHIFT = $FD23 +AUD0BKUP = $FD24 +AUD0CTLA = $FD25 +AUD0CNT = $FD26 +AUD0CTLB = $FD27 +AUD1VOL = $FD28 +AUD1FEED = $FD29 +AUD1OUT = $FD2A +AUD1SHIFT = $FD2B +AUD1BKUP = $FD2C +AUD1CTLA = $FD2D +AUD1CNT = $FD2E +AUD1CTLB = $FD2F +AUD2VOL = $FD30 +AUD2FEED = $FD31 +AUD2OUT = $FD32 +AUD2SHIFT = $FD33 +AUD2BKUP = $FD34 +AUD2CTLA = $FD35 +AUD2CNT = $FD36 +AUD2CTLB = $FD37 +AUD3VOL = $FD38 +AUD3FEED = $FD39 +AUD3OUT = $FD3A +AUD3SHIFT = $FD3B +AUD3BKUP = $FD3C +AUD3CTLA = $FD3D +AUD3CNT = $FD3E +AUD3CTLB = $FD3F + +; AUD_CONTROL bits are almost identical to TIM_CONTROLA bits. +; See TIM_CONTROLA above for the other definitions +FEEDBACK_7 = %10000000 +ENABLE_INTEGRATE = %00100000 + +; Stereo control registers follow +; Stereo capability does not exist in all Lynxes +; Left and right may be reversed, and if so will be corrected in a later +; release + +ATTENREG0 = $FD40 ; Stereo attenuation registers +ATTENREG1 = $FD41 +ATTENREG2 = $FD42 +ATTENREG3 = $FD43 +LEFT_ATTENMASK = %11110000 +RIGHT_ATTENMASK = %00001111 + +; Bit definitions for MPAN and MSTEREO registers +LEFT3_SELECT = %10000000 +LEFT2_SELECT = %01000000 +LEFT1_SELECT = %00100000 +LEFT0_SELECT = %00010000 +RIGHT3_SELECT = %00001000 +RIGHT2_SELECT = %00000100 +RIGHT1_SELECT = %00000010 +RIGHT0_SELECT = %00000001 + +MPAN = $FD44 MSTEREO = $FD50 -; Mikey Misc - -; Interrupt bits in INTRST and INTSET -TIMER0_INTERRUPT = $01 -TIMER1_INTERRUPT = $02 -TIMER2_INTERRUPT = $04 -TIMER3_INTERRUPT = $08 -TIMER4_INTERRUPT = $10 -TIMER5_INTERRUPT = $20 -TIMER6_INTERRUPT = $40 -TIMER7_INTERRUPT = $80 - -HBL_INTERRUPT = TIMER0_INTERRUPT -VBL_INTERRUPT = TIMER2_INTERRUPT -SERIAL_INTERRUPT = TIMER4_INTERRUPT -SND_INTERRUPT = TIMER7_INTERRUPT +; Mikey interrupts INTRST = $FD80 INTSET = $FD81 -MAGRDY0 = $FD84 -MAGRDY1 = $FD85 -AUDIN = $FD86 -SYSCTL1 = $FD87 -MIKEYHREV = $FD88 -MIKEYSREV = $FD89 +; Interrupt bits in INTRST and INTSET +TIMER0_INTERRUPT = %00000001 +TIMER1_INTERRUPT = %00000010 +TIMER2_INTERRUPT = %00000100 +TIMER3_INTERRUPT = %00001000 +TIMER4_INTERRUPT = %00010000 +TIMER5_INTERRUPT = %00100000 +TIMER6_INTERRUPT = %01000000 +TIMER7_INTERRUPT = %10000000 -IODIR = $FD8A -IODAT = $FD8B +HBL_INTERRUPT = TIMER0_INTERRUPT +VBL_INTERRUPT = TIMER2_INTERRUPT +SERIAL_INTERRUPT = TIMER4_INTERRUPT +SND_INTERRUPT = TIMER7_INTERRUPT + +MAGRDY0 = $FD84 +MAGRDY1 = $FD85 +AUDIN = $FD86 +SYSCTL1 = $FD87 +; SYSCTL1 bit definitions +POWERON = %00000010 +CART_ADDR_STROBE = %00000001 + +MIKEYHREV = $FD88 +MIKEYSREV = $FD89 + +IODIR = $FD8A +IODAT = $FD8B ; IODIR and IODAT bit definitions -AUDIN_BIT = $10 ; Note that there is also the address AUDIN -READ_ENABLE = $10 ; Same bit for AUDIN_BIT -RESTLESS = $08 -NOEXP = $04 ; If set, redeye is not connected -CART_ADDR_DATA = $02 -CART_POWER_OFF = $02 ; Same bit for CART_ADDR_DATA -EXTERNAL_POWER = $01 +AUDIN_BIT = %00010000 ; Note that there is also the address AUDIN +READ_ENABLE = %00010000 ; Same bit for AUDIN_BIT +RESTLESS = %00001000 +NOEXP = %00000100 ; If set, redeye is not connected +CART_ADDR_DATA = %00000010 +CART_POWER_OFF = %00000010 ; Same bit for CART_ADDR_DATA +EXTERNAL_POWER = %00000001 -SERCTL = $FD8C +SERCTL = $FD8C ; SERCTL bit definitions for write operations -TXINTEN = $80 -RXINTEN = $40 -PAREN = $10 -RESETERR = $08 -TXOPEN = $04 -TXBRK = $02 -PAREVEN = $01 +TXINTEN = %10000000 +RXINTEN = %01000000 +PAREN = %00010000 +RESETERR = %00001000 +TXOPEN = %00000100 +TXBRK = %00000010 +PAREVEN = %00000001 ; SERCTL bit definitions for read operations -TXRDY = $80 -RXRDY = $40 -TXEMPTY = $20 -PARERR = $10 -OVERRUN = $08 -FRAMERR = $04 -RXBRK = $02 -PARBIT = $01 +TXRDY = %10000000 +RXRDY = %01000000 +TXEMPTY = %00100000 +PARERR = %00010000 +OVERRUN = %00001000 +FRAMERR = %00000100 +RXBRK = %00000010 +PARBIT = %00000001 -SERDAT = $FD8D -SDONEACK = $FD90 -CPUSLEEP = $FD91 -DISPCTL = $FD92 -PBKUP = $FD93 -DISPADRL = $FD94 -DISPADRH = $FD95 -MTEST0 = $FD9C -MTEST1 = $FD9D -MTEST2 = $FD9E -PALETTE = $FDA0 ; hardware rgb palette -GCOLMAP = $FDA0 ; hardware rgb palette (green) -RBCOLMAP = $FDB0 ; hardware rgb palette (red-blue) +SERDAT = $FD8D +SDONEACK = $FD90 +CPUSLEEP = $FD91 +DISPCTL = $FD92 +; DISPCTL bit definitions +DISP_COLOR = %10000000 ; must be set to 1 +DISP_FOURBIT = %01000000 ; must be set to 1 +DISP_FLIP = %00100000 +DMA_ENABLE = %00010000 ; must be set to 1 +PBKUP = $FD93 +DISPADRL = $FD94 +DISPADRH = $FD95 -; *** -; *** Misc Hardware + 6502 vectors -; *** +MTEST0 = $FD9C +; MTEST0 bit definitions +AT_CNT16 = %10000000 +AT_TEST = %01000000 +XCLKEN = %00100000 +UART_TURBO = %00010000 +ROM_SEL = %00001000 +ROM_TEST = %00000100 +M_TEST = %00000010 +CPU_TEST = %00000001 -MAPCTL = $FFF9 -VECTORS = $FFFB -INTVECTL = $FFFE -INTVECTH = $FFFF -RSTVECTL = $FFFC -RSTVECTH = $FFFD -NMIVECTL = $FFFA -NMIVECTH = $FFFB +MTEST1 = $FD9D +; MTEST1 bit definitions +P_CNT16 = %01000000 +REF_CNT16 = %00100000 +VID_TRIG = %00010000 +REF_TRIG = %00001000 +VID_DMA_DIS = %00000100 +REF_FAST = %00000010 +REF_DIS = %00000001 +MTEST2 = $FD9E +; MTEST2 bit definitions +V_STROBE = %00010000 +V_ZERO = %00001000 +H_120 = %00000100 +H_ZERO = %00000010 +V_BLANKEF = %00000001 + +PALETTE = $FDA0 ; hardware rgb palette +GCOLMAP = $FDA0 ; hardware rgb palette (green) +RBCOLMAP = $FDB0 ; hardware rgb palette (red-blue) + +; Memory mapping control and 6502 vectors + +MAPCTL = $FFF9 +; MAPCTL bit definitions +TURBO_DISABLE = %10000000 +VECTOR_SPACE = %00001000 ; 1 maps RAM into specified space +ROM_SPACE = %00000100 +MIKEY_SPACE = %00000010 +SUZY_SPACE = %00000001 + +VECTORS = $FFFB +INTVECTL = $FFFE +INTVECTH = $FFFF +RSTVECTL = $FFFC +RSTVECTH = $FFFD +NMIVECTL = $FFFA +NMIVECTH = $FFFB diff --git a/include/_mikey.h b/include/_mikey.h index b9b7f6906..9a50745b2 100644 --- a/include/_mikey.h +++ b/include/_mikey.h @@ -27,7 +27,7 @@ #ifndef __MIKEY_H #define __MIKEY_H -/* timer structure */ +/* Timer structure */ typedef struct _mikey_timer { unsigned char reload; unsigned char control; @@ -39,7 +39,7 @@ typedef struct _mikey_all_timers { struct _mikey_timer timer[8]; } _mikey_all_timers; -/* audio channel structure */ +/* Audio channel structure */ typedef struct _mikey_audio { unsigned char volume; unsigned char feedback; @@ -53,54 +53,213 @@ typedef struct _mikey_audio { /* Define a structure with the mikey register offsets */ struct __mikey { - struct _mikey_timer timer0; // 0xFD00 - struct _mikey_timer timer1; // 0xFD04 - struct _mikey_timer timer2; // 0xFD08 - struct _mikey_timer timer3; // 0xFD0C - struct _mikey_timer timer4; // 0xFD10 - struct _mikey_timer timer5; // 0xFD14 - struct _mikey_timer timer6; // 0xFD18 - struct _mikey_timer timer7; // 0xFD1C - struct _mikey_audio channel_a; // 0xFD20 - struct _mikey_audio channel_b; // 0xFD28 - struct _mikey_audio channel_c; // 0xFD30 - struct _mikey_audio channel_d; // 0xFD38 - unsigned char attena; // 0xFD40 ?? not yet allocated? - unsigned char attenb; // 0xFD41 | - unsigned char attenc; // 0xFD42 | - unsigned char attend; // 0xFD43 | - unsigned char panning; // 0xFD44 | - unsigned char unused0[11]; // 0xFD45 - 0xFD4F not used - unsigned char mstereo; // 0xFD50 stereo control bits - unsigned char unused1[47]; // 0xFD51 - 0xFD7F not used - unsigned char intrst; // 0xFD80 interrupt poll 0 - unsigned char intset; // 0xFD81 interrupt poll 1 - unsigned char unused2[2]; // 0xFD82 - 0xFD83 not used - unsigned char magrdy0; // 0xFD84 mag tape channel0 ready bit - unsigned char magrdy1; // 0xFD85 mag tape channel1 ready bit - unsigned char audin; // 0xFD86 audio in - unsigned char sysctl1; // 0xFD87 control bits - unsigned char mikeyrev; // 0xFD88 mikey hardware rev - unsigned char mikeysrev; // 0xFD89 mikey software rev - unsigned char iodir; // 0xFD8A parallel i/o data dir - unsigned char iodat; // 0xFD8B parallel data - unsigned char serctl; // 0xFD8C serial control register - unsigned char serdat; // 0xFD8D serial data - unsigned char unused3[2]; // 0xFD8E - 0xFD8F not used - unsigned char sdoneack; // 0xFD90 suzy done acknowledge - unsigned char cpusleep; // 0xFD91 cpu bus request disable - unsigned char dispctl; // 0xFD92 video bus request enable, viddma - unsigned char pkbkup; // 0xFD93 magic 'P' count - unsigned char *scrbase; // 0xFD94 start address of video display - unsigned char unused4[6]; // 0xFD96 - 0xFD9B not used - unsigned char mtest0; // 0xFD9C - unsigned char mtest1; // 0xFD9D - unsigned char mtest2; // 0xFD9E - unsigned char unused5; // 0xFD9F not used - unsigned char palette[32]; // 0xFDA0 - 0xFDBF palette 32 bytes - // 0xFDC0 - 0xFDFF not used + struct _mikey_timer timer0; // 0xFD00 + struct _mikey_timer timer1; // 0xFD04 + struct _mikey_timer timer2; // 0xFD08 + struct _mikey_timer timer3; // 0xFD0C + struct _mikey_timer timer4; // 0xFD10 + struct _mikey_timer timer5; // 0xFD14 + struct _mikey_timer timer6; // 0xFD18 + struct _mikey_timer timer7; // 0xFD1C + struct _mikey_audio channel_a; // 0xFD20 + struct _mikey_audio channel_b; // 0xFD28 + struct _mikey_audio channel_c; // 0xFD30 + struct _mikey_audio channel_d; // 0xFD38 + unsigned char attena; // 0xFD40 ?? not yet allocated? + unsigned char attenb; // 0xFD41 | + unsigned char attenc; // 0xFD42 | + unsigned char attend; // 0xFD43 | + unsigned char panning; // 0xFD44 | + unsigned char unused0[11]; // 0xFD45 - 0xFD4F not used + unsigned char mstereo; // 0xFD50 stereo control bits + unsigned char unused1[47]; // 0xFD51 - 0xFD7F not used + unsigned char intrst; // 0xFD80 interrupt poll 0 + unsigned char intset; // 0xFD81 interrupt poll 1 + unsigned char unused2[2]; // 0xFD82 - 0xFD83 not used + unsigned char magrdy0; // 0xFD84 mag tape channel0 ready bit + unsigned char magrdy1; // 0xFD85 mag tape channel1 ready bit + unsigned char audin; // 0xFD86 audio in + unsigned char sysctl1; // 0xFD87 control bits + unsigned char mikeyrev; // 0xFD88 mikey hardware rev + unsigned char mikeysrev; // 0xFD89 mikey software rev + unsigned char iodir; // 0xFD8A parallel i/o data dir + unsigned char iodat; // 0xFD8B parallel data + unsigned char serctl; // 0xFD8C serial control register + unsigned char serdat; // 0xFD8D serial data + unsigned char unused3[2]; // 0xFD8E - 0xFD8F not used + unsigned char sdoneack; // 0xFD90 suzy done acknowledge + unsigned char cpusleep; // 0xFD91 cpu bus request disable + unsigned char dispctl; // 0xFD92 video bus request enable, viddma + unsigned char pkbkup; // 0xFD93 magic 'P' count + unsigned char *scrbase; // 0xFD94 start address of video display + unsigned char unused4[6]; // 0xFD96 - 0xFD9B not used + unsigned char mtest0; // 0xFD9C + unsigned char mtest1; // 0xFD9D + unsigned char mtest2; // 0xFD9E + unsigned char unused5; // 0xFD9F not used + unsigned char palette[32]; // 0xFDA0 - 0xFDBF palette 32 bytes + unsigned char unused6[64]; // 0xFDC0 - 0xFDFF not used + unsigned char bootrom[504]; // 0xFE00 - 0xFFD8 boot rom + unsigned char reserved; // 0xFFD8 reserved for future hardware + unsigned char mapctl; // 0xFFF9 map control register + struct { + unsigned char *nmi; // 0xFFFA NMI vector + unsigned char *reset; // 0xFFFB reset vector + unsigned char *irq; // 0xFFFC IRQ vector + } vectors; }; +// TIM_CONTROLA control bit definitions +enum { + ENABLE_INT = 0x80, + RESET_DONE = 0x40, + ENABLE_RELOAD = 0x10, + ENABLE_COUNT = 0x08 +}; + +// AUD_CONTROL control bit definitions +enum { + FEEDBACK_7 = 0x80, + ENABLE_INTEGRATE = 0x20 +}; + +// Audio and timer clock settings for source period +enum { + AUD_LINKING = 0x07, + AUD_64 = 0x06, + AUD_32 = 0x05, + AUD_16 = 0x04, + AUD_8 = 0x03, + AUD_4 = 0x02, + AUD_2 = 0x01, + AUD_1 = 0x00 +}; + +// TIM_CONTROLB control bit definitions +enum { + TIMER_DONE = 0x08, + LAST_CLOCK = 0x04, + BORROW_IN = 0x02, + BORROW_OUT = 0x01 +}; + +// MPAN and MSTEREO registers bit definitions +enum { + LEFT3_SELECT = 0x80, + LEFT2_SELECT = 0x40, + LEFT1_SELECT = 0x20, + LEFT0_SELECT = 0x10, + RIGHT3_SELECT = 0x08, + RIGHT2_SELECT = 0x04, + RIGHT1_SELECT = 0x02, + RIGHT0_SELECT = 0x01, + LEFT_ATTENMASK = 0xF0, + RIGHT_ATTENMASK = 0x0F +}; + +// Interrupt Reset and Set bit definitions +enum { + TIMER7_INT = 0x80, + TIMER6_INT = 0x40, + TIMER5_INT = 0x20, + TIMER4_INT = 0x10, + TIMER3_INT = 0x08, + TIMER2_INT = 0x04, + TIMER1_INT = 0x02, + TIMER0_INT = 0x01, + SERIAL_INT = TIMER4_INT, + VERTICAL_INT = TIMER2_INT, + HORIZONTAL_INT = TIMER0_INT +}; + +// SYSCTL1 bit definitions +enum { + POWERON = 0x02, + CART_ADDR_STROBE = 0x01 +}; + +// IODIR and IODAT bit definitions +enum { + AUDIN_BIT = 0x10, // different from AUDIN address + READ_ENABLE = 0x10, // same bit for AUDIN_BIT + RESTLESS = 0x08, + NOEXP = 0x04, // if set, redeye is not connected + CART_ADDR_DATA = 0x02, // + CART_POWER_OFF = 0x02, // same bit for CART_ADDR_DATA + EXTERNAL_POWER = 0x01 +}; + +// SERCTL bit definitions for write operations +enum { + TXINTEN = 0x80, + RXINTEN = 0x40, + PAREN = 0x10, + RESETERR = 0x08, + TXOPEN = 0x04, + TXBRK = 0x02, + PAREVEN = 0x01 +}; + +// SERCTL bit definitions for read operations +enum { + TXRDY = 0x80, + RXRDY = 0x40, + TXEMPTY = 0x20, + PARERR = 0x10, + OVERRUN = 0x08, + FRAMERR = 0x04, + RXBRK = 0x02, + PARBIT = 0x01 +}; + +// DISPCTL bit definitions +enum { + DISP_COLOR = 0x08, // must be set to 1 + DISP_FOURBIT = 0x04, // must be set to 1 + DISP_FLIP = 0x02, // + DMA_ENABLE = 0x01 // must be set to 1 +}; + +// MTEST0 bit definitions +enum { + AT_CNT16 = 0x80, + AT_TEST = 0x40, + XCLKEN = 0x20, + UART_TURBO = 0x10, + ROM_SEL = 0x08, + ROM_TEST = 0x04, + M_TEST = 0x02, + CPU_TEST = 0x01 +}; + +// MTEST1 bit definitions +enum { + P_CNT16 = 0x40, + REF_CNT16 = 0x20, + VID_TRIG = 0x10, + REF_TRIG = 0x08, + VID_DMA_DIS = 0x04, + REF_FAST = 0x02, + REF_DIS = 0x01 +}; + +// MTEST2 bit definitions +enum { + V_STROBE = 0x10, + V_ZERO = 0x08, + H_120 = 0x04, + H_ZERO = 0x02, + V_BLANKEF = 0x01 +}; + +// MAPCTL bit definitions +enum { + TURBO_DISABLE = 0x80, + VECTOR_SPACE = 0x08, + ROM_SPACE = 0x04, + MIKEY_SPACE = 0x02, + SUZY_SPACE = 0x01 +}; #endif