Fixed cycle counting and finished 2.0
* Added rules for branch taken/not taken * Fixed incorrect adding of cycles for many ALU instructions * Fixed timing for ASL, DEC, INC, LSR, ROL, and ROR * Renamed global opcode_table to g_opcode_table * Normalized all hex output to be capitals
This commit is contained in:
Tennessee Carmel-Veilleux
parent
d8869a8d28
commit
aa6c897c1a
221
dcc6502.c
221
dcc6502.c
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@ -34,6 +34,10 @@
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#define VERSION_INFO "v2.0"
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#define NUMBER_OPCODES 151
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/* Exceptions for cycle counting */
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#define CYCLES_CROSS_PAGE_ADDS_ONE (1 << 0)
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#define CYCLES_BRANCH_TAKEN_ADDS_ONE (1 << 1)
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/* The 6502's 13 addressing modes */
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typedef enum {
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IMMED = 0, /* Immediate */
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@ -61,7 +65,7 @@ typedef struct opcode_s {
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const char *mnemonic; /* Index in the name table */
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addressing_mode_e addressing; /* Addressing mode */
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unsigned int cycles; /* Number of cycles */
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unsigned int cross_page; /* 1 if cross-page boundaries affect cycles */
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unsigned int cycles_exceptions; /* Mask of cycle-counting exceptions */
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} opcode_t;
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typedef struct options_s {
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@ -73,53 +77,52 @@ typedef struct options_s {
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uint16_t org; /* Origin of addresses */
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} options_t;
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/* Opcode table */
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opcode_t opcode_table[NUMBER_OPCODES] = {
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{0x69, "ADC", IMMED, 2, 1}, /* ADC */
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{0x65, "ADC", ZEROP, 3, 1},
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{0x75, "ADC", ZEPIX, 4, 1},
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{0x6D, "ADC", ABSOL, 4, 1},
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{0x7D, "ADC", ABSIX, 4, 1},
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{0x79, "ADC", ABSIY, 4, 1},
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{0x61, "ADC", INDIN, 6, 1},
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{0x71, "ADC", ININD, 5, 1},
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static opcode_t g_opcode_table[NUMBER_OPCODES] = {
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{0x69, "ADC", IMMED, 2, 0}, /* ADC */
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{0x65, "ADC", ZEROP, 3, 0},
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{0x75, "ADC", ZEPIX, 4, 0},
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{0x6D, "ADC", ABSOL, 4, 0},
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{0x7D, "ADC", ABSIX, 4, CYCLES_CROSS_PAGE_ADDS_ONE},
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{0x79, "ADC", ABSIY, 4, CYCLES_CROSS_PAGE_ADDS_ONE},
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{0x61, "ADC", INDIN, 6, 0},
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{0x71, "ADC", ININD, 5, CYCLES_CROSS_PAGE_ADDS_ONE},
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{0x29, "AND", IMMED, 2, 1}, /* AND */
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{0x25, "AND", ZEROP, 3, 1},
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{0x35, "AND", ZEPIX, 4, 1},
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{0x2D, "AND", ABSOL, 4, 1},
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{0x3D, "AND", ABSIX, 4, 1},
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{0x39, "AND", ABSIY, 4, 1},
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{0x21, "AND", INDIN, 6, 1},
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{0x31, "AND", ININD, 5, 1},
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{0x29, "AND", IMMED, 2, 0}, /* AND */
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{0x25, "AND", ZEROP, 3, 0},
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{0x35, "AND", ZEPIX, 4, 0},
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{0x2D, "AND", ABSOL, 4, 0},
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{0x3D, "AND", ABSIX, 4, CYCLES_CROSS_PAGE_ADDS_ONE},
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{0x39, "AND", ABSIY, 4, CYCLES_CROSS_PAGE_ADDS_ONE},
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{0x21, "AND", INDIN, 6, 0},
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{0x31, "AND", ININD, 5, CYCLES_CROSS_PAGE_ADDS_ONE},
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{0x0A, "ASL", ACCUM, 2, 0}, /* ASL */
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{0x06, "ASL", ZEROP, 5, 0},
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{0x16, "ASL", ZEPIX, 6, 0},
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{0x0E, "ASL", ABSOL, 6, 0},
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{0x1E, "ASL", ABSIX, 6, 0},
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{0x1E, "ASL", ABSIX, 7, 0},
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{0x90, "BCC", RELAT, 4, 1}, /* BCC */
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{0x90, "BCC", RELAT, 2, CYCLES_CROSS_PAGE_ADDS_ONE | CYCLES_BRANCH_TAKEN_ADDS_ONE}, /* BCC */
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{0xB0, "BCS", RELAT, 4, 1}, /* BCS */
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{0xB0, "BCS", RELAT, 2, CYCLES_CROSS_PAGE_ADDS_ONE | CYCLES_BRANCH_TAKEN_ADDS_ONE}, /* BCS */
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{0xF0, "BEQ", RELAT, 4, 1}, /* BEQ */
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{0xF0, "BEQ", RELAT, 2, CYCLES_CROSS_PAGE_ADDS_ONE | CYCLES_BRANCH_TAKEN_ADDS_ONE}, /* BEQ */
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{0x24, "BIT", ZEROP, 3, 0}, /* BIT */
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{0x2C, "BIT", ABSOL, 4, 0},
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{0x30, "BMI", RELAT, 4, 1}, /* BMI */
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{0x30, "BMI", RELAT, 2, CYCLES_CROSS_PAGE_ADDS_ONE | CYCLES_BRANCH_TAKEN_ADDS_ONE}, /* BMI */
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{0xD0, "BNE", RELAT, 4, 1}, /* BNE */
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{0xD0, "BNE", RELAT, 2, CYCLES_CROSS_PAGE_ADDS_ONE | CYCLES_BRANCH_TAKEN_ADDS_ONE}, /* BNE */
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{0x10, "BPL", RELAT, 4, 1}, /* BPL */
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{0x10, "BPL", RELAT, 2, CYCLES_CROSS_PAGE_ADDS_ONE | CYCLES_BRANCH_TAKEN_ADDS_ONE}, /* BPL */
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{0x00, "BRK", IMPLI, 7, 0}, /* BRK */
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{0x50, "BVC", RELAT, 4, 1}, /* BVC */
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{0x50, "BVC", RELAT, 2, CYCLES_CROSS_PAGE_ADDS_ONE | CYCLES_BRANCH_TAKEN_ADDS_ONE}, /* BVC */
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{0x70, "BVS", RELAT, 4, 1}, /* BVS */
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{0x70, "BVS", RELAT, 2, CYCLES_CROSS_PAGE_ADDS_ONE | CYCLES_BRANCH_TAKEN_ADDS_ONE}, /* BVS */
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{0x18, "CLC", IMPLI, 2, 0}, /* CLC */
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@ -133,10 +136,10 @@ opcode_t opcode_table[NUMBER_OPCODES] = {
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{0xC5, "CMP", ZEROP, 3, 0},
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{0xD5, "CMP", ZEPIX, 4, 0},
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{0xCD, "CMP", ABSOL, 4, 0},
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{0xDD, "CMP", ABSIX, 4, 0},
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{0xD9, "CMP", ABSIY, 4, 0},
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{0xDD, "CMP", ABSIX, 4, CYCLES_CROSS_PAGE_ADDS_ONE},
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{0xD9, "CMP", ABSIY, 4, CYCLES_CROSS_PAGE_ADDS_ONE},
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{0xC1, "CMP", INDIN, 6, 0},
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{0xD1, "CMP", ININD, 5, 0},
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{0xD1, "CMP", ININD, 5, CYCLES_CROSS_PAGE_ADDS_ONE},
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{0xE0, "CPX", IMMED, 2, 0}, /* CPX */
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{0xE4, "CPX", ZEROP, 3, 0},
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@ -149,25 +152,25 @@ opcode_t opcode_table[NUMBER_OPCODES] = {
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{0xC6, "DEC", ZEROP, 5, 0}, /* DEC */
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{0xD6, "DEC", ZEPIX, 6, 0},
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{0xCE, "DEC", ABSOL, 6, 0},
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{0xDE, "DEC", ABSIX, 6, 0},
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{0xDE, "DEC", ABSIX, 7, 0},
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{0xCA, "DEX", IMPLI, 2, 0}, /* DEX */
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{0x88, "DEY", IMPLI, 2, 0}, /* DEY */
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{0x49, "EOR", IMMED, 2, 1}, /* EOR */
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{0x45, "EOR", ZEROP, 3, 1},
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{0x55, "EOR", ZEPIX, 4, 1},
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{0x4D, "EOR", ABSOL, 4, 1},
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{0x5D, "EOR", ABSIX, 4, 1},
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{0x59, "EOR", ABSIY, 4, 1},
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{0x49, "EOR", IMMED, 2, 0}, /* EOR */
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{0x45, "EOR", ZEROP, 3, 0},
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{0x55, "EOR", ZEPIX, 4, 0},
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{0x4D, "EOR", ABSOL, 4, 0},
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{0x5D, "EOR", ABSIX, 4, CYCLES_CROSS_PAGE_ADDS_ONE},
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{0x59, "EOR", ABSIY, 4, CYCLES_CROSS_PAGE_ADDS_ONE},
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{0x41, "EOR", INDIN, 6, 1},
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{0x51, "EOR", ININD, 5, 1},
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{0x51, "EOR", ININD, 5, CYCLES_CROSS_PAGE_ADDS_ONE},
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{0xE6, "INC", ZEROP, 5, 0}, /* INC */
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{0xF6, "INC", ZEPIX, 6, 0},
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{0xEE, "INC", ABSOL, 6, 0},
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{0xFE, "INC", ABSIX, 6, 0},
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{0xFE, "INC", ABSIX, 7, 0},
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{0xE8, "INX", IMPLI, 2, 0}, /* INX */
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@ -178,32 +181,32 @@ opcode_t opcode_table[NUMBER_OPCODES] = {
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{0x20, "JSR", ABSOL, 6, 0}, /* JSR */
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{0xA9, "LDA", IMMED, 2, 1}, /* LDA */
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{0xA5, "LDA", ZEROP, 3, 1},
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{0xB5, "LDA", ZEPIX, 4, 1},
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{0xAD, "LDA", ABSOL, 4, 1},
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{0xBD, "LDA", ABSIX, 4, 1},
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{0xB9, "LDA", ABSIY, 4, 1},
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{0xA1, "LDA", INDIN, 6, 1},
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{0xB1, "LDA", ININD, 5, 1},
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{0xA9, "LDA", IMMED, 2, 0}, /* LDA */
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{0xA5, "LDA", ZEROP, 3, 0},
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{0xB5, "LDA", ZEPIX, 4, 0},
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{0xAD, "LDA", ABSOL, 4, 0},
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{0xBD, "LDA", ABSIX, 4, CYCLES_CROSS_PAGE_ADDS_ONE},
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{0xB9, "LDA", ABSIY, 4, CYCLES_CROSS_PAGE_ADDS_ONE},
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{0xA1, "LDA", INDIN, 6, 0},
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{0xB1, "LDA", ININD, 5, CYCLES_CROSS_PAGE_ADDS_ONE},
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{0xA2, "LDX", IMMED, 2, 1}, /* LDX */
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{0xA6, "LDX", ZEROP, 3, 1},
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{0xB6, "LDX", ZEPIY, 4, 1},
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{0xAE, "LDX", ABSOL, 4, 1},
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{0xBE, "LDX", ABSIY, 4, 1},
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{0xA2, "LDX", IMMED, 2, 0}, /* LDX */
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{0xA6, "LDX", ZEROP, 3, 0},
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{0xB6, "LDX", ZEPIY, 4, 0},
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{0xAE, "LDX", ABSOL, 4, 0},
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{0xBE, "LDX", ABSIY, 4, CYCLES_CROSS_PAGE_ADDS_ONE},
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{0xA0, "LDY", IMMED, 2, 1}, /* LDY */
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{0xA4, "LDY", ZEROP, 3, 1},
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{0xB4, "LDY", ZEPIX, 4, 1},
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{0xAC, "LDY", ABSOL, 4, 1},
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{0xBC, "LDY", ABSIX, 4, 1},
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{0xA0, "LDY", IMMED, 2, 0}, /* LDY */
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{0xA4, "LDY", ZEROP, 3, 0},
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{0xB4, "LDY", ZEPIX, 4, 0},
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{0xAC, "LDY", ABSOL, 4, 0},
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{0xBC, "LDY", ABSIX, 4, CYCLES_CROSS_PAGE_ADDS_ONE},
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{0x4A, "LSR", ACCUM, 2, 0}, /* LSR */
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{0x46, "LSR", ZEROP, 5, 0},
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{0x56, "LSR", ZEPIX, 6, 0},
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{0x4E, "LSR", ABSOL, 6, 0},
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{0x5E, "LSR", ABSIX, 6, 0},
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{0x5E, "LSR", ABSIX, 7, 0},
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{0xEA, "NOP", IMPLI, 2, 0}, /* NOP */
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@ -211,10 +214,10 @@ opcode_t opcode_table[NUMBER_OPCODES] = {
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{0x05, "ORA", ZEROP, 3, 0},
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{0x15, "ORA", ZEPIX, 4, 0},
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{0x0D, "ORA", ABSOL, 4, 0},
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{0x1D, "ORA", ABSIX, 4, 0},
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{0x19, "ORA", ABSIY, 4, 0},
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{0x1D, "ORA", ABSIX, 4, CYCLES_CROSS_PAGE_ADDS_ONE},
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{0x19, "ORA", ABSIY, 4, CYCLES_CROSS_PAGE_ADDS_ONE},
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{0x01, "ORA", INDIN, 6, 0},
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{0x11, "ORA", ININD, 5, 0},
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{0x11, "ORA", ININD, 5, CYCLES_CROSS_PAGE_ADDS_ONE},
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{0x48, "PHA", IMPLI, 3, 0}, /* PHA */
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@ -228,26 +231,26 @@ opcode_t opcode_table[NUMBER_OPCODES] = {
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{0x26, "ROL", ZEROP, 5, 0},
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{0x36, "ROL", ZEPIX, 6, 0},
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{0x2E, "ROL", ABSOL, 6, 0},
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{0x3E, "ROL", ABSIX, 6, 0},
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{0x3E, "ROL", ABSIX, 7, 0},
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{0x6A, "ROR", ACCUM, 2, 0}, /* ROR */
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{0x66, "ROR", ZEROP, 5, 0},
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{0x76, "ROR", ZEPIX, 6, 0},
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{0x6E, "ROR", ABSOL, 6, 0},
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{0x7E, "ROR", ABSIX, 6, 0},
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{0x7E, "ROR", ABSIX, 7, 0},
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{0x40, "RTI", IMPLI, 6, 0}, /* RTI */
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{0x60, "RTS", IMPLI, 6, 0}, /* RTS */
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{0xE9, "SBC", IMMED, 2, 1}, /* SBC */
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{0xE5, "SBC", ZEROP, 3, 1},
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{0xF5, "SBC", ZEPIX, 4, 1},
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{0xED, "SBC", ABSOL, 4, 1},
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{0xFD, "SBC", ABSIX, 4, 1},
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{0xF9, "SBC", ABSIY, 4, 1},
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{0xE1, "SBC", INDIN, 6, 1},
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{0xF1, "SBC", ININD, 5, 1},
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{0xE9, "SBC", IMMED, 2, 0}, /* SBC */
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{0xE5, "SBC", ZEROP, 3, 0},
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{0xF5, "SBC", ZEPIX, 4, 0},
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{0xED, "SBC", ABSOL, 4, 0},
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{0xFD, "SBC", ABSIX, 4, CYCLES_CROSS_PAGE_ADDS_ONE},
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{0xF9, "SBC", ABSIY, 4, CYCLES_CROSS_PAGE_ADDS_ONE},
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{0xE1, "SBC", INDIN, 6, 0},
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{0xF1, "SBC", ININD, 5, CYCLES_CROSS_PAGE_ADDS_ONE},
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{0x38, "SEC", IMPLI, 2, 0}, /* SEC */
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@ -258,10 +261,10 @@ opcode_t opcode_table[NUMBER_OPCODES] = {
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{0x85, "STA", ZEROP, 3, 0}, /* STA */
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{0x95, "STA", ZEPIX, 4, 0},
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{0x8D, "STA", ABSOL, 4, 0},
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{0x9D, "STA", ABSIX, 4, 0},
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{0x99, "STA", ABSIY, 4, 0},
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{0x9D, "STA", ABSIX, 4, CYCLES_CROSS_PAGE_ADDS_ONE},
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{0x99, "STA", ABSIY, 4, CYCLES_CROSS_PAGE_ADDS_ONE},
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{0x81, "STA", INDIN, 6, 0},
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{0x91, "STA", ININD, 5, 0},
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{0x91, "STA", ININD, 5, CYCLES_CROSS_PAGE_ADDS_ONE},
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{0x86, "STX", ZEROP, 3, 0}, /* STX */
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{0x96, "STX", ZEPIY, 4, 0},
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@ -286,7 +289,7 @@ opcode_t opcode_table[NUMBER_OPCODES] = {
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/* This function emits a comment header with information about the file
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being disassembled */
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void emit_header(options_t *options, int fsize) {
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static void emit_header(options_t *options, int fsize) {
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fprintf(stdout, "; Source generated by DCC6502 version %s\n", VERSION_INFO);
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fprintf(stdout, "; For more info about DCC6502, see https://github.com/tcarmelveilleux/dcc6502\n");
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fprintf(stdout, "; FILENAME: %s, File Size: %d, ORG: $%04X\n", options->filename, fsize, options->org);
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@ -296,15 +299,36 @@ void emit_header(options_t *options, int fsize) {
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fprintf(stdout, ";---------------------------------------------------------------------------\n");
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}
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/* This function appends cycle counting to the comment block */
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char *append_cycle(char *input, uint8_t entry) {
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/* This function appends cycle counting to the comment block. See following
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* for methods used:
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* "Nick Bensema's Guide to Cycle Counting on the Atari 2600"
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* http://www.alienbill.com/2600/cookbook/cycles/nickb.txt
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*/
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static char *append_cycle(char *input, uint8_t entry, uint16_t pc, uint16_t new_pc) {
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char tmpstr[256];
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int cycles = opcode_table[entry].cycles;
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int cycles = g_opcode_table[entry].cycles;
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int exceptions = g_opcode_table[entry].cycles_exceptions;
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int crosses_page = ((pc & 0xff00u) != (new_pc & 0xff00u)) ? 1 : 0;
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// On page boundary crossing, instruction will take an extra cycle
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if (opcode_table[entry].cross_page) {
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sprintf(tmpstr, " Cycles: %d/%d", cycles, cycles + 1);
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// On some exceptional conditions, instruction will take an extra cycle, or even two
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if (exceptions != 0) {
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if ((exceptions & CYCLES_BRANCH_TAKEN_ADDS_ONE) && (exceptions & CYCLES_CROSS_PAGE_ADDS_ONE)) {
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/* Branch case: check for page crossing, since it can be determined
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* statically from the relative offset and current PC.
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*/
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if (crosses_page) {
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/* Crosses page, always at least 1 extra cycle, two times */
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sprintf(tmpstr, " Cycles: %d/%d", cycles + 1, cycles + 2);
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} else {
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/* Does not cross page, maybe one extra cycle if branch taken */
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sprintf(tmpstr, " Cycles: %d/%d", cycles, cycles + 1);
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}
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} else {
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/* One exception: two times, can't tell in advance whether page crossing occurs */
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sprintf(tmpstr, " Cycles: %d/%d", cycles, cycles + 1);
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}
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} else {
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/* No exceptions, no extra time */
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sprintf(tmpstr, " Cycles: %d", cycles);
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}
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@ -312,13 +336,13 @@ char *append_cycle(char *input, uint8_t entry) {
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return (input + strlen(input));
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}
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void add_nes_str(char *instr, char *instr2) {
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static void add_nes_str(char *instr, char *instr2) {
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||||
strcat(instr, " [NES] ");
|
||||
strcat(instr, instr2);
|
||||
}
|
||||
|
||||
/* This function put NES-specific info in the comment block */
|
||||
void append_nes(char *input, uint16_t arg) {
|
||||
static void append_nes(char *input, uint16_t arg) {
|
||||
switch(arg) {
|
||||
case 0x2000: add_nes_str(input, "PPU setup #1"); break;
|
||||
case 0x2001: add_nes_str(input, "PPU setup #2"); break;
|
||||
|
|
@ -354,13 +378,14 @@ void append_nes(char *input, uint16_t arg) {
|
|||
}
|
||||
}
|
||||
|
||||
/* Helper macros for disassemble() function */
|
||||
#define DUMP_FORMAT (options->hex_output ? "%-16s%-16s;" : "%-8s%-16s;")
|
||||
#define HIGH_PART(val) (((val) >> 8) & 0xFFu)
|
||||
#define LOW_PART(val) ((val) & 0xFFu)
|
||||
#define LOAD_WORD(buffer, current_pc) ((uint16_t)buffer[(current_pc) + 1] | (((uint16_t)buffer[(current_pc) + 2]) << 8))
|
||||
|
||||
/* This function disassembles the opcode at the PC and outputs it in *output */
|
||||
void disassemble(char *output, uint8_t *buffer, options_t *options, uint16_t *pc) {
|
||||
static void disassemble(char *output, uint8_t *buffer, options_t *options, uint16_t *pc) {
|
||||
char opcode_repr[256], hex_dump[256];
|
||||
int opcode_idx;
|
||||
int len = 0;
|
||||
|
|
@ -377,17 +402,16 @@ void disassemble(char *output, uint8_t *buffer, options_t *options, uint16_t *pc
|
|||
|
||||
// Linear search for opcode
|
||||
for (opcode_idx = 0; opcode_idx < NUMBER_OPCODES; opcode_idx++) {
|
||||
if (opcode == opcode_table[opcode_idx].number) {
|
||||
if (opcode == g_opcode_table[opcode_idx].number) {
|
||||
/* Found the opcode, record its table index */
|
||||
found = 1;
|
||||
entry = opcode_idx;
|
||||
}
|
||||
}
|
||||
|
||||
// TODO: Normalize %02x versus %02X
|
||||
// For opcode not found, terminate early
|
||||
if (!found) {
|
||||
sprintf(opcode_repr, ".byte $%02x", opcode);
|
||||
sprintf(opcode_repr, ".byte $%02X", opcode);
|
||||
if (options->hex_output) {
|
||||
sprintf(hex_dump, "$%04X> %02X:", current_addr, opcode);
|
||||
sprintf(output, "%-16s%-16s; INVALID OPCODE !!!\n", hex_dump, opcode_repr);
|
||||
|
|
@ -399,19 +423,19 @@ void disassemble(char *output, uint8_t *buffer, options_t *options, uint16_t *pc
|
|||
}
|
||||
|
||||
// Opcode found in table: disassemble properly according to addressing mode
|
||||
mnemonic = opcode_table[entry].mnemonic;
|
||||
mnemonic = g_opcode_table[entry].mnemonic;
|
||||
|
||||
// Set hex dump to default single address format. Will be overwritten
|
||||
// by more complex output in case of hex dump mode enabled
|
||||
sprintf(hex_dump, "$%04X", current_addr);
|
||||
|
||||
switch (opcode_table[entry].addressing) {
|
||||
switch (g_opcode_table[entry].addressing) {
|
||||
case IMMED:
|
||||
/* Get immediate value operand */
|
||||
byte_operand = buffer[*pc + 1];
|
||||
*pc += 1;
|
||||
|
||||
sprintf(opcode_repr, "%s #$%02x", mnemonic, byte_operand);
|
||||
sprintf(opcode_repr, "%s #$%02X", mnemonic, byte_operand);
|
||||
if (options->hex_output) {
|
||||
sprintf(hex_dump, "$%04X> %02X %02X:", current_addr, opcode, byte_operand);
|
||||
}
|
||||
|
|
@ -554,16 +578,17 @@ void disassemble(char *output, uint8_t *buffer, options_t *options, uint16_t *pc
|
|||
break;
|
||||
}
|
||||
|
||||
// Emit disassembly line content, prior to annotation comments
|
||||
len = sprintf(output, DUMP_FORMAT, hex_dump, opcode_repr);
|
||||
output += len;
|
||||
|
||||
/* Add cycle count if necessary */
|
||||
if (options->cycle_counting) {
|
||||
output = append_cycle(output, entry);
|
||||
output = append_cycle(output, entry, *pc + 1, word_operand);
|
||||
}
|
||||
|
||||
/* Add NES port info if necessary */
|
||||
switch (opcode_table[entry].addressing) {
|
||||
switch (g_opcode_table[entry].addressing) {
|
||||
case ABSOL:
|
||||
case ABSIX:
|
||||
case ABSIY:
|
||||
|
|
@ -577,13 +602,13 @@ void disassemble(char *output, uint8_t *buffer, options_t *options, uint16_t *pc
|
|||
}
|
||||
}
|
||||
|
||||
void version(void) {
|
||||
static void version(void) {
|
||||
fprintf(stderr, "DCC6502 %s (C)1998-2014 Tennessee Carmel-Veilleux <veilleux@tentech.ca>\n", VERSION_INFO);
|
||||
fprintf(stderr, "This software is licensed under the MIT license. See the LICENSE file.\n");
|
||||
fprintf(stderr, "See source on github: https://github.com/tcarmelveilleux/dcc6502.\n");
|
||||
}
|
||||
|
||||
void usage(void) {
|
||||
static void usage(void) {
|
||||
fprintf(stderr, "Usage: dcc6502 [options] FILENAME");
|
||||
fprintf(stderr, " -?/-h : Show this help message\n");
|
||||
fprintf(stderr, " -o ORIGIN : Set the origin (base address of disassembly) [default: 0x8000]\n");
|
||||
|
|
@ -595,7 +620,7 @@ void usage(void) {
|
|||
fprintf(stderr, "\n");
|
||||
}
|
||||
|
||||
unsigned long str_arg_to_ulong(char *str, unsigned long default_val) {
|
||||
static unsigned long str_arg_to_ulong(char *str, unsigned long default_val) {
|
||||
uint32_t tmp = 0;
|
||||
|
||||
errno = EOK;
|
||||
|
|
@ -609,7 +634,7 @@ unsigned long str_arg_to_ulong(char *str, unsigned long default_val) {
|
|||
}
|
||||
}
|
||||
|
||||
void usage_and_exit(int exit_code, const char *message) {
|
||||
static void usage_and_exit(int exit_code, const char *message) {
|
||||
version();
|
||||
usage();
|
||||
if (NULL != message) {
|
||||
|
|
@ -618,7 +643,7 @@ void usage_and_exit(int exit_code, const char *message) {
|
|||
exit(exit_code);
|
||||
}
|
||||
|
||||
void parse_args(int argc, char *argv[], options_t *options) {
|
||||
static void parse_args(int argc, char *argv[], options_t *options) {
|
||||
int arg_idx = 1;
|
||||
|
||||
options->cycle_counting = 0;
|
||||
|
|
|
|||
Loading…
Reference in New Issue