From 555568c10bc56909e32f00e8f3c9e5475720846f Mon Sep 17 00:00:00 2001 From: jborza Date: Sun, 14 Apr 2019 15:15:15 +0200 Subject: [PATCH] added stubs for missing instructions to cpu --- cpu.c | 245 +++++++++++++++++++++++++++++++++---------- data/generate_cpu.py | 17 +++ 2 files changed, 208 insertions(+), 54 deletions(-) create mode 100644 data/generate_cpu.py diff --git a/cpu.c b/cpu.c index f4ee024..22f5b81 100644 --- a/cpu.c +++ b/cpu.c @@ -65,63 +65,100 @@ word read_word(State6502 * state, word address) { int emulate_6502_op(State6502 * state) { byte* opcode = &state->memory[state->pc++]; switch (*opcode) { + + + + case ADC_IMM: unimplemented_instruction(state); break; + case ADC_ZP: unimplemented_instruction(state); break; + case ADC_ZPX: unimplemented_instruction(state); break; + case ADC_ABS: unimplemented_instruction(state); break; + case ADC_ABSX: unimplemented_instruction(state); break; + case ADC_ABSY: unimplemented_instruction(state); break; + case ADC_INDX: unimplemented_instruction(state); break; + case ADC_INDY: unimplemented_instruction(state); break; + case AND_IMM: unimplemented_instruction(state); break; + case AND_ZP: unimplemented_instruction(state); break; + case AND_ZPX: unimplemented_instruction(state); break; + case AND_ABS: unimplemented_instruction(state); break; + case AND_ABSX: unimplemented_instruction(state); break; + case AND_ABSY: unimplemented_instruction(state); break; + case AND_INDX: unimplemented_instruction(state); break; + case AND_INDY: unimplemented_instruction(state); break; + case ASL_ACC: unimplemented_instruction(state); break; + case ASL_ZP: unimplemented_instruction(state); break; + case ASL_ZPX: unimplemented_instruction(state); break; + case ASL_ABS: unimplemented_instruction(state); break; + case ASL_ABSX: unimplemented_instruction(state); break; + case BCC_REL: unimplemented_instruction(state); break; + case BCS_REL: unimplemented_instruction(state); break; + case BEQ_REL: unimplemented_instruction(state); break; + case BMI_REL: unimplemented_instruction(state); break; + case BNE_REL: unimplemented_instruction(state); break; + case BPL_REL: unimplemented_instruction(state); break; + case BVC_REL: unimplemented_instruction(state); break; + case BVS_REL: unimplemented_instruction(state); break; + case BIT_ZP: unimplemented_instruction(state); break; + case BIT_ABS: unimplemented_instruction(state); break; case BRK: state->running = 0; state->flags.b = 1; break; //BRK + case CLC: unimplemented_instruction(state); break; + case CLD: unimplemented_instruction(state); break; + case CLI: unimplemented_instruction(state); break; + case CLV: unimplemented_instruction(state); break; case NOP: break; //NOP - case ORA_INDX: //ORA, indirect, x - { - //pre-indexed indirect - //zero-page address is added to x register - byte indirect_address = pop_byte(state) + state->x; - //pointing to address of a word holding the address of the operand - word address = read_word(state, indirect_address); - ORA(state, state->memory[address]); - break; - } - case ORA_ZP: //ORA, zero page - { - byte address = pop_byte(state); - ORA(state, state->memory[address]); - break; - } - case ORA_INDY: //ORA, indirect, y (post_indexed) - { - //post-indexed indirect - //zero-page address as an argument - byte indirect_address = pop_byte(state); - //the address and the following byte is read as a word, adding Y register - word address = read_word(state, indirect_address) + state->y; - ORA(state, state->memory[address]); - break; - } - case ORA_IMM: - ORA(state, pop_byte(state)); - break; - case ORA_ZPX: - { - byte address = pop_byte(state) + state->x; - ORA(state, state->memory[address]); - break; - } - case ORA_ABS: - { - word address = pop_word(state); - ORA(state, state->memory[address]); - break; - } - case ORA_ABSX: - { - word address = pop_word(state) + state->x; - ORA(state, state->memory[address]); - break; - } - case ORA_ABSY: - { - word address = pop_word(state) + state->y; - ORA(state, state->memory[address]); - break; - } + case PHA: unimplemented_instruction(state); break; + case PLA: unimplemented_instruction(state); break; + case PHP: unimplemented_instruction(state); break; + case PLP: unimplemented_instruction(state); break; + case RTI: unimplemented_instruction(state); break; + case RTS: unimplemented_instruction(state); break; + case SEC: unimplemented_instruction(state); break; + case SED: unimplemented_instruction(state); break; + case SEI: unimplemented_instruction(state); break; + case TAX: unimplemented_instruction(state); break; + case TXA: unimplemented_instruction(state); break; + case TAY: unimplemented_instruction(state); break; + case TYA: unimplemented_instruction(state); break; + case TSX: unimplemented_instruction(state); break; + case TXS: unimplemented_instruction(state); break; + case CMP_IMM: unimplemented_instruction(state); break; + case CMP_ZP: unimplemented_instruction(state); break; + case CMP_ZPX: unimplemented_instruction(state); break; + case CMP_ABS: unimplemented_instruction(state); break; + case CMP_ABSX: unimplemented_instruction(state); break; + case CMP_ABSY: unimplemented_instruction(state); break; + case CMP_INDX: unimplemented_instruction(state); break; + case CMP_INDY: unimplemented_instruction(state); break; + case CPX_IMM: unimplemented_instruction(state); break; + case CPX_ZP: unimplemented_instruction(state); break; + case CPX_ABS: unimplemented_instruction(state); break; + case CPY_IMM: unimplemented_instruction(state); break; + case CPY_ZP: unimplemented_instruction(state); break; + case CPY_ABS: unimplemented_instruction(state); break; + case DEC_ZP: unimplemented_instruction(state); break; + case DEC_ZPX: unimplemented_instruction(state); break; + case DEC_ABS: unimplemented_instruction(state); break; + case DEC_ABSX: unimplemented_instruction(state); break; + case DEX: unimplemented_instruction(state); break; + case DEY: unimplemented_instruction(state); break; + case INX: unimplemented_instruction(state); break; + case INY: unimplemented_instruction(state); break; + case EOR_IMM: unimplemented_instruction(state); break; + case EOR_ZP: unimplemented_instruction(state); break; + case EOR_ZPX: unimplemented_instruction(state); break; + case EOR_ABS: unimplemented_instruction(state); break; + case EOR_ABSX: unimplemented_instruction(state); break; + case EOR_ABSY: unimplemented_instruction(state); break; + case EOR_INDX: unimplemented_instruction(state); break; + case EOR_INDY: unimplemented_instruction(state); break; + case INC_ZP: unimplemented_instruction(state); break; + case INC_ZPX: unimplemented_instruction(state); break; + case INC_ABS: unimplemented_instruction(state); break; + case INC_ABSX: unimplemented_instruction(state); break; + case JMP_ABS: unimplemented_instruction(state); break; + case JMP_IND: unimplemented_instruction(state); break; + case JSR_ABS: unimplemented_instruction(state); break; case LDA_IMM: { LDA(state, pop_byte(state)); @@ -166,7 +203,7 @@ int emulate_6502_op(State6502 * state) { word address = read_word(state, indirect_address); LDA(state, state->memory[address]); break; - } + } case LDA_INDY: { //post-indexed indirect @@ -177,6 +214,106 @@ int emulate_6502_op(State6502 * state) { LDA(state, state->memory[address]); break; } + case LDX_IMM: unimplemented_instruction(state); break; + case LDX_ZP: unimplemented_instruction(state); break; + case LDX_ZPY: unimplemented_instruction(state); break; + case LDX_ABS: unimplemented_instruction(state); break; + case LDX_ABSY: unimplemented_instruction(state); break; + case LDY_IMM: unimplemented_instruction(state); break; + case LDY_ZP: unimplemented_instruction(state); break; + case LDY_ZPX: unimplemented_instruction(state); break; + case LDY_ABS: unimplemented_instruction(state); break; + case LDY_ABSX: unimplemented_instruction(state); break; + case LSR_ACC: unimplemented_instruction(state); break; + case LSR_ZP: unimplemented_instruction(state); break; + case LSR_ZPX: unimplemented_instruction(state); break; + case LSR_ABS: unimplemented_instruction(state); break; + case LSR_ABSX: unimplemented_instruction(state); break; + case ORA_IMM: + ORA(state, pop_byte(state)); + break; + case ORA_ZP: //ORA, zero page + { + byte address = pop_byte(state); + ORA(state, state->memory[address]); + break; + } + case ORA_ZPX: + { + byte address = pop_byte(state) + state->x; + ORA(state, state->memory[address]); + break; + } + case ORA_ABS: + { + word address = pop_word(state); + ORA(state, state->memory[address]); + break; + } + case ORA_ABSX: + { + word address = pop_word(state) + state->x; + ORA(state, state->memory[address]); + break; + } + case ORA_ABSY: + { + word address = pop_word(state) + state->y; + ORA(state, state->memory[address]); + break; + } + case ORA_INDX: //ORA, indirect, x + { + //pre-indexed indirect + //zero-page address is added to x register + byte indirect_address = pop_byte(state) + state->x; + //pointing to address of a word holding the address of the operand + word address = read_word(state, indirect_address); + ORA(state, state->memory[address]); + break; + } + case ORA_INDY: //ORA, indirect, y (post_indexed) + { + //post-indexed indirect + //zero-page address as an argument + byte indirect_address = pop_byte(state); + //the address and the following byte is read as a word, adding Y register + word address = read_word(state, indirect_address) + state->y; + ORA(state, state->memory[address]); + break; + } + case ROL_ACC: unimplemented_instruction(state); break; + case ROL_ZP: unimplemented_instruction(state); break; + case ROL_ZPX: unimplemented_instruction(state); break; + case ROL_ABS: unimplemented_instruction(state); break; + case ROL_ABSX: unimplemented_instruction(state); break; + case ROR_ACC: unimplemented_instruction(state); break; + case ROR_ZP: unimplemented_instruction(state); break; + case ROR_ZPX: unimplemented_instruction(state); break; + case ROR_ABS: unimplemented_instruction(state); break; + case ROR_ABSX: unimplemented_instruction(state); break; + case SBC_IMM: unimplemented_instruction(state); break; + case SBC_ZP: unimplemented_instruction(state); break; + case SBC_ZPX: unimplemented_instruction(state); break; + case SBC_ABS: unimplemented_instruction(state); break; + case SBC_ABSX: unimplemented_instruction(state); break; + case SBC_ABSY: unimplemented_instruction(state); break; + case SBC_INDX: unimplemented_instruction(state); break; + case SBC_INDY: unimplemented_instruction(state); break; + case STA_ZP: unimplemented_instruction(state); break; + case STA_ZPX: unimplemented_instruction(state); break; + case STA_ABS: unimplemented_instruction(state); break; + case STA_ABSX: unimplemented_instruction(state); break; + case STA_ABSY: unimplemented_instruction(state); break; + case STA_INDX: unimplemented_instruction(state); break; + case STA_INDY: unimplemented_instruction(state); break; + case STX_ZP: unimplemented_instruction(state); break; + case STX_ZPY: unimplemented_instruction(state); break; + case STX_ABS: unimplemented_instruction(state); break; + case STY_ZP: unimplemented_instruction(state); break; + case STY_ZPX: unimplemented_instruction(state); break; + case STY_ABS: unimplemented_instruction(state); break; + default: unimplemented_instruction(state); break; } diff --git a/data/generate_cpu.py b/data/generate_cpu.py new file mode 100644 index 0000000..8fcdcc4 --- /dev/null +++ b/data/generate_cpu.py @@ -0,0 +1,17 @@ +import csv + +with open('cpu.c','w') as outfile: + + with open('6502_ops.csv','r') as file: + reader = csv.DictReader(file) + for op in reader: + print(op) + args = int(op['bytes']) + + addr_mode = op['addressing mode'] + suffix = '_'+ addr_mode if addr_mode != 'IMP' else '' + mnemonic = op['mnemonic'] + name = mnemonic + suffix + + outfile.write('case %s: ' % name) + outfile.write('unimplemented_instruction(state); break;\n') \ No newline at end of file