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Add STZ instruction (to store zero)

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This commit is contained in:
Peter Evans 2018-02-22 00:02:57 -06:00
parent 7363547608
commit 807362e871
7 changed files with 35 additions and 9 deletions
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1
include/mos6502.enums.h
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@ -122,6 +122,7 @@ enum instruction {
STA, // STore Accumulator
STX, // STore X
STY, // STore Y
STZ, // STore Zero
TAX, // Transfer Accumulator to X
TAY, // Transfer Accumulator to Y
TSX, // Transfer Stack register to X

1
include/mos6502.h
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@ -231,6 +231,7 @@ DECL_INST(sei);
DECL_INST(sta);
DECL_INST(stx);
DECL_INST(sty);
DECL_INST(stz);
DECL_INST(tax);
DECL_INST(tay);
DECL_INST(tsx);

6
src/mos6502.addr.c
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@ -25,10 +25,10 @@ static int addr_modes[] = {
REL, IDY, ZPG, NOA, ZPX, ZPX, ZPX, NOA, IMP, ABY, ACC, NOA, ABX, ABX, ABX, NOA, // 3x
IMP, IDX, NOA, NOA, NOA, ZPG, ZPG, NOA, IMP, IMM, ACC, NOA, ABS, ABS, ABS, NOA, // 4x
REL, IDY, ZPG, NOA, NOA, ZPX, ZPX, NOA, IMP, ABY, IMP, NOA, NOA, ABX, ABX, NOA, // 5x
IMP, IDX, NOA, NOA, NOA, ZPG, ZPG, NOA, IMP, IMM, ACC, NOA, IND, ABS, ABS, NOA, // 6x
REL, IDY, ZPG, NOA, NOA, ZPX, ZPX, NOA, IMP, ABY, IMP, NOA, ABX, ABX, ABX, NOA, // 7x
IMP, IDX, NOA, NOA, ZPG, ZPG, ZPG, NOA, IMP, IMM, ACC, NOA, IND, ABS, ABS, NOA, // 6x
REL, IDY, ZPG, NOA, ZPX, ZPX, ZPX, NOA, IMP, ABY, IMP, NOA, ABX, ABX, ABX, NOA, // 7x
REL, IDX, NOA, NOA, ZPG, ZPG, ZPG, NOA, IMP, IMM, IMP, NOA, ABS, ABS, ABS, NOA, // 8x
REL, IDY, ZPG, NOA, ZPX, ZPX, ZPY, NOA, IMP, ABY, IMP, NOA, NOA, ABX, NOA, NOA, // 9x
REL, IDY, ZPG, NOA, ZPX, ZPX, ZPY, NOA, IMP, ABY, IMP, NOA, ABS, ABX, ABX, NOA, // 9x
IMM, IDX, IMM, NOA, ZPG, ZPG, ZPG, NOA, IMP, IMM, IMP, NOA, ABS, ABS, ABS, NOA, // Ax
REL, IDY, ZPG, NOA, ZPX, ZPX, ZPY, NOA, IMP, ABY, IMP, NOA, ABX, ABX, ABY, NOA, // Bx
IMM, IDX, NOA, NOA, ZPG, ZPG, ZPG, NOA, IMP, IMM, IMP, NOA, ABS, ABS, ABS, NOA, // Cx

13
src/mos6502.c
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@ -33,10 +33,10 @@ static int instructions[] = {
BMI, AND, AND, BAD, BIT, AND, ROL, BAD, SEC, AND, DEC, BAD, BIT, AND, ROL, BAD, // 3x
RTI, EOR, BAD, BAD, BAD, EOR, LSR, BAD, PHA, EOR, LSR, BAD, JMP, EOR, LSR, BAD, // 4x
BVC, EOR, EOR, BAD, BAD, EOR, LSR, BAD, CLI, EOR, PHY, BAD, BAD, EOR, LSR, BAD, // 5x
RTS, ADC, BAD, BAD, BAD, ADC, ROR, BAD, PLA, ADC, ROR, BAD, JMP, ADC, ROR, BAD, // 6x
BVS, ADC, ADC, BAD, BAD, ADC, ROR, BAD, SEI, ADC, PLY, BAD, JMP, ADC, ROR, BAD, // 7x
RTS, ADC, BAD, BAD, STZ, ADC, ROR, BAD, PLA, ADC, ROR, BAD, JMP, ADC, ROR, BAD, // 6x
BVS, ADC, ADC, BAD, STZ, ADC, ROR, BAD, SEI, ADC, PLY, BAD, JMP, ADC, ROR, BAD, // 7x
BRA, STA, BAD, BAD, STY, STA, STX, BAD, DEY, BIM, TXA, BAD, STY, STA, STX, BAD, // 8x
BCC, STA, STA, BAD, STY, STA, STX, BAD, TYA, STA, TXS, BAD, BAD, STA, BAD, BAD, // 9x
BCC, STA, STA, BAD, STY, STA, STX, BAD, TYA, STA, TXS, BAD, STZ, STA, STZ, BAD, // 9x
LDY, LDA, LDX, BAD, LDY, LDA, LDX, BAD, TAY, LDA, TAX, BAD, LDY, LDA, LDX, BAD, // Ax
BCS, LDA, LDA, BAD, LDY, LDA, LDX, BAD, CLV, LDA, TSX, BAD, LDY, LDA, LDX, BAD, // Bx
CPY, CMP, BAD, BAD, CPY, CMP, DEC, BAD, INY, CMP, DEX, BAD, CPY, CMP, DEC, BAD, // Cx
@ -114,6 +114,7 @@ static mos6502_instruction_handler instruction_handlers[] = {
INST_HANDLER(sta),
INST_HANDLER(stx),
INST_HANDLER(sty),
INST_HANDLER(stz),
INST_HANDLER(tax),
INST_HANDLER(tay),
INST_HANDLER(tsx),
@ -135,10 +136,10 @@ static int cycles[] = {
2, 5, 5, 0, 4, 4, 6, 0, 2, 4, 2, 0, 4, 4, 7, 0, // 3x
6, 6, 0, 0, 0, 3, 5, 0, 3, 2, 2, 0, 3, 4, 6, 0, // 4x
2, 5, 5, 0, 0, 4, 6, 0, 2, 4, 3, 0, 0, 4, 7, 0, // 5x
6, 6, 0, 0, 0, 3, 5, 0, 4, 2, 2, 0, 5, 4, 6, 0, // 6x
2, 5, 5, 0, 0, 4, 6, 0, 2, 4, 4, 0, 6, 4, 7, 0, // 7x
6, 6, 0, 0, 3, 3, 5, 0, 4, 2, 2, 0, 5, 4, 6, 0, // 6x
2, 5, 5, 0, 4, 4, 6, 0, 2, 4, 4, 0, 6, 4, 7, 0, // 7x
3, 6, 0, 0, 3, 3, 3, 0, 2, 2, 2, 0, 4, 4, 4, 0, // 8x
2, 6, 5, 0, 4, 4, 4, 0, 2, 5, 2, 0, 0, 5, 0, 0, // 9x
2, 6, 5, 0, 4, 4, 4, 0, 2, 5, 2, 0, 4, 5, 5, 0, // 9x
2, 6, 2, 0, 3, 3, 3, 0, 2, 2, 2, 0, 4, 4, 4, 0, // Ax
2, 5, 5, 0, 4, 4, 4, 0, 2, 4, 2, 0, 4, 4, 4, 0, // Bx
2, 6, 0, 0, 3, 3, 5, 0, 2, 2, 2, 0, 4, 4, 3, 0, // Cx

1
src/mos6502.dis.c
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@ -98,6 +98,7 @@ static char *instruction_strings[] = {
"STA",
"STX",
"STY",
"STZ",
"TAX",
"TAY",
"TSX",

8
src/mos6502.loadstor.c
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@ -129,6 +129,14 @@ DEFINE_INST(sty)
mos6502_set(cpu, cpu->eff_addr, cpu->Y);
}
/*
* Store a zero byte into the effective address
*/
DEFINE_INST(stz)
{
mos6502_set(cpu, cpu->eff_addr, 0);
}
/*
* The TAX instruction taxes no one but your patience for my puns. What
* it does do is transfer the contents of the A register to X.

14
tests/mos6502.loadstor.c
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@ -110,6 +110,20 @@ Test(mos6502_loadstor, sty)
cr_assert_eq(mos6502_get(cpu, cpu->eff_addr), cpu->Y);
}
Test(mos6502_loadstor, stz)
{
// To begin with, we want a non-zero value in eff_addr
cpu->eff_addr = 111;
mos6502_set(cpu, cpu->eff_addr, 222);
// Furthermore, we pass in a non-zero operand to stz, which
// _shouldn't_ care what the operand is. It should only assign a
// zero to eff_addr.
mos6502_handle_stz(cpu, 11);
cr_assert_eq(mos6502_get(cpu, cpu->eff_addr), 0);
}
Test(mos6502_loadstor, tax)
{
cpu->A = 111;