From f9a277e7bcc31cc0184c6b0460a780de4b3abc51 Mon Sep 17 00:00:00 2001
From: Peter Evans <peter@modul8r.com>
Date: Wed, 21 Feb 2018 21:57:21 -0600
Subject: [PATCH] Add new Branch Always instruction

---
 include/mos6502.enums.h |  1 +
 include/mos6502.h       |  1 +
 src/mos6502.addr.c      |  2 +-
 src/mos6502.branch.c    | 10 ++++++++++
 src/mos6502.c           |  5 +++--
 src/mos6502.dis.c       |  1 +
 tests/mos6502.branch.c  |  8 ++++++++
 7 files changed, 25 insertions(+), 3 deletions(-)

diff --git a/include/mos6502.enums.h b/include/mos6502.enums.h
index b756957..2bc0b45 100644
--- a/include/mos6502.enums.h
+++ b/include/mos6502.enums.h
@@ -77,6 +77,7 @@ enum instruction {
     BMI,    // Branch on MInus 
     BNE,    // Branch on Not Equal to zero
     BPL,    // Branch on PLus
+    BRA,    // BRanch Always
     BRK,    // BReaK (interrupt)
     BVC,    // Branch on oVerflow Clear
     BVS,    // Branch on oVerflow Set
diff --git a/include/mos6502.h b/include/mos6502.h
index 89cc6bf..6ee96eb 100644
--- a/include/mos6502.h
+++ b/include/mos6502.h
@@ -186,6 +186,7 @@ DECL_INST(bim);
 DECL_INST(bmi);
 DECL_INST(bne);
 DECL_INST(bpl);
+DECL_INST(bra);
 DECL_INST(brk);
 DECL_INST(bvc);
 DECL_INST(bvs);
diff --git a/src/mos6502.addr.c b/src/mos6502.addr.c
index 383f299..0b459e2 100644
--- a/src/mos6502.addr.c
+++ b/src/mos6502.addr.c
@@ -27,7 +27,7 @@ static int addr_modes[] = {
     REL, IDY, ZPG, NOA, NOA, ZPX, ZPX, NOA, IMP, ABY, NOA, NOA, NOA, ABX, ABX, NOA, // 5x
     IMP, IDX, NOA, NOA, NOA, ZPG, ZPG, NOA, IMP, IMM, ACC, NOA, IND, ABS, ABS, NOA, // 6x
     REL, IDY, ZPG, NOA, NOA, ZPX, ZPX, NOA, IMP, ABY, NOA, NOA, ABX, ABX, ABX, NOA, // 7x
-    NOA, IDX, NOA, NOA, ZPG, ZPG, ZPG, NOA, IMP, IMM, IMP, NOA, ABS, ABS, ABS, NOA, // 8x
+    REL, IDX, NOA, NOA, ZPG, ZPG, ZPG, NOA, IMP, IMM, IMP, NOA, ABS, ABS, ABS, NOA, // 8x
     REL, IDY, ZPG, NOA, ZPX, ZPX, ZPY, NOA, IMP, ABY, IMP, NOA, NOA, ABX, NOA, NOA, // 9x
     IMM, IDX, IMM, NOA, ZPG, ZPG, ZPG, NOA, IMP, IMM, IMP, NOA, ABS, ABS, ABS, NOA, // Ax
     REL, IDY, ZPG, NOA, ZPX, ZPX, ZPY, NOA, IMP, ABY, IMP, NOA, ABX, ABX, ABY, NOA, // Bx
diff --git a/src/mos6502.branch.c b/src/mos6502.branch.c
index 59e6e1f..e74aae2 100644
--- a/src/mos6502.branch.c
+++ b/src/mos6502.branch.c
@@ -67,6 +67,16 @@ DEFINE_INST(bpl)
     JUMP_IF(~cpu->P & MOS_NEGATIVE);
 }
 
+/*
+ * This instruction will branch in all cases. It's not a true
+ * conditional; it's analagous to a relative address mode JMP.
+ */
+DEFINE_INST(bra)
+{
+    // Always jump!
+    JUMP_IF(1);
+}
+
 /*
  * Branch if the overflow bit is clear.
  */
diff --git a/src/mos6502.c b/src/mos6502.c
index ce7aa4b..43592ff 100644
--- a/src/mos6502.c
+++ b/src/mos6502.c
@@ -35,7 +35,7 @@ static int instructions[] = {
     BVC, EOR, EOR, BAD, BAD, EOR, LSR, BAD, CLI, EOR, BAD, BAD, BAD, EOR, LSR, BAD, // 5x
     RTS, ADC, BAD, BAD, BAD, ADC, ROR, BAD, PLA, ADC, ROR, BAD, JMP, ADC, ROR, BAD, // 6x
     BVS, ADC, ADC, BAD, BAD, ADC, ROR, BAD, SEI, ADC, BAD, BAD, JMP, ADC, ROR, BAD, // 7x
-    BAD, STA, BAD, BAD, STY, STA, STX, BAD, DEY, BIM, TXA, BAD, STY, STA, STX, BAD, // 8x
+    BRA, STA, BAD, BAD, STY, STA, STX, BAD, DEY, BIM, TXA, BAD, STY, STA, STX, BAD, // 8x
     BCC, STA, STA, BAD, STY, STA, STX, BAD, TYA, STA, TXS, BAD, BAD, STA, BAD, BAD, // 9x
     LDY, LDA, LDX, BAD, LDY, LDA, LDX, BAD, TAY, LDA, TAX, BAD, LDY, LDA, LDX, BAD, // Ax
     BCS, LDA, LDA, BAD, LDY, LDA, LDX, BAD, CLV, LDA, TSX, BAD, LDY, LDA, LDX, BAD, // Bx
@@ -69,6 +69,7 @@ static mos6502_instruction_handler instruction_handlers[] = {
     INST_HANDLER(bmi),
     INST_HANDLER(bne),
     INST_HANDLER(bpl),
+    INST_HANDLER(bra),
     INST_HANDLER(brk),
     INST_HANDLER(bvc),
     INST_HANDLER(bvs),
@@ -132,7 +133,7 @@ static int cycles[] = {
       2,   5,   5,   0,   0,   4,   6,   0,   2,   4,   0,   0,   0,   4,   7,   0, // 5x
       6,   6,   0,   0,   0,   3,   5,   0,   4,   2,   2,   0,   5,   4,   6,   0, // 6x
       2,   5,   5,   0,   0,   4,   6,   0,   2,   4,   0,   0,   6,   4,   7,   0, // 7x
-      0,   6,   0,   0,   3,   3,   3,   0,   2,   2,   2,   0,   4,   4,   4,   0, // 8x
+      3,   6,   0,   0,   3,   3,   3,   0,   2,   2,   2,   0,   4,   4,   4,   0, // 8x
       2,   6,   5,   0,   4,   4,   4,   0,   2,   5,   2,   0,   0,   5,   0,   0, // 9x
       2,   6,   2,   0,   3,   3,   3,   0,   2,   2,   2,   0,   4,   4,   4,   0, // Ax
       2,   5,   5,   0,   4,   4,   4,   0,   2,   4,   2,   0,   4,   4,   4,   0, // Bx
diff --git a/src/mos6502.dis.c b/src/mos6502.dis.c
index 8921fa0..1386982 100644
--- a/src/mos6502.dis.c
+++ b/src/mos6502.dis.c
@@ -53,6 +53,7 @@ static char *instruction_strings[] = {
     "BMI",
     "BNE",
     "BPL",
+    "BRA",
     "BRK",
     "BVC",
     "BVS",
diff --git a/tests/mos6502.branch.c b/tests/mos6502.branch.c
index 53be7e2..b4278ab 100644
--- a/tests/mos6502.branch.c
+++ b/tests/mos6502.branch.c
@@ -78,6 +78,14 @@ Test(mos6502_branch, bpl)
     cr_assert_eq(cpu->PC, 125);
 }
 
+Test(mos6502_branch, bra)
+{
+    cr_assert_eq(cpu->PC, 0);
+    cpu->eff_addr = 123;
+    mos6502_handle_bra(cpu, 0);
+    cr_assert_eq(cpu->PC, 123);
+}
+
 Test(mos6502_branch, bvc)
 {
     cpu->eff_addr = 123;