Peter Evans
c2e90651ac
Again, latch data must be > 128 (0x80)
2018-02-20 14:44:17 -06:00
Peter Evans
e826fc05d9
We can only write latch data that is > 128
2018-02-20 14:43:33 -06:00
Peter Evans
98f640f0d1
Use the proper sector header length (20 bytes)
2018-02-20 14:35:07 -06:00
Peter Evans
08f3899de4
Tracks don't move from shifting; sector work
...
The sector work being:
- We only wrap around if we go beyond the length of an encoded track, so
use ENC_ETRACK.
- If we DO wrap around, we don't use modulus; we simply reset to zero.
2018-02-20 14:33:36 -06:00
Peter Evans
c7fbb4aa50
Backward steps require adjacent phases
2018-02-20 14:30:20 -06:00
Peter Evans
28061c1d11
Adjust length/data for sectors; cleanup some magic numbers
2018-02-20 01:00:46 -06:00
Peter Evans
2318b1917a
This form needs two RORs to work
...
That's because the first ROR pushes the 1 in bit0 into the carry bit;
the second moves the carry bit into the bit7 position, which will match
128.
2018-02-19 22:01:30 -06:00
Peter Evans
d590a809d8
Tests should reflect how carry is handled in ROL/R now
2018-02-19 21:59:55 -06:00
Peter Evans
65f13bb1e4
Add missing output and fix buffer size issue
...
We use BUFSIZ everywhere, except in setvbuf(), which kinda needs to know
the proper buffer size. Because we were passing 256, which is (much!)
lower than BUFSIZ, we were wrapping output around in an odd, unexpected
way.
2018-02-19 21:49:58 -06:00
Peter Evans
9f0d7f5413
Fix some compile failures due to changed params
2018-02-19 20:03:25 -06:00
Peter Evans
508be6458a
Pass in sector table for logical-physical orders
...
We were not encoding data properly, because in DOS 3.3 and ProDOS,
sectors must be interleaved on disk media (whereas in the original image
form, data is laid out in a linear fashion).
This solves a bug where we erroneously encountered a "bad" opcode (a7)
in the program code.
2018-02-19 18:49:37 -06:00
Peter Evans
3ab654c306
Correct note on GBASL/H address
2018-02-19 13:53:48 -06:00
Peter Evans
96e4b5d9d8
Remove JSR WAIT to speed up disk II controller
2018-02-19 00:48:11 -06:00
Peter Evans
015104bd57
Self-sync bytes should be written after a sector header
...
Not after the data field marker, where the controller/RWTS don't expect
to find them.
2018-02-18 23:46:48 -06:00
Peter Evans
c89e855559
Update to use correct encoded sector length
2018-02-18 23:46:18 -06:00
Peter Evans
00854e74b9
Explain how the JSR call is handled in some impls
2018-02-18 19:49:34 -06:00
Peter Evans
0fccf552f2
Final comments
2018-02-18 11:16:09 -06:00
Peter Evans
7c2c6d5d54
Reformat and annotate disk II controller code
2018-02-18 00:50:50 -06:00
Peter Evans
0d1e949d13
Mask the result so it's never more than a byte
...
This is because the eff_addr variable is a 16bit one, and adding addr +
X or addr + Y can possibly result in a 9-bit value, which is not what we
want. (You'd be pulling data from the stack instead of the zero page.)
2018-02-16 00:44:55 -06:00
Peter Evans
e9164d9872
Very minor changes to make the code simpler
2018-02-16 00:19:14 -06:00
Peter Evans
058b45e7d1
Use 9-bit rotation, not 8-bit
2018-02-15 19:32:01 -06:00
Peter Evans
067c0cea2f
Also check the N flag (i.e. set it to zero)
2018-02-15 13:01:58 -06:00
Peter Evans
e415b3e490
We should check only the first byte for zero
...
We need to accept values for result that are greater than a byte so that
we can determine if carry is set, but this causes an issue when an app
uses addition to force an overflow that would set the zero bit. Masking
result for only the LSB fixes that problem.
2018-02-15 00:26:21 -06:00
Peter Evans
08b0e2e648
Show effective address
2018-02-14 22:19:35 -06:00
Peter Evans
fe70cd1f71
Remove debugging, use ENC_ETRACK for sector pos max
...
Also, there's no need for a while statement; we can just reset to zero.
2018-02-14 22:09:21 -06:00
Peter Evans
7224698cd7
This should be EOR, not ADC
...
I might as well fix the bad opcode here, too!
2018-02-14 21:50:13 -06:00
Peter Evans
9a5c94bbbb
The 49 opcode is EOR, not ADC.
...
Excuse me, I just need to scream now.
AHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
Thank you for your indulgence. Please carry on.
2018-02-14 21:37:02 -06:00
Peter Evans
64b9cbefcb
Several changes to phase and writes
...
1. The phaser algorithm was reworked, and it should be more accurate in
choosing when to step forward or backward.
2. Writes should be committed when the latch has bit 7 high. This hasn't
actually been a problem yet, since other things are broken! But we might
as well fix it now that we've seen it.
2018-02-14 16:49:20 -06:00
Peter Evans
100621a6c6
Show second-digit row mappings for gcr62
2018-02-12 21:20:09 -06:00
Peter Evans
5b1298bded
Document the gcr62 table
2018-02-12 21:19:47 -06:00
Peter Evans
ec522f259e
Add block comments to describe source files
2018-02-12 21:15:20 -06:00
Peter Evans
0822b2f4ba
Use the correct file name
2018-02-12 21:11:50 -06:00
Peter Evans
5c0f65215b
Use the correct file name
2018-02-12 20:18:17 -06:00
Peter Evans
1e3f2e5781
Use the correct name of the source file
2018-02-12 19:28:37 -06:00
Peter Evans
e63d7e5d72
The file is apple2.dd.c
2018-02-12 18:24:35 -06:00
Peter Evans
9e26e215cd
In which we discover that image doesn't matter
2018-02-11 20:38:51 -06:00
Peter Evans
ba387c004f
We should be dividing, not using modulus
2018-02-11 20:36:41 -06:00
Peter Evans
3e2d8acacf
The same track/sector method works for all images
...
Particularly so as the data segment is now the 6-and-2 encoded form,
which we either encode from DOS 3.3/ProDOS, or use literally from NIB
files.
2018-02-11 20:25:44 -06:00
Peter Evans
4765dab912
Don't run erc after building it
2018-02-11 19:28:26 -06:00
Peter Evans
350a06890a
Split up logic for keyboard test
...
In accordance with the split in logic we had made for the source
function
2018-02-10 18:31:38 -06:00
Peter Evans
69d425db2d
Add tests for vm_di
2018-02-10 18:25:29 -06:00
Peter Evans
919869289e
Add missing test for reflect functions, init
2018-02-10 18:20:50 -06:00
Peter Evans
9f60e61cfb
Add missing docblock comments
2018-02-09 23:14:05 -06:00
Peter Evans
aee0521b0a
Change key to ALT+Q
2018-02-07 16:08:43 -06:00
Peter Evans
3223fe6110
Enable disassembly toggle (ALT+D)
2018-02-07 15:24:02 -06:00
Peter Evans
fa938470d3
Account for changes to vm_reflect functions
2018-02-07 14:44:37 -06:00
Peter Evans
c1cbdb4a43
ALT+P will pause
2018-02-07 14:44:26 -06:00
Peter Evans
308a1070ae
Add paused field, pause execution
2018-02-07 14:44:04 -06:00
Peter Evans
433d9a436f
Add pause function, flesh out machine_info
2018-02-07 14:43:20 -06:00
Peter Evans
a84b4c12e9
Treat pause and disasm as toggle functions
...
This allows us to remove the resume and disasm_off functions. (The
disasm_on function is simply renamed to disasm.)
2018-02-07 14:41:44 -06:00
