Peter Evans
647139924b
Small comment
2018-01-12 14:51:00 -06:00
Peter Evans
f69454c965
Some soft switches now require consecutive reads
...
To allow this to work, we had to allow the CPU struct to record what the
last opcode/operand/address were, although in truth we only needed the
last address.
2018-01-12 14:49:27 -06:00
Peter Evans
7d6886a3a8
Change last_addr field to eff_addr
2018-01-12 13:57:48 -06:00
Peter Evans
e56ed9ea43
Add missing docblocks
2018-01-11 22:48:40 -06:00
Peter Evans
a1435de0ad
We weren't noting missing docblock comments.
...
Due to a very python-noob mistake.
2018-01-11 22:42:19 -06:00
Peter Evans
1b2e9d952b
Add missing test code for the aux bank switch
2018-01-11 22:35:23 -06:00
Peter Evans
c4c0312402
Add missing tests for read/write bank switches
2018-01-11 22:24:19 -06:00
Peter Evans
21040898b3
Return, don't break in write mapper; log if we get to the end
2018-01-11 22:23:53 -06:00
Peter Evans
6d21774e78
Add missing tests
2018-01-11 21:58:17 -06:00
Peter Evans
d79bcba5ec
Add missing docblocks
2018-01-11 21:58:05 -06:00
Peter Evans
9564f86a57
Remove flash_memory function
2018-01-11 21:57:52 -06:00
Peter Evans
578e0b291c
Allow us to switch main/aux; write bank switch mappers
2018-01-11 19:52:13 -06:00
Peter Evans
a17ad0596b
Initialize cpu as NULL
...
Static analysis in clang caught this; we might try to free memory from a
garbage pointer value if the main segment malloc fails.
2018-01-11 13:25:22 -06:00
Peter Evans
9d2f9b6f60
Refactor to remove ram2
...
Both main and auxiliary memory need to keep an extra 4k of memory that
is bank-switchable, so we have changed to store that memory literally
within the main and aux segments.
2018-01-11 13:19:17 -06:00
Peter Evans
288b4a9e8d
The boot procedure no longer defaults bank_switch to 0
2018-01-10 21:50:43 -06:00
Peter Evans
81b07361fb
Wait less time for instructions
2018-01-10 21:49:52 -06:00
Peter Evans
fe0ed815a9
Move bank switch set up for the mem init functions.
...
This also changes bank_switch to mirror at boot what the reset function
does later on. Without doing so, our init memory routines will fail.
2018-01-10 21:48:55 -06:00
Peter Evans
24e6e0fd25
Properly free main/aux memory
2018-01-10 21:29:25 -06:00
Peter Evans
8d9b48912e
Add memory injection to 6502; main memory in apple2
...
Note that memory _is_ now managed in apple2, and _not_ in mos6502.
2018-01-10 21:28:05 -06:00
Peter Evans
04854d903c
Add aux memory field
2018-01-10 20:36:44 -06:00
Peter Evans
8898c3e59d
Use macros to define segment read/write map functions
2018-01-10 20:12:48 -06:00
Peter Evans
3db536a83d
Change memory_mode -> bank_switch
...
This also changes the concept of the field; bank_switch is a collection
of bit flags now.
2018-01-10 19:59:33 -06:00
Peter Evans
343d870399
Add missing mach parameter to set_video/set_memory
2018-01-10 16:59:02 -06:00
Peter Evans
538b5ddaa0
Add address for reset vector, applesoft, powerup
2018-01-10 16:47:45 -06:00
Peter Evans
aa486656b3
Set the reset vector to the applesoft interpreter address
2018-01-10 16:47:18 -06:00
Peter Evans
cb53c70cda
We missed a doc-block for the new set16 func
2018-01-10 16:46:55 -06:00
Peter Evans
fcba14f91b
Add set16 function
2018-01-10 16:43:14 -06:00
Peter Evans
6af0ae85a4
Also force bank switch mode back to ROM
2018-01-10 15:16:12 -06:00
Peter Evans
c9188a288d
Reset should change the video mode to 40 column text
2018-01-10 15:14:07 -06:00
Peter Evans
7f6b8d3587
We can no longer assume PC increments during address handling
...
This change required a number of consequent changes to assumptions we'd
made, and I'm not 100% confident we have things right at this point in
time.
2018-01-09 20:59:14 -06:00
Peter Evans
e3ab043aee
We no longer need to pass the opcode here
2018-01-09 20:58:53 -06:00
Peter Evans
80a7671a19
Remove next_byte, read_byte; execute works without an opcode arg
...
This also adds RTS and RTI as instructions that "would jump".
2018-01-09 20:58:19 -06:00
Peter Evans
a785eb5665
Remove next_byte, read_byte; remove opcode from execute
...
The execute function should just work from the PC register. It might
seem to be easier to test by passing an arbitrary opcode into the
function, but because so much of the chip's execution is
context-sensitive (that is, it expects PC to be pointing at the opcode,
to have its operand in front of it, etc.), passing an arbitrary opcode
is not really reflective of what needs to be in place for the function
to work correctly.
2018-01-09 20:56:11 -06:00
Peter Evans
04aab568df
Oh, little-endian issues; you are my bane
2018-01-09 16:28:14 -06:00
Peter Evans
68b1b79549
Added a "fix" to JSR test.
...
It's really wrong, because we _should_ be storing PC + 2 in the stack.
And software's definitely gonna bork when we try emulating them, because
they will invariably inspect the stack and assume that's what we have in
there.
But the proper fix is to not actually do next_byte(), and to never
advance PC outside of the execute function. But that's a bigger change
than I want to do at this specific moment.
So, in the meantime, you have me prattling on in a commit message. Lucky
you!
2018-01-09 16:26:21 -06:00
Peter Evans
b492b44e0c
We have a raft of changes here...
...
1. In some cases we corrected little-endian issues.
2. In others, we need to correct expected output to account for PC,
cycles and hex dumps.
2018-01-09 16:24:51 -06:00
Peter Evans
de859bcea8
We were not obeying little-endianness here
2018-01-09 16:24:25 -06:00
Peter Evans
7e51339b88
Account for incremented PC byte in rel tests
2018-01-09 16:06:41 -06:00
Peter Evans
4beff0bff8
Remember that we must obey little-endian order
2018-01-09 16:00:15 -06:00
Peter Evans
42394fee80
Add new peripheral ROMs, plus a stub ROM
...
...The latter being in the form of the zeropad file, 256 bytes long.
2018-01-09 15:58:29 -06:00
Peter Evans
d7148b88bf
Relative address was not being calculated correctly.
...
The disassembler is using the correct approach, so I adapted it to the
execution code.
2018-01-09 15:57:37 -06:00
Peter Evans
a267065059
Include cycle information
2018-01-09 15:57:20 -06:00
Peter Evans
8201117223
Change init routine to use peripheral function
2018-01-09 15:56:48 -06:00
Peter Evans
0e0244162f
Change objstore structure to contain all peripheral ROM
2018-01-09 15:56:21 -06:00
Peter Evans
3c46a41351
Fix little-endian issue with IND output
...
Also change the ADDR label to emit a hex code, not a decimal code.
2018-01-08 23:36:11 -06:00
Peter Evans
1abf0223c8
The value of PC by that point is correct.
...
Adding 2 skips us ahead farther than we should be going.
2018-01-08 22:25:37 -06:00
Peter Evans
f7b8740c2e
Let the CPU run for longer before it dies
2018-01-08 22:24:30 -06:00
Peter Evans
b21b48cac0
Fix a couple of issues...
...
1. The execute function should not be incrementing the PC register, as
this happens in other places.
2. The push_ and pop_stack functions were not considering that the data
should be in little-endian order.
2018-01-08 21:22:29 -06:00
Peter Evans
e4049a6a11
Better info on each opcode sequence
...
Plus fix a display bug that showed the operand in the wrong order.
2018-01-08 21:21:09 -06:00
Peter Evans
7c899122ad
We should advance to the next byte in execution
2018-01-08 21:15:56 -06:00
