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c953616a71
There is one failing test, which I expect to fail at this point; that's because we need to write a read/write map function for the stack and zero page so that they use aux memory when BANK_ALTZP is on, and main memory when not.
208 lines
7.3 KiB
C
208 lines
7.3 KiB
C
#include <criterion/criterion.h>
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#include "apple2.h"
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#include "apple2.mem.h"
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static apple2 *mach = NULL;
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static void
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setup()
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{
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mach = apple2_create(100, 100);
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vm_segment_set_map_machine(mach);
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}
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static void
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teardown()
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{
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apple2_free(mach);
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vm_segment_set_map_machine(NULL);
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}
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TestSuite(apple2_mem, .init = setup, .fini = teardown);
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Test(apple2_mem, map)
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{
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// mach already had the mem_map function run, so we just need to
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// test the results.
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size_t addr;
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for (addr = APPLE2_BANK_OFFSET; addr < MOS6502_MEMSIZE; addr++) {
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cr_assert_eq(mach->main->read_table[addr], apple2_mem_read_bank);
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cr_assert_eq(mach->main->write_table[addr], apple2_mem_write_bank);
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}
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}
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Test(apple2_mem, map_bank_switch)
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{
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vm_segment *segments[2];
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segments[0] = mach->main;
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segments[1] = mach->aux;
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for (int i = 0; i < 2; i++) {
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cr_assert_eq(segments[i]->read_table[0xC080], apple2_mem_read_bank_switch);
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cr_assert_eq(segments[i]->read_table[0xC081], apple2_mem_read_bank_switch);
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cr_assert_eq(segments[i]->read_table[0xC082], apple2_mem_read_bank_switch);
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cr_assert_eq(segments[i]->read_table[0xC083], apple2_mem_read_bank_switch);
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cr_assert_eq(segments[i]->read_table[0xC088], apple2_mem_read_bank_switch);
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cr_assert_eq(segments[i]->read_table[0xC089], apple2_mem_read_bank_switch);
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cr_assert_eq(segments[i]->read_table[0xC08A], apple2_mem_read_bank_switch);
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cr_assert_eq(segments[i]->read_table[0xC08B], apple2_mem_read_bank_switch);
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cr_assert_eq(segments[i]->read_table[0xC088], apple2_mem_read_bank_switch);
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cr_assert_eq(segments[i]->read_table[0xC011], apple2_mem_read_bank_switch);
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cr_assert_eq(segments[i]->read_table[0xC012], apple2_mem_read_bank_switch);
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cr_assert_eq(segments[i]->read_table[0xC016], apple2_mem_read_bank_switch);
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cr_assert_eq(segments[i]->write_table[0xC008], apple2_mem_write_bank_switch);
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cr_assert_eq(segments[i]->write_table[0xC009], apple2_mem_write_bank_switch);
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}
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}
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Test(apple2_mem, read_bank)
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{
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vm_8bit val;
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// Test that setting a value in the rom segment is returned to us
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// when addressing from main memory
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apple2_set_bank_switch(mach, BANK_WRITE);
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val = 123;
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vm_segment_set(mach->rom, 0x77, val);
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val = vm_segment_get(mach->rom, 0x77);
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cr_assert_eq(vm_segment_get(mach->main, 0xD077), val);
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// In RAM1 bank mode, setting a value in memory should return thaty
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// value in memory... but, as a twist, also check that the value is
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// not set in ROM nor in RAM2.
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val = 222;
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apple2_set_bank_switch(mach, BANK_RAM | BANK_WRITE);
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vm_segment_set(mach->main, 0xD077, val);
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cr_assert_eq(vm_segment_get(mach->main, 0xD077), val);
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cr_assert_neq(vm_segment_get(mach->rom, 0x77), val);
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cr_assert_neq(vm_segment_get(mach->main, 0x10077), val);
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// Finally, in RAM2 bank mode, we test similarly to ROM mode. Set
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// the value directly in ram2 (which is at $10000 - $1FFFF) and see
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// if it's there when addressing from main memory in the $Dnnn
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// range.
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val = 111;
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apple2_set_bank_switch(mach, mach->bank_switch | BANK_RAM2);
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vm_segment_set(mach->main, 0x10077, val);
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cr_assert_eq(vm_segment_get(mach->main, 0xD077), val);
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}
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/*
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* The write_bank test will look a bit similar to the read_bank one,
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* except in logic it should be written somewhat as an inverse. That is,
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* we want our writes to all go to memory, and double-check that the
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* right location is being updated (or not being updated).
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*/
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Test(apple2_mem, write_bank)
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{
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vm_8bit right, wrong;
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// In BANK_DEFAULT mode, we expect that updates to ROM will never be
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// successful (after all, it wouldn't be read-only memory if they
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// were).
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right = 123;
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wrong = 222;
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vm_segment_set(mach->rom, 0x77, right);
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vm_segment_set(mach->main, 0xD077, wrong);
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cr_assert_eq(vm_segment_get(mach->rom, 0x77), right);
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cr_assert_eq(vm_segment_get(mach->main, 0xD077), right);
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// RAM1 is the main bank; it's all 64k RAM in one chunk.
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right = 111;
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wrong = 232;
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apple2_set_bank_switch(mach, BANK_RAM | BANK_WRITE);
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vm_segment_set(mach->main, 0xD078, right);
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vm_segment_set(mach->main, 0x10078, wrong);
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cr_assert_eq(vm_segment_get(mach->main, 0xD078), right);
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cr_assert_eq(vm_segment_get(mach->main, 0x10078), wrong);
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// RAM2 is most of the 64k, except the first 4k of the last 12
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// ($D000..$DFFF) is in ram2.
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right = 210;
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wrong = 132;
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apple2_set_bank_switch(mach, mach->bank_switch | BANK_RAM2);
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vm_segment_set(mach->main, 0x10073, wrong);
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vm_segment_set(mach->main, 0xD073, right);
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cr_assert_eq(vm_segment_get(mach->main, 0x10073), right);
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}
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Test(apple2_mem, read_bank_switch)
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{
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vm_segment_get(mach->main, 0xC080);
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cr_assert_eq(mach->bank_switch, BANK_RAM | BANK_RAM2);
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// This (and a few others) are trickier to test, as they require
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// consecutive reads to trigger.
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vm_segment_get(mach->main, 0xC081);
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cr_assert_neq(mach->bank_switch, BANK_WRITE | BANK_RAM2);
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mach->cpu->last_addr = 0xC081;
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vm_segment_get(mach->main, 0xC081);
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cr_assert_eq(mach->bank_switch, BANK_WRITE | BANK_RAM2);
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vm_segment_get(mach->main, 0xC082);
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cr_assert_eq(mach->bank_switch, BANK_RAM2);
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// Another that needs consecutives
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vm_segment_get(mach->main, 0xC083);
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cr_assert_neq(mach->bank_switch, BANK_RAM | BANK_WRITE | BANK_RAM2);
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mach->cpu->last_addr = 0xC083;
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vm_segment_get(mach->main, 0xC083);
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cr_assert_eq(mach->bank_switch, BANK_RAM | BANK_WRITE | BANK_RAM2);
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vm_segment_get(mach->main, 0xC088);
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cr_assert_eq(mach->bank_switch, BANK_RAM);
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// You get the idea
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vm_segment_get(mach->main, 0xC089);
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cr_assert_neq(mach->bank_switch, BANK_WRITE);
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mach->cpu->last_addr = 0xC089;
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vm_segment_get(mach->main, 0xC089);
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cr_assert_eq(mach->bank_switch, BANK_WRITE);
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vm_segment_get(mach->main, 0xC08A);
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cr_assert_eq(mach->bank_switch, BANK_DEFAULT);
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vm_segment_get(mach->main, 0xC08B);
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cr_assert_neq(mach->bank_switch, BANK_RAM | BANK_WRITE);
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mach->cpu->last_addr = 0xC08B;
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vm_segment_get(mach->main, 0xC08B);
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cr_assert_eq(mach->bank_switch, BANK_RAM | BANK_WRITE);
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mach->bank_switch = BANK_RAM | BANK_RAM2;
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cr_assert_eq(vm_segment_get(mach->main, 0xC011), 0x80);
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mach->bank_switch = BANK_DEFAULT;
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cr_assert_eq(vm_segment_get(mach->main, 0xC011), 0x00);
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mach->bank_switch = BANK_RAM;
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cr_assert_eq(vm_segment_get(mach->main, 0xC012), 0x80);
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mach->bank_switch = BANK_DEFAULT;
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cr_assert_eq(vm_segment_get(mach->main, 0xC012), 0x00);
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mach->bank_switch = BANK_ALTZP;
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cr_assert_eq(vm_segment_get(mach->main, 0xC016), 0x80);
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mach->bank_switch = BANK_DEFAULT;
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cr_assert_eq(vm_segment_get(mach->main, 0xC016), 0x00);
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}
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Test(apple2_mem, write_bank_switch)
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{
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vm_segment_set(mach->main, 0xC008, 1);
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cr_assert_eq(mach->bank_switch & BANK_ALTZP, BANK_ALTZP);
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vm_segment_set(mach->main, 0xC009, 1);
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cr_assert_eq(mach->bank_switch & BANK_ALTZP, 0);
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}
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Test(apple2_mem, init_peripheral_rom)
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{
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// FIXME: this isn't working, _and_ it's pretty tightly coupled into
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// the create() function. We could use a better way of testing this.
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//cr_assert_eq(apple2_mem_init_disk2_rom(mach), OK);
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}
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Test(apple2_mem, init_sys_rom)
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{
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// FIXME: same
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//cr_assert_eq(apple2_mem_init_sys_rom(mach), OK);
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}
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