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erc-c/tests/mos6502.bits.c
Peter Evans 7b65dc1657 Add new BIM instruction (BIt imMediate mode)
This is not a real instruction in the 65c02 processor; I invented it for
the sole purpose of handling the specialized logic that is performed by
BIT in IMM mode. To be fair--I can imagine this really _was_ implemented
as a "separate" instruction on the chip! But I don't know that for sure.
2018-02-21 21:01:46 -06:00

130 lines
2.9 KiB
C

#include <criterion/criterion.h>
#include "mos6502.h"
#include "mos6502.enums.h"
#include "mos6502.tests.h"
TestSuite(mos6502_bits, .init = setup, .fini = teardown);
Test(mos6502_bits, and)
{
cpu->A = 5;
mos6502_handle_and(cpu, 1);
cr_assert_eq(cpu->A, 1);
cpu->A = 5;
mos6502_handle_and(cpu, 4);
cr_assert_eq(cpu->A, 4);
}
Test(mos6502_bits, asl)
{
mos6502_handle_asl(cpu, 5);
cr_assert_eq(cpu->A, 10);
cpu->eff_addr = 123;
mos6502_handle_asl(cpu, 22);
cr_assert_eq(mos6502_get(cpu, 123), 44);
}
Test(mos6502_bits, bit)
{
cpu->A = 5;
mos6502_handle_bit(cpu, 129);
cr_assert_eq(cpu->P & MOS_NEGATIVE, MOS_NEGATIVE);
cr_assert_eq(cpu->P & MOS_OVERFLOW, 0);
cr_assert_eq(cpu->P & MOS_ZERO, 0);
mos6502_handle_bit(cpu, 193);
cr_assert_eq(cpu->P & MOS_NEGATIVE, MOS_NEGATIVE);
cr_assert_eq(cpu->P & MOS_OVERFLOW, MOS_OVERFLOW);
cr_assert_eq(cpu->P & MOS_ZERO, 0);
mos6502_handle_bit(cpu, 65);
cr_assert_eq(cpu->P & MOS_NEGATIVE, 0);
cr_assert_eq(cpu->P & MOS_OVERFLOW, MOS_OVERFLOW);
cr_assert_eq(cpu->P & MOS_ZERO, 0);
mos6502_handle_bit(cpu, 33);
cr_assert_eq(cpu->P & MOS_NEGATIVE, 0);
cr_assert_eq(cpu->P & MOS_OVERFLOW, 0);
cr_assert_eq(cpu->P & MOS_ZERO, 0);
mos6502_handle_bit(cpu, 0);
cr_assert_eq(cpu->P & MOS_NEGATIVE, 0);
cr_assert_eq(cpu->P & MOS_OVERFLOW, 0);
cr_assert_eq(cpu->P & MOS_ZERO, MOS_ZERO);
}
Test(mos6502_bits, bim)
{
// This version of BIT should not modify the NV flags
cpu->P |= MOS_NEGATIVE;
cpu->P |= MOS_OVERFLOW;
cpu->A = 63;
mos6502_handle_bim(cpu, 123);
cr_assert_eq(cpu->P & MOS_ZERO, 0);
cr_assert_eq(cpu->P & MOS_NEGATIVE, MOS_NEGATIVE);
cr_assert_eq(cpu->P & MOS_OVERFLOW, MOS_OVERFLOW);
cpu->A = 4;
mos6502_handle_bim(cpu, 123);
cr_assert_eq(cpu->P & MOS_ZERO, MOS_ZERO);
}
Test(mos6502_bits, eor)
{
cpu->A = 5;
mos6502_handle_eor(cpu, 4);
cr_assert_eq(cpu->A, 1);
cpu->A = 5;
mos6502_handle_eor(cpu, 1);
cr_assert_eq(cpu->A, 4);
}
Test(mos6502_bits, lsr)
{
mos6502_handle_lsr(cpu, 5);
cr_assert_eq(cpu->A, 2);
cr_assert_eq(cpu->P & MOS_CARRY, MOS_CARRY);
cpu->eff_addr = 123;
mos6502_handle_lsr(cpu, 11);
cr_assert_eq(mos6502_get(cpu, 123), 5);
cr_assert_eq(cpu->P & MOS_CARRY, MOS_CARRY);
}
Test(mos6502_bits, ora)
{
cpu->A = 5;
mos6502_handle_ora(cpu, 4);
cr_assert_eq(cpu->A, 5);
cpu->A = 5;
mos6502_handle_ora(cpu, 10);
cr_assert_eq(cpu->A, 15);
}
Test(mos6502_bits, rol)
{
mos6502_handle_rol(cpu, 8);
cr_assert_eq(cpu->A, 17);
cpu->eff_addr = 234;
mos6502_handle_rol(cpu, 128);
cr_assert_eq(mos6502_get(cpu, 234), 0);
}
Test(mos6502_bits, ror)
{
mos6502_handle_ror(cpu, 64);
cr_assert_eq(cpu->A, 160);
cpu->eff_addr = 123;
mos6502_handle_ror(cpu, 1);
mos6502_handle_ror(cpu, 0);
cr_assert_eq(mos6502_get(cpu, 123), 128);
}