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463 lines
13 KiB
C
463 lines
13 KiB
C
/*
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* mos6502.c
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*
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* These functions are kind of the "top-level", if you will, for the MOS
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* 6502 processor. You can create the processor struct, operate on the
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* stack, etc.
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include "log.h"
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#include "mos6502.h"
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// All of our address modes, instructions, etc. are defined here.
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#include "mos6502.enums.h"
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/*
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* This is a table which defines what instruction each opcode is mapped
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* to. All possible (256) values are defined here. You will note many
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* cases where we use NOP where opcodes are not _technically_ defined;
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* this may or may not be the best behavior. It's quite possible we should
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* instead crash the program when we stumble upon such malformed opcodes
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*/
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static int instructions[] = {
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// 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
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BRK, ORA, NOP, NOP, NOP, ORA, ASL, NOP, PHP, ORA, ASL, NOP, NOP, ORA, ASL, NOP, // 0x
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BPL, ORA, NOP, NOP, NOP, ORA, ASL, NOP, CLC, ORA, NOP, NOP, NOP, ORA, ASL, NOP, // 1x
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JSR, AND, NOP, NOP, BIT, AND, ROL, NOP, PLP, AND, ROL, NOP, BIT, AND, ROL, NOP, // 2x
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BMI, AND, NOP, NOP, NOP, AND, ROL, NOP, SEC, AND, NOP, NOP, NOP, AND, ROL, NOP, // 3x
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RTI, EOR, NOP, NOP, NOP, EOR, LSR, NOP, PHA, ADC, LSR, NOP, JMP, EOR, LSR, NOP, // 4x
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BVC, EOR, NOP, NOP, NOP, EOR, LSR, NOP, CLI, EOR, NOP, NOP, NOP, EOR, LSR, NOP, // 5x
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RTS, ADC, NOP, NOP, NOP, ADC, ROR, NOP, PLA, ADC, ROR, NOP, JMP, ADC, ROR, NOP, // 6x
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BVS, ADC, NOP, NOP, NOP, ADC, ROR, NOP, SEI, ADC, NOP, NOP, NOP, ADC, ROR, NOP, // 7x
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NOP, STA, NOP, NOP, STY, STA, STX, NOP, DEY, NOP, TXA, NOP, STY, STA, STX, NOP, // 8x
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BCC, STA, NOP, NOP, STY, STA, STX, NOP, TYA, STA, TXS, NOP, NOP, STA, NOP, NOP, // 9x
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LDY, LDA, LDX, NOP, LDY, LDA, LDX, NOP, TAY, LDA, TAX, NOP, LDY, LDA, LDX, NOP, // Ax
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BCS, LDA, NOP, NOP, LDY, LDA, LDX, NOP, CLV, LDA, TSX, NOP, LDY, LDA, LDX, NOP, // Bx
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CPY, CMP, NOP, NOP, CPY, CMP, DEC, NOP, INY, CMP, DEX, NOP, CPY, CMP, DEC, NOP, // Cx
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BNE, CMP, NOP, NOP, NOP, CMP, DEC, NOP, CLD, CMP, NOP, NOP, NOP, CMP, DEC, NOP, // Dx
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CPX, SBC, NOP, NOP, CPX, SBC, INC, NOP, INX, SBC, NOP, NOP, CPX, SBC, INC, NOP, // Ex
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BEQ, SBC, NOP, NOP, NOP, SBC, INC, NOP, SED, SBC, NOP, NOP, NOP, SBC, INC, NOP, // Fx
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};
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static char *instruction_strings[] = {
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"ADC",
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"AND",
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"ASL",
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"BCC",
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"BCS",
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"BEQ",
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"BIT",
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"BMI",
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"BNE",
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"BPL",
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"BRK",
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"BVC",
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"BVS",
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"CLC",
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"CLD",
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"CLI",
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"CLV",
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"CMP",
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"CPX",
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"CPY",
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"DEC",
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"DEX",
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"DEY",
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"EOR",
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"INC",
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"INX",
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"INY",
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"JMP",
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"JSR",
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"LDA",
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"LDX",
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"LDY",
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"LSR",
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"NOP",
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"ORA",
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"PHA",
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"PHP",
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"PLA",
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"PLP",
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"ROL",
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"ROR",
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"RTI",
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"RTS",
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"SBC",
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"SEC",
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"SED",
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"SEI",
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"STA",
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"STX",
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"STY",
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"TAX",
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"TAY",
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"TSX",
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"TXA",
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"TXS",
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"TYA",
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};
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/*
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* A small convenience for defining instruction handlers below.
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*/
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#define INST_HANDLER(x) \
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mos6502_handle_##x
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/*
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* Here's another table, this time mapping instruction codes to
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* instruction handler functions. They are listed in the order defined
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* in the instruction enum (in mos6502.enums.h).
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*/
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static mos6502_instruction_handler instruction_handlers[] = {
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INST_HANDLER(adc),
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INST_HANDLER(and),
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INST_HANDLER(asl),
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INST_HANDLER(bcc),
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INST_HANDLER(bcs),
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INST_HANDLER(beq),
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INST_HANDLER(bit),
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INST_HANDLER(bmi),
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INST_HANDLER(bne),
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INST_HANDLER(bpl),
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INST_HANDLER(brk),
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INST_HANDLER(bvc),
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INST_HANDLER(bvs),
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INST_HANDLER(clc),
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INST_HANDLER(cld),
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INST_HANDLER(cli),
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INST_HANDLER(clv),
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INST_HANDLER(cmp),
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INST_HANDLER(cpx),
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INST_HANDLER(cpy),
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INST_HANDLER(dec),
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INST_HANDLER(dex),
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INST_HANDLER(dey),
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INST_HANDLER(eor),
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INST_HANDLER(inc),
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INST_HANDLER(inx),
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INST_HANDLER(iny),
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INST_HANDLER(jmp),
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INST_HANDLER(jsr),
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INST_HANDLER(lda),
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INST_HANDLER(ldx),
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INST_HANDLER(ldy),
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INST_HANDLER(lsr),
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INST_HANDLER(nop),
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INST_HANDLER(ora),
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INST_HANDLER(pha),
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INST_HANDLER(php),
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INST_HANDLER(pla),
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INST_HANDLER(plp),
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INST_HANDLER(rol),
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INST_HANDLER(ror),
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INST_HANDLER(rti),
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INST_HANDLER(rts),
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INST_HANDLER(sbc),
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INST_HANDLER(sec),
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INST_HANDLER(sed),
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INST_HANDLER(sei),
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INST_HANDLER(sta),
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INST_HANDLER(stx),
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INST_HANDLER(sty),
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INST_HANDLER(tax),
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INST_HANDLER(tay),
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INST_HANDLER(tsx),
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INST_HANDLER(txa),
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INST_HANDLER(txs),
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INST_HANDLER(tya),
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};
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/*
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* Here we have a table that maps opcodes to the number of cycles each
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* should cost. In cases where no opcode is defined, we set the number
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* of cycles to zero.
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*/
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static int cycles[] = {
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// 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
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7, 6, 0, 0, 0, 3, 5, 0, 3, 2, 2, 0, 0, 4, 6, 0, // 0x
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2, 5, 0, 0, 0, 4, 6, 0, 2, 4, 0, 0, 0, 4, 7, 0, // 1x
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6, 6, 0, 0, 3, 3, 5, 0, 4, 2, 2, 0, 4, 4, 6, 0, // 2x
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2, 5, 0, 0, 0, 4, 6, 0, 2, 4, 0, 0, 0, 4, 7, 0, // 3x
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6, 6, 0, 0, 0, 3, 5, 0, 3, 2, 2, 0, 3, 4, 6, 0, // 4x
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2, 5, 0, 0, 0, 4, 6, 0, 2, 4, 0, 0, 0, 4, 7, 0, // 5x
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6, 6, 0, 0, 0, 3, 5, 0, 4, 2, 2, 0, 5, 4, 6, 0, // 6x
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2, 5, 0, 0, 0, 4, 6, 0, 2, 4, 0, 0, 0, 4, 7, 0, // 7x
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0, 6, 0, 0, 3, 3, 3, 0, 2, 0, 2, 0, 4, 4, 4, 0, // 8x
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2, 6, 0, 0, 4, 4, 4, 0, 2, 5, 2, 0, 0, 5, 0, 0, // 9x
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2, 6, 2, 0, 3, 3, 3, 0, 2, 2, 2, 0, 4, 4, 4, 0, // Ax
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2, 5, 0, 0, 4, 4, 4, 0, 2, 4, 2, 0, 4, 4, 4, 0, // Bx
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2, 6, 0, 0, 3, 3, 5, 0, 2, 2, 2, 0, 4, 4, 3, 0, // Cx
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2, 5, 0, 0, 0, 4, 6, 0, 2, 4, 0, 0, 0, 4, 7, 0, // Dx
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2, 6, 0, 0, 3, 3, 5, 0, 2, 2, 2, 0, 4, 4, 6, 0, // Ex
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2, 5, 0, 0, 0, 4, 6, 0, 2, 4, 0, 0, 0, 4, 7, 0, // Fx
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};
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/*
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* Build a new mos6502 struct object, and also build the memory contents
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* used therein. All registers should be zeroed out.
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*/
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mos6502 *
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mos6502_create()
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{
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mos6502 *cpu;
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cpu = malloc(sizeof(mos6502));
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if (cpu == NULL) {
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log_critical("Not enough memory to allocate mos6502");
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exit(1);
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}
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cpu->memory = vm_segment_create(MOS6502_MEMSIZE);
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cpu->last_addr = 0;
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cpu->PC = 0;
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cpu->A = 0;
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cpu->X = 0;
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cpu->Y = 0;
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cpu->P = 0;
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cpu->S = 0;
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return cpu;
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}
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/*
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* Free the memory consumed by the mos6502 struct.
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*/
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void
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mos6502_free(mos6502 *cpu)
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{
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vm_segment_free(cpu->memory);
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free(cpu);
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}
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/*
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* Return the next byte from the PC register position, and increment the
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* PC register.
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*/
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vm_8bit
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mos6502_next_byte(mos6502 *cpu)
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{
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vm_8bit byte;
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byte = vm_segment_get(cpu->memory, cpu->PC);
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cpu->PC++;
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return byte;
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}
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/*
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* Push a _16-bit_ number to the stack. Generally speaking, only
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* addresses are pushed to the stack, such that would be contained in
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* the PC register (which is 16-bit).
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*
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* The stack is contained within a single page of memory, so you would
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* be right in observing that the stack can contain at most 128, not
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* 256, addresses.
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*/
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void
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mos6502_push_stack(mos6502 *cpu, vm_16bit addr)
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{
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// First we need to set the hi byte, by shifting the address right 8
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// positions and using the base offset of the S register.
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vm_segment_set(cpu->memory, 0x0100 + cpu->S, addr >> 8);
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// Next we must record the lo byte, this time by using a bitmask to
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// capture just the low end of addr, but recording it in S + 1.
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vm_segment_set(cpu->memory, 0x0100 + cpu->S + 1, addr & 0xFF);
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// And finally we need to increment S by 2 (since we've used two
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// bytes in the stack).
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cpu->S += 2;
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}
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/*
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* Pop an address from the stack and return that.
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*/
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vm_16bit
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mos6502_pop_stack(mos6502 *cpu)
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{
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// The first thing we want to do here is to decrement S by 2, since
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// the value we want to return is two positions back.
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cpu->S -= 2;
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// We need to use a bitwise-or operation to combine the hi and lo
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// bytes we retrieve from the stack into the actual position we
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// would use for the PC register.
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return
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(vm_segment_get(cpu->memory, 0x0100 + cpu->S) << 8) |
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vm_segment_get(cpu->memory, 0x0100 + cpu->S + 1);
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}
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/*
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* Here we set the status register to a given status value, regardless
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* of its past contents.
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*/
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void
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mos6502_set_status(mos6502 *cpu, vm_8bit status)
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{
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cpu->P = status;
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}
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/*
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* In contrast, the modify_status function will conditionally set the
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* contents of certain bits, based upon the value of the operand. Those
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* bits are the negative, overflow, carry, and zero flags.
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*/
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void
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mos6502_modify_status(mos6502 *cpu, vm_8bit status, vm_8bit oper)
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{
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if (status & NEGATIVE) {
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cpu->P &= ~NEGATIVE;
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if (oper & 0x80) {
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cpu->P |= NEGATIVE;
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}
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}
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if (status & OVERFLOW) {
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cpu->P &= ~OVERFLOW;
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if (oper & OVERFLOW) {
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cpu->P |= OVERFLOW;
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}
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}
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if (status & CARRY) {
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cpu->P &= ~CARRY;
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if (oper > 0) {
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cpu->P |= CARRY;
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}
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}
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if (status & ZERO) {
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cpu->P &= ~ZERO;
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if (oper == 0) {
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cpu->P |= ZERO;
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}
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}
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}
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/*
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* Return the instruction that is mapped to a given opcode.
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*/
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int
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mos6502_instruction(vm_8bit opcode)
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{
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return instructions[opcode];
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}
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/*
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* Return the number of cycles an opcode may consume. The cpu is a
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* required parameter, because the number of opcodes is conditional upon
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* the effective address of the instruction we're executing.
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*/
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int
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mos6502_cycles(mos6502 *cpu, vm_8bit opcode)
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{
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// In some contexts, we may need to return an additional cycle.
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int modif = 0;
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int addr_mode;
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int lo_addr;
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addr_mode = mos6502_addr_mode(opcode);
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// Mainly we care about the lo byte of the last effective address
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lo_addr = cpu->last_addr & 0xFF;
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// Ok, here's the deal: if you are using an address mode that uses
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// any of the index registers, you need to return an additional
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// cycle if the lo byte of the address plus that index would cross a
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// memory page boundary
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switch (addr_mode) {
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case ABX:
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if (lo_addr + cpu->X > 255) {
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modif = 1;
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}
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break;
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case ABY:
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case INY:
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if (lo_addr + cpu->Y > 255) {
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modif = 1;
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}
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break;
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default:
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break;
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}
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return cycles[opcode] + modif;
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}
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/*
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* Here we intend to return the proper resolver function for any given
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* instruction.
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*/
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mos6502_instruction_handler
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mos6502_get_instruction_handler(vm_8bit opcode)
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{
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return instruction_handlers[mos6502_instruction(opcode)];
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}
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/*
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* This code does the execution step that the 6502 processor would take,
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* from soup to nuts.
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*/
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void
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mos6502_execute(mos6502 *cpu, vm_8bit opcode)
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{
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vm_8bit operand;
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int cycles;
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mos6502_address_resolver resolver;
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mos6502_instruction_handler handler;
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// First, we need to know how to resolve our effective address and
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// how to execute anything.
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resolver = mos6502_get_address_resolver(opcode);
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handler = mos6502_get_instruction_handler(opcode);
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// The operand is the effective operand, the value that the
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// instruction handler cares about (if it cares about any such
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// value). For example, the operand could be the literal value that
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// you pass into an instruction via immediate mode. As a
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// side-effect, resolver will set the last_addr field in cpu to the
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// effective address where the operand can be found in memory, or
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// zero if that does not apply (such as in immediate mode).
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operand = resolver(cpu);
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// Here's where the magic happens. Whatever the instruction does, it
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// happens in the handler function.
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handler(cpu, operand);
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// This will be the number of cycles we should spend on the
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// instruction. Of course, we can execute instructions pretty
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// quickly in a modern architecture, but a lot of code was written
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// with the idea that certain instructions -- in certain address
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// modes -- were more expensive than others, and you want those
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// programs to feel faster or slower in relation to that.
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cycles = mos6502_cycles(cpu, opcode);
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// FIXME: actually emulate the cycles
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// Ok -- we're done! This wasn't so hard, was it?
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return;
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}
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/*
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* Return the next byte in memory according to the program counter
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* register, and then increment the register.
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*/
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vm_8bit
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mos6502_read_byte(mos6502 *cpu)
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{
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vm_8bit byte;
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byte = vm_segment_get(cpu->memory, cpu->PC);
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cpu->PC++;
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return byte;
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}
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