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142 lines
4.4 KiB
C
142 lines
4.4 KiB
C
/*
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* mos6502.enums.h
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* Enums and other symbols for use with the mos 6502
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*
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* We have separated the definitions of address mode types, instruction
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* types, etc. into their own file so that we can include it in our main
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* source file, as well as from our unit test suite, without necessarily
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* adding them to the global namespace throughout the application.
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*/
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#ifndef _MOS6502_ENUMS_H_
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#define _MOS6502_ENUMS_H_
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/*
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* This defines all of the flags that are possible within the status (P)
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* register. Note that there is intentionally _no_ definition for the
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* 6th bit.
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*/
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enum status_flags {
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MOS_CARRY = 1,
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MOS_ZERO = 2,
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MOS_INTERRUPT = 4,
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MOS_DECIMAL = 8,
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MOS_BREAK = 16,
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MOS_UNUSED = 32,
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MOS_OVERFLOW = 64,
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MOS_NEGATIVE = 128,
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};
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#define MOS_NVZ (MOS_NEGATIVE | MOS_OVERFLOW | MOS_ZERO)
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#define MOS_NVZC (MOS_NEGATIVE | MOS_OVERFLOW | MOS_ZERO | MOS_CARRY)
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#define MOS_NZ (MOS_NEGATIVE | MOS_ZERO)
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#define MOS_NZC (MOS_NEGATIVE | MOS_ZERO | MOS_CARRY)
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#define MOS_ZC (MOS_ZERO | MOS_CARRY)
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#define MOS_STATUS_DEFAULT (MOS_NEGATIVE | MOS_OVERFLOW | \
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MOS_INTERRUPT | MOS_ZERO | MOS_CARRY)
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/*
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* Here we define the various address modes that are possible. These do
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* not map to any significant numbers that are documented for the 6502
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* processor; the position of these symbols don't really matter, and are
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* generally (except for `NOA`, no address mode) in alphabetical order.
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*/
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enum addr_mode {
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NOA, // no address mode
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ACC, // accumulator
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ABS, // absolute
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ABX, // absolute x-index
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ABY, // absolute y-index
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BY2, // Consume 2 bytes (for NP2)
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BY3, // Consume 3 bytes (for NP3)
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IMM, // immediate
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IMP, // implied
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IND, // indirect
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IDX, // x-index indirect
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IDY, // indirect y-index
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REL, // relative
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ZPG, // zero page
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ZPX, // zero page x-index
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ZPY, // zero page y-index
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};
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/*
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* These define the various instructions as enum symbols; again, like
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* for address modes, the values of these enums are not actually
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* significant to the 6502 processor, and are only useful to we, the
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* programmers.
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*/
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enum instruction {
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ADC, // ADd with Carry
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AND, // bitwise AND
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ASL, // Arithmetic Shift Left
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BAD, // bad instruction
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BCC, // Branch on Carry Clear
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BCS, // Branch on Carry Set
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BEQ, // Branch on EQual to zero
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BIT, // BIT test
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BIM, // BIt test (imMediate mode) (* not a real instruction in the processor; just used by us)
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BMI, // Branch on MInus
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BNE, // Branch on Not Equal to zero
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BPL, // Branch on PLus
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BRA, // BRanch Always
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BRK, // BReaK (interrupt)
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BVC, // Branch on oVerflow Clear
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BVS, // Branch on oVerflow Set
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CLC, // CLear Carry
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CLD, // CLear Decimal
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CLI, // CLear Interrupt disable
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CLV, // CLear oVerflow
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CMP, // CoMPare
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CPX, // ComPare with X register
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CPY, // ComPare with Y register
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DEC, // DECrement
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DEX, // DEcrement X
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DEY, // DEcrement Y
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EOR, // Exclusive OR
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INC, // INCrement
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INX, // INcrement X
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INY, // INcrement Y
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JMP, // JuMP
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JSR, // Jump to SubRoutine
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LDA, // LoaD Accumulator
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LDX, // LoaD X
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LDY, // LoaD Y
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LSR, // Logical Shift Right
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NOP, // NO oPeration
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NP2, // No oPeration (2 bytes consumed)
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NP3, // No oPeration (3 bytes consumed)
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ORA, // OR with Accumulator
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PHA, // PusH Accumulator
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PHP, // PusH Predicate register
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PHX, // PusH X register
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PHY, // PusH Y register
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PLA, // PulL Accumulator
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PLP, // PulL Predicate register
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PLX, // PulL X register
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PLY, // PulL Y register
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ROL, // ROtate Left
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ROR, // ROtate Right
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RTI, // ReTurn from Interrupt
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RTS, // ReTurn from Subroutine
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SBC, // SuBtract with Carry
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SEC, // SEt Carry
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SED, // SEt Decimal
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SEI, // SEt Interrupt disable
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STA, // STore Accumulator
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STX, // STore X
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STY, // STore Y
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STZ, // STore Zero
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TAX, // Transfer Accumulator to X
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TAY, // Transfer Accumulator to Y
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TRB, // Test and Reset Bits
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TSB, // Test and Set Bits
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TSX, // Transfer Stack register to X
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TXA, // Transfer X to Accumulator
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TXS, // Transfer X to Stack register
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TYA, // Transfer Y to Accumulator
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};
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#endif
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